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Tue, 17 Feb 2026 13:22:49 -0800 (PST) From: Taylor Simpson To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, matheus.bernardino@oss.qualcomm.com, sid.manning@oss.qualcomm.com, marco.liebel@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, ltaylorsimpson@gmail.com Subject: [PATCH v3 1/8] Hexagon (target/hexagon) Properly handle Hexagon CPU version Date: Tue, 17 Feb 2026 14:22:38 -0700 Message-ID: <20260217212245.95321-2-ltaylorsimpson@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260217212245.95321-1-ltaylorsimpson@gmail.com> References: <20260217212245.95321-1-ltaylorsimpson@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=ltaylorsimpson@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771363407344154100 Add the following CPU versions that were previously missing v5 v55 v60 v61 v62 v65 Create a CPUHexagonDef struct to represent the definition of a core Currently contains an enum with the known Hexagon CPU versions Add a field to HexagonCPUClass to note the Hexagon definition Co-authored-by: Matheus Tavares Bernardino Co-authored-by: Brian Cain Signed-off-by: Taylor Simpson Reviewed-by: Anton Johansson --- target/hexagon/cpu-qom.h | 27 +++++++++++++++++++++++ target/hexagon/cpu.h | 2 ++ target/hexagon/cpu.c | 46 ++++++++++++++++++++++++---------------- 3 files changed, 57 insertions(+), 18 deletions(-) diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h index 0b149bd5fe..6e1bb04070 100644 --- a/target/hexagon/cpu-qom.h +++ b/target/hexagon/cpu-qom.h @@ -11,11 +11,38 @@ =20 #include "hw/core/cpu.h" =20 +typedef enum { + HEX_VER_NONE =3D 0x00, + HEX_VER_V5 =3D 0x04, + HEX_VER_V55 =3D 0x05, + HEX_VER_V60 =3D 0x60, + HEX_VER_V61 =3D 0x61, + HEX_VER_V62 =3D 0x62, + HEX_VER_V65 =3D 0x65, + HEX_VER_V66 =3D 0x66, + HEX_VER_V67 =3D 0x67, + HEX_VER_V68 =3D 0x68, + HEX_VER_V69 =3D 0x69, + HEX_VER_V71 =3D 0x71, + HEX_VER_V73 =3D 0x73, + HEX_VER_ANY =3D 0xff, +} HexagonVersion; + +typedef struct { + HexagonVersion hex_version; +} HexagonCPUDef; + #define TYPE_HEXAGON_CPU "hexagon-cpu" =20 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) =20 +#define TYPE_HEXAGON_CPU_V5 HEXAGON_CPU_TYPE_NAME("v5") +#define TYPE_HEXAGON_CPU_V55 HEXAGON_CPU_TYPE_NAME("v55") +#define TYPE_HEXAGON_CPU_V60 HEXAGON_CPU_TYPE_NAME("v60") +#define TYPE_HEXAGON_CPU_V61 HEXAGON_CPU_TYPE_NAME("v61") +#define TYPE_HEXAGON_CPU_V62 HEXAGON_CPU_TYPE_NAME("v62") +#define TYPE_HEXAGON_CPU_V65 HEXAGON_CPU_TYPE_NAME("v65") #define TYPE_HEXAGON_CPU_V66 HEXAGON_CPU_TYPE_NAME("v66") #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") #define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 85afd59277..f99647dfb6 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -117,6 +117,8 @@ typedef struct HexagonCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + + const HexagonCPUDef *hex_def; } HexagonCPUClass; =20 struct ArchCPU { diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 58a22ee41f..949d509a15 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -27,13 +27,6 @@ #include "exec/gdbstub.h" #include "accel/tcg/cpu-ops.h" =20 -static void hexagon_v66_cpu_init(Object *obj) { } -static void hexagon_v67_cpu_init(Object *obj) { } -static void hexagon_v68_cpu_init(Object *obj) { } -static void hexagon_v69_cpu_init(Object *obj) { } -static void hexagon_v71_cpu_init(Object *obj) { } -static void hexagon_v73_cpu_init(Object *obj) { } - static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -377,11 +370,21 @@ static void hexagon_cpu_class_init(ObjectClass *c, co= nst void *data) cc->tcg_ops =3D &hexagon_tcg_ops; } =20 -#define DEFINE_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_HEXAGON_CPU, \ - .instance_init =3D initfn \ +static void hexagon_cpu_class_base_init(ObjectClass *c, const void *data) +{ + HexagonCPUClass *mcc =3D HEXAGON_CPU_CLASS(c); + /* Make sure all CPU models define a HexagonCPUDef */ + g_assert(!object_class_is_abstract(c) && data !=3D NULL); + mcc->hex_def =3D data; +} + +#define DEFINE_CPU(type_name, version) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_HEXAGON_CPU, \ + .class_data =3D &(const HexagonCPUDef) { \ + .hex_version =3D version, \ + } \ } =20 static const TypeInfo hexagon_cpu_type_infos[] =3D { @@ -394,13 +397,20 @@ static const TypeInfo hexagon_cpu_type_infos[] =3D { .abstract =3D true, .class_size =3D sizeof(HexagonCPUClass), .class_init =3D hexagon_cpu_class_init, + .class_base_init =3D hexagon_cpu_class_base_init, }, - DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init), - DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), - DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), - DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init), - DEFINE_CPU(TYPE_HEXAGON_CPU_V71, hexagon_v71_cpu_init), - DEFINE_CPU(TYPE_HEXAGON_CPU_V73, hexagon_v73_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V5, HEX_VER_V5), + DEFINE_CPU(TYPE_HEXAGON_CPU_V55, HEX_VER_V55), + DEFINE_CPU(TYPE_HEXAGON_CPU_V60, HEX_VER_V60), + DEFINE_CPU(TYPE_HEXAGON_CPU_V61, HEX_VER_V61), + DEFINE_CPU(TYPE_HEXAGON_CPU_V62, HEX_VER_V62), + DEFINE_CPU(TYPE_HEXAGON_CPU_V65, HEX_VER_V65), + DEFINE_CPU(TYPE_HEXAGON_CPU_V66, HEX_VER_V66), + DEFINE_CPU(TYPE_HEXAGON_CPU_V67, HEX_VER_V67), + DEFINE_CPU(TYPE_HEXAGON_CPU_V68, HEX_VER_V68), + DEFINE_CPU(TYPE_HEXAGON_CPU_V69, HEX_VER_V69), + DEFINE_CPU(TYPE_HEXAGON_CPU_V71, HEX_VER_V71), + DEFINE_CPU(TYPE_HEXAGON_CPU_V73, HEX_VER_V73), }; =20 DEFINE_TYPES(hexagon_cpu_type_infos) --=20 2.43.0