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([2401:d002:dc0f:2100:4a1:428a:70f2:5844]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1aadca84sm53294155ad.70.2026.02.15.19.44.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Feb 2026 19:44:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771213489; x=1771818289; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PxqU8tvo+gNnuGxhj0o+hsuYHhhpNyvRSdlXMU1ShJM=; b=a5BATFP0fwjnKUHC0eKeI2e0HTvBU+It6bY+SA9txy32AR9Zla7jw80G88sXUaiZtM tlr1M476QTRyWA3j9HwSq2kT5zFj4DVPqYFHPUAGcG3jVtcsfQXsd8V8rr/7QeaOSPI8 P8rPNR4mRNjS9fDUdLZbTT1ues80AnQBScuQEW/2/e+w5e5sPAW5HI9RJ3AAWRaC+Zn0 KIctjpek0XfFcyLF+yHKnNCcI8HYcA4qw4OTRt1GVZmgS6rmasfu1gSVHcMJ3S1x4Xqz P4KS/79F2TaFKjPEgqG5OQPuLv9F/GLbE8c7v0M7xgdyNVx9vSDuqdN+GcfcGJHaqe1u UrJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771213489; x=1771818289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=PxqU8tvo+gNnuGxhj0o+hsuYHhhpNyvRSdlXMU1ShJM=; b=js+5elRdmx72snsKJ3Hql3rlEQUxckK+M6zcq4TM3Z0cjUmciyuyiG92UiHAXun+BF wbvOwcOSWv5F1X9DnkuvX5scELXeoBKzQNfmrfjSNyotAWhKtsPNxU57NEcyTIp2PiZy UcZL8Q+EFDdHQLmglXEbdILhIgvo+2rFVNhB8IxtlIkBgThD5Y6jNQVBwCgUl2ZaVIl4 1tHvj4yoko7fdea00ba3K3hW9ldRF3y0TYO6TwjMZWgQBgaARkj6kNoWUQf+JhPv5tnB I0f7rKA+dbbEpPBlDAmCeEH1FV1x5sI/K8+klzNqcYt1tJVbm8DB3U7xos1lISPmeumZ Rs+Q== X-Gm-Message-State: AOJu0YzEesZiFQ6xMVouQPgF4Rw03VHhQUSqwemARwhxn8Qc0C4Fbi6E CWl+QP6Cg0vhjYOfEj3KN6SskYhjSpsO37inxarktqIa1hOBBFNHv/Pv0Oh3vEfCaFwStig8i46 pet7tZoo= X-Gm-Gg: AZuq6aL+s66iBLQpWYQQomjSySlTWvXBFMMkUgDmPB4SUhi9e2emOSdOfpqT2TA3D0O NwRmjtFgtkHP1CH7MQQYFC6Hki7outrz+YUW/HM2NmODQuurI26u6jOsQNIz3YgnIuVg9rIYgVd q+PIEIVhPP4FGpEga8qxz6C03qZZDkFaRI/Wwr0bKqbrDmE4Mhv492IQ0NAJrXvNzv0AvGMkilc 9WMEIZut+EXtpuYYtTAB1SXwWvgTrx1VQHAcwoCT7Z1U4HoZo5HFqROKeKF1I96wsYv7XgmvRNv Bzg4KM0o069pFFeihZPRwuCY6eeFRgUg1UAG3mI19ldtBANMrBO/SVTFUL4KYk6TGjoxKLQQq2Z d+AxjCAuWAVv6Xk/aEgHGO7o03F0nuYVBPHGcDWNGeX/cbkSYeH14ICpu6SyhW6Igof+d/pckJ7 QV4zISFPquhcK4hMbsrnD2Xa8WGj14ITZR X-Received: by 2002:a17:902:ecc6:b0:2aa:e817:1bd3 with SMTP id d9443c01a7336-2ab505bb034mr94688145ad.29.1771213488652; Sun, 15 Feb 2026 19:44:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [RFC PATCH 05/13] target/arm: Move kvm test out of cpu_arm_set_sve Date: Mon, 16 Feb 2026 13:44:24 +1000 Message-ID: <20260216034432.23912-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260216034432.23912-1-richard.henderson@linaro.org> References: <20260216034432.23912-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771213583355158500 Content-Type: text/plain; charset="utf-8" Introduce a set of stub property callbacks for when we really don't want to be able to enable SVE. Register the real or stub funtions in aarch64_add_sve_properties depending on whether or not SVE is available. Adjust aarch64_a64fx_initfn to initialize the set of supported vector sizes before calling aarch64_add_sve_properties. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++------ target/arm/tcg/cpu64.c | 2 +- 2 files changed, 42 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0116b6cc88..38d06af49f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -292,6 +292,30 @@ static void cpu_arm_set_vq(Object *obj, Visitor *v, co= nst char *name, vq_map->init |=3D 1 << (vq - 1); } =20 +static void prop_bool_get_false(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D false; + visit_type_bool(v, name, &value, errp); +} + +static void prop_bool_set_false(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value; + + if (visit_type_bool(v, name, &value, errp) && value) { + error_setg(errp, "'%s' feature not supported by %s on this host", + name, current_accel_name()); + } +} + +static void prop_add_stub_bool(Object *obj, const char *name) +{ + object_property_add(obj, name, "bool", prop_bool_get_false, + prop_bool_set_false, NULL, NULL); +} + static bool cpu_arm_get_sve(Object *obj, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -301,12 +325,6 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp) static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - - if (value && kvm_enabled() && !kvm_arm_sve_supported()) { - error_setg(errp, "'sve' feature not supported by KVM on this host"= ); - return; - } - FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value); } =20 @@ -439,7 +457,23 @@ void aarch64_add_sve_properties(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); uint32_t vq; =20 - object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); + /* + * For hw virtualization, we have already probed the set of vector + * lengths supported. If there are none, the host doesn't support + * SVE at all. In which case we register a stub property, to allow + * -cpu max,sve=3Doff + * to always be valid. + * + * For TCG, this function is only called for cpu models which + * support SVE. The error message in the stub is written + * assuming host virtualiation is being used. + */ + if (cpu->sve_vq.supported) { + object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_= sve); + } else { + assert(!tcg_enabled()); + prop_add_stub_bool(obj, "sve"); + } =20 for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { char name[8]; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index fa80e48d2b..84857fb706 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -524,10 +524,10 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->gic_pribits =3D 5; =20 /* The A64FX supports only 128, 256 and 512 bit vector lengths */ - aarch64_add_sve_properties(obj); cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ | (1 << 1) /* 256bit */ | (1 << 3); /* 512bit */ + aarch64_add_sve_properties(obj); =20 cpu->isar.reset_pmcr_el0 =3D 0x46014040; =20 --=20 2.43.0