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This probably belongs in asm-arm64/kvm.h */ +#define KVM_REG_ARM64_SME_ZT0 \ + (KVM_REG_ARM64 | KVM_REG_ARM64_SME | \ + KVM_REG_ARM64_SME_ZT_BASE | KVM_REG_SIZE_U512) + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_INFO(DEVICE_CTRL), KVM_CAP_LAST_INFO @@ -2157,10 +2162,39 @@ static int kvm_arch_put_sve(CPUState *cs, uint32_t = vq, bool have_ffr) return 0; } =20 +static int kvm_arch_put_sme(CPUState *cs, uint32_t svq) +{ + CPUARMState *env =3D cpu_env(cs); + ARMCPU *cpu =3D env_archcpu(env); + uint64_t tmp[ARM_MAX_VQ * 2]; + uint64_t *r; + int ret; + + for (int n =3D 0; n < svq * 16; ++n) { + r =3D sve_bswap64(tmp, &env->za_state.za[n].d[0], svq * 2); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SME_ZAHREG(n, 0), r); + if (ret) { + return ret; + } + } + + if (cpu_isar_feature(aa64_sme2, cpu)) { + r =3D sve_bswap64(tmp, env->za_state.zt0, ARRAY_SIZE(env->za_state= .zt0)); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SME_ZT0, r); + if (ret) { + return ret; + } + } + return 0; +} + int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp) { uint64_t val; uint32_t fpr; + bool sme_sm =3D false; + bool sme_za =3D false; + uint32_t svq =3D 0; int i, ret; unsigned int el; =20 @@ -2239,7 +2273,18 @@ int kvm_arch_put_registers(CPUState *cs, KvmPutState= level, Error **errp) } } =20 - if (cpu_isar_feature(aa64_sve, cpu)) { + if (cpu_isar_feature(aa64_sme, cpu)) { + /* Current SVL is required for either SM or ZA */ + sme_sm =3D FIELD_EX64(env->svcr, SVCR, SM); + sme_za =3D FIELD_EX64(env->svcr, SVCR, ZA); + if (sme_sm || sme_za) { + svq =3D sve_vqm1_for_el_sm(env, el, true) + 1; + } + } + + if (sme_sm) { + ret =3D kvm_arch_put_sve(cs, svq, cpu_isar_feature(aa64_sme_fa64, = cpu)); + } else if (cpu_isar_feature(aa64_sve, cpu)) { ret =3D kvm_arch_put_sve(cs, cpu->sve_max_vq, true); } else { ret =3D kvm_arch_put_fpsimd(cs); @@ -2248,6 +2293,13 @@ int kvm_arch_put_registers(CPUState *cs, KvmPutState= level, Error **errp) return ret; } =20 + if (sme_za) { + ret =3D kvm_arch_put_sme(cs, svq); + if (ret) { + return ret; + } + } + fpr =3D vfp_get_fpsr(env); ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); if (ret) { @@ -2342,11 +2394,41 @@ static int kvm_arch_get_sve(CPUState *cs, uint32_t = vq, bool have_ffr) return 0; } =20 +static int kvm_arch_get_sme(CPUState *cs, uint32_t svq) +{ + CPUARMState *env =3D cpu_env(cs); + ARMCPU *cpu =3D env_archcpu(env); + uint64_t *r; + int ret; + + for (int n =3D 0; n < svq * 16; ++n) { + r =3D &env->za_state.za[n].d[0]; + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SME_ZAHREG(n, 0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, svq * 2); + } + + if (cpu_isar_feature(aa64_sme2, cpu)) { + r =3D env->za_state.zt0; + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SME_ZT0, r); + if (ret) { + return ret; + } + sve_bswap64(r, r, ARRAY_SIZE(env->za_state.zt0)); + } + return 0; +} + int kvm_arch_get_registers(CPUState *cs, Error **errp) { uint64_t val; unsigned int el; uint32_t fpr; + bool sme_sm =3D false; + bool sme_za =3D false; + uint32_t svq =3D 0; int i, ret; =20 ARMCPU *cpu =3D ARM_CPU(cs); @@ -2424,7 +2506,18 @@ int kvm_arch_get_registers(CPUState *cs, Error **err= p) env->spsr =3D env->banked_spsr[i]; } =20 - if (cpu_isar_feature(aa64_sve, cpu)) { + if (cpu_isar_feature(aa64_sme, cpu)) { + /* Current SVL is required for either SM or ZA */ + sme_sm =3D FIELD_EX64(env->svcr, SVCR, SM); + sme_za =3D FIELD_EX64(env->svcr, SVCR, ZA); + if (sme_sm || sme_za) { + svq =3D sve_vqm1_for_el_sm(env, el, true) + 1; + } + } + + if (sme_sm) { + ret =3D kvm_arch_get_sve(cs, svq, cpu_isar_feature(aa64_sme_fa64, = cpu)); + } else if (cpu_isar_feature(aa64_sve, cpu)) { ret =3D kvm_arch_get_sve(cs, cpu->sve_max_vq, true); } else { ret =3D kvm_arch_get_fpsimd(cs); @@ -2433,6 +2526,13 @@ int kvm_arch_get_registers(CPUState *cs, Error **err= p) return ret; } =20 + if (sme_za) { + ret =3D kvm_arch_get_sme(cs, svq); + if (ret) { + return ret; + } + } + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); if (ret) { return ret; --=20 2.43.0