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Sun, 15 Feb 2026 14:04:26 -0800 (PST) From: Taylor Simpson To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, matheus.bernardino@oss.qualcomm.com, sid.manning@oss.qualcomm.com, marco.liebel@oss.qualcomm.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, ltaylorsimpson@gmail.com Subject: [PATCH v2 1/8] Hexagon (target/hexagon) Properly handle Hexagon CPU version Date: Sun, 15 Feb 2026 15:04:15 -0700 Message-ID: <20260215220422.212249-2-ltaylorsimpson@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260215220422.212249-1-ltaylorsimpson@gmail.com> References: <20260215220422.212249-1-ltaylorsimpson@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=ltaylorsimpson@gmail.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771193132065158500 Add the following CPU versions that were previously missing v5 v55 v60 v61 v62 v65 Create an enum with the known Hexagon CPU versions Add a field to HexagonCPUClass to note the Hexagon CPU version Co-authored-by: Matheus Tavares Bernardino Co-authored-by: Brian Cain Signed-off-by: Taylor Simpson --- target/hexagon/cpu-qom.h | 23 +++++++++++++++++++++++ target/hexagon/cpu.h | 2 ++ target/hexagon/cpu.c | 28 ++++++++++++++++++++++------ 3 files changed, 47 insertions(+), 6 deletions(-) diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h index 0b149bd5fe..d2f98c683a 100644 --- a/target/hexagon/cpu-qom.h +++ b/target/hexagon/cpu-qom.h @@ -11,11 +11,34 @@ =20 #include "hw/core/cpu.h" =20 +typedef enum { + HEX_VER_NONE =3D 0x00, + HEX_VER_V5 =3D 0x04, + HEX_VER_V55 =3D 0x05, + HEX_VER_V60 =3D 0x60, + HEX_VER_V61 =3D 0x61, + HEX_VER_V62 =3D 0x62, + HEX_VER_V65 =3D 0x65, + HEX_VER_V66 =3D 0x66, + HEX_VER_V67 =3D 0x67, + HEX_VER_V68 =3D 0x68, + HEX_VER_V69 =3D 0x69, + HEX_VER_V71 =3D 0x71, + HEX_VER_V73 =3D 0x73, + HEX_VER_ANY =3D 0xff, +} HexagonVersion; + #define TYPE_HEXAGON_CPU "hexagon-cpu" =20 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) =20 +#define TYPE_HEXAGON_CPU_V5 HEXAGON_CPU_TYPE_NAME("v5") +#define TYPE_HEXAGON_CPU_V55 HEXAGON_CPU_TYPE_NAME("v55") +#define TYPE_HEXAGON_CPU_V60 HEXAGON_CPU_TYPE_NAME("v60") +#define TYPE_HEXAGON_CPU_V61 HEXAGON_CPU_TYPE_NAME("v61") +#define TYPE_HEXAGON_CPU_V62 HEXAGON_CPU_TYPE_NAME("v62") +#define TYPE_HEXAGON_CPU_V65 HEXAGON_CPU_TYPE_NAME("v65") #define TYPE_HEXAGON_CPU_V66 HEXAGON_CPU_TYPE_NAME("v66") #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") #define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 85afd59277..2b8e761c4d 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -117,6 +117,8 @@ typedef struct HexagonCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + + HexagonVersion hex_version; } HexagonCPUClass; =20 struct ArchCPU { diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 58a22ee41f..09a0de3c2f 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -27,12 +27,22 @@ #include "exec/gdbstub.h" #include "accel/tcg/cpu-ops.h" =20 -static void hexagon_v66_cpu_init(Object *obj) { } -static void hexagon_v67_cpu_init(Object *obj) { } -static void hexagon_v68_cpu_init(Object *obj) { } -static void hexagon_v69_cpu_init(Object *obj) { } -static void hexagon_v71_cpu_init(Object *obj) { } -static void hexagon_v73_cpu_init(Object *obj) { } +#define HEX_CPU_INIT(NAME, VER) \ +static void hexagon_##NAME##_cpu_init(Object *obj) \ +{ HEXAGON_CPU_GET_CLASS(obj)->hex_version =3D VER; } + +HEX_CPU_INIT(v5, HEX_VER_V5) +HEX_CPU_INIT(v55, HEX_VER_V55) +HEX_CPU_INIT(v60, HEX_VER_V60) +HEX_CPU_INIT(v61, HEX_VER_V61) +HEX_CPU_INIT(v62, HEX_VER_V62) +HEX_CPU_INIT(v65, HEX_VER_V65) +HEX_CPU_INIT(v66, HEX_VER_V66) +HEX_CPU_INIT(v67, HEX_VER_V67) +HEX_CPU_INIT(v68, HEX_VER_V68) +HEX_CPU_INIT(v69, HEX_VER_V69) +HEX_CPU_INIT(v71, HEX_VER_V71) +HEX_CPU_INIT(v73, HEX_VER_V73) =20 static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model) { @@ -395,6 +405,12 @@ static const TypeInfo hexagon_cpu_type_infos[] =3D { .class_size =3D sizeof(HexagonCPUClass), .class_init =3D hexagon_cpu_class_init, }, + DEFINE_CPU(TYPE_HEXAGON_CPU_V5, hexagon_v5_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V55, hexagon_v55_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V60, hexagon_v60_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V61, hexagon_v61_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V62, hexagon_v62_cpu_init), + DEFINE_CPU(TYPE_HEXAGON_CPU_V65, hexagon_v65_cpu_init), DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init), DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), --=20 2.43.0