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charset="utf-8" From: Nicolin Chen When the guest enables the Event Queue and a vIOMMU is present, allocate a vEVENTQ object so that host-side events related to the vIOMMU can be received and propagated back to the guest. For cold-plugged devices using SMMUv3 acceleration, the vIOMMU is created before the guest boots. In this case, the vEVENTQ is allocated when the guest writes to SMMU_CR0 and sets EVENTQEN =3D 1. If no cold-plugged device exists at boot (i.e. no vIOMMU initially), the vEVENTQ is allocated when a vIOMMU is created, i.e. during the first device hot-plug. Also, rename the local error variable and refactor smmu_writel() to use a single error accumulator with error_propagate(). Event read and propagation will be added in a later patch. Signed-off-by: Nicolin Chen Tested-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen --- hw/arm/smmuv3-accel.c | 61 +++++++++++++++++++++++++++++++++++++++++-- hw/arm/smmuv3-accel.h | 6 +++++ hw/arm/smmuv3.c | 17 +++++++----- 3 files changed, 75 insertions(+), 9 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c19c526fca..d92fcb1a89 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -390,6 +390,19 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void = *cmd, SMMUDevice *sdev, sizeof(Cmd), &entry_num, cmd, errp); } =20 +static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel) +{ + IOMMUFDVeventq *veventq =3D accel->veventq; + + if (!veventq) { + return; + } + close(veventq->veventq_fd); + iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id); + g_free(veventq); + accel->veventq =3D NULL; +} + static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel) { IOMMUFDViommu *viommu =3D accel->viommu; @@ -397,6 +410,7 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *= accel) if (!viommu) { return; } + smmuv3_accel_free_veventq(accel); iommufd_backend_free_id(viommu->iommufd, accel->bypass_hwpt_id); iommufd_backend_free_id(viommu->iommufd, accel->abort_hwpt_id); iommufd_backend_free_id(viommu->iommufd, accel->viommu->viommu_id); @@ -404,6 +418,41 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState = *accel) accel->viommu =3D NULL; } =20 +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp) +{ + SMMUv3AccelState *accel =3D s->s_accel; + IOMMUFDVeventq *veventq; + uint32_t veventq_id; + uint32_t veventq_fd; + + if (!accel || !accel->viommu) { + return true; + } + + if (accel->veventq) { + return true; + } + + if (!smmuv3_eventq_enabled(s)) { + return true; + } + + if (!iommufd_backend_alloc_veventq(accel->viommu->iommufd, + accel->viommu->viommu_id, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, + 1 << s->eventq.log2size, &veventq_i= d, + &veventq_fd, errp)) { + return false; + } + + veventq =3D g_new(IOMMUFDVeventq, 1); + veventq->veventq_id =3D veventq_id; + veventq->veventq_fd =3D veventq_fd; + veventq->viommu =3D accel->viommu; + accel->veventq =3D veventq; + return true; +} + static bool smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **errp) @@ -429,6 +478,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *idev, viommu->viommu_id =3D viommu_id; viommu->s2_hwpt_id =3D s2_hwpt_id; viommu->iommufd =3D idev->iommufd; + accel->viommu =3D viommu; =20 /* * Pre-allocate HWPTs for S1 bypass and abort cases. These will be att= ached @@ -448,14 +498,20 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, goto free_abort_hwpt; } =20 + /* Allocate a vEVENTQ if guest has enabled event queue */ + if (!smmuv3_accel_alloc_veventq(s, errp)) { + goto free_bypass_hwpt; + } + /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */ hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) { - goto free_bypass_hwpt; + goto free_veventq; } - accel->viommu =3D viommu; return true; =20 +free_veventq: + smmuv3_accel_free_veventq(accel); free_bypass_hwpt: iommufd_backend_free_id(idev->iommufd, accel->bypass_hwpt_id); free_abort_hwpt: @@ -463,6 +519,7 @@ free_abort_hwpt: free_viommu: iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); g_free(viommu); + accel->viommu =3D NULL; return false; } =20 diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index a8a64802ec..dba6c71de5 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -22,6 +22,7 @@ */ typedef struct SMMUv3AccelState { IOMMUFDViommu *viommu; + IOMMUFDVeventq *veventq; uint32_t bypass_hwpt_id; uint32_t abort_hwpt_id; QLIST_HEAD(, SMMUv3AccelDevice) device_list; @@ -50,6 +51,7 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error = **errp); bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sde= v, Error **errp); void smmuv3_accel_idr_override(SMMUv3State *s); +bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); void smmuv3_accel_reset(SMMUv3State *s); #else static inline void smmuv3_accel_init(SMMUv3State *s) @@ -80,6 +82,10 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SM= MUDevice *sdev, static inline void smmuv3_accel_idr_override(SMMUv3State *s) { } +static inline bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp) +{ + return true; +} static inline void smmuv3_accel_reset(SMMUv3State *s) { } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c08d58c579..f804d3af25 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1597,14 +1597,17 @@ static MemTxResult smmu_writell(SMMUv3State *s, hwa= ddr offset, static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset, uint64_t data, MemTxAttrs attrs) { - Error *local_err =3D NULL; + Error *err =3D NULL, *local_err =3D NULL; =20 switch (offset) { case A_CR0: s->cr[0] =3D data; s->cr0ack =3D data & ~SMMU_CR0_RESERVED; /* in case the command queue has been enabled */ - smmuv3_cmdq_consume(s, &local_err); + smmuv3_cmdq_consume(s, &err); + /* Allocate vEVENTQ if EVENTQ is enabled and a vIOMMU is available= */ + smmuv3_accel_alloc_veventq(s, &local_err); + error_propagate(&err, local_err); break; case A_CR1: s->cr[1] =3D data; @@ -1621,7 +1624,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr= offset, * By acknowledging the CMDQ_ERR, SW may notify cmds can * be processed again */ - smmuv3_cmdq_consume(s, &local_err); + smmuv3_cmdq_consume(s, &err); break; case A_GERROR_IRQ_CFG0: /* 64b */ s->gerror_irq_cfg0 =3D deposit64(s->gerror_irq_cfg0, 0, 32, data); @@ -1643,7 +1646,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr= offset, if (data & R_GBPA_UPDATE_MASK) { /* Ignore update bit as write is synchronous. */ s->gbpa =3D data & ~R_GBPA_UPDATE_MASK; - smmuv3_accel_attach_gbpa_hwpt(s, &local_err); + smmuv3_accel_attach_gbpa_hwpt(s, &err); } break; case A_STRTAB_BASE: /* 64b */ @@ -1671,7 +1674,7 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr= offset, break; case A_CMDQ_PROD: s->cmdq.prod =3D data; - smmuv3_cmdq_consume(s, &local_err); + smmuv3_cmdq_consume(s, &err); break; case A_CMDQ_CONS: s->cmdq.cons =3D data; @@ -1711,8 +1714,8 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr= offset, break; } =20 - if (local_err) { - error_report_err(local_err); + if (err) { + error_report_err(err); } return MEMTX_OK; } --=20 2.43.0