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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1770932420; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kzNIMoMsZQLW9k2rl05Uvtl5Z3XBb7ZfckzwPkttOsg=; b=Q2Rn2ctWGe3VBm1I9VzhM3vfSJ18a6M8NFbQrRz/cWR3veG1O2zsHIViAIOcTgaYYe4Y3J LmpuQ3HoBiIyFo+71a80LOciLvzypsQCyt3EXYwOMM4cYO9V15gyAKT09E4Qd5f+NPXd50 kJHXSo+J/LLyTb/Nb+l0toqU0BRoX6g= X-MC-Unique: E8WzIMWTNPmMExCZNc_XdA-1 X-Mimecast-MFC-AGG-ID: E8WzIMWTNPmMExCZNc_XdA_1770932417 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PULL 08/16] hw/arm/aspeed_ast27x0: Add AST2700 A2 SoC support Date: Thu, 12 Feb 2026 22:39:47 +0100 Message-ID: <20260212213955.2225662-9-clg@redhat.com> In-Reply-To: <20260212213955.2225662-1-clg@redhat.com> References: <20260212213955.2225662-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1770932518416158500 From: Jamin Lin AST2700 A2 is functionally identical to AST2700 A1. There are no changes to the IRQ layout, memory map, or peripheral configuration. The only difference is the silicon revision. This commit introduces a dedicated AST2700 A2 SoC type by reusing the existing AST2700 A1 implementation and setting the A2 silicon revision accordingly. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan Link: https://lore.kernel.org/qemu-devel/20260211021527.119674-4-jamin_lin@= aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast27x0.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 61790ea1cc2b..87dcb82e1b01 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -1166,6 +1166,36 @@ static void aspeed_soc_ast2700a1_class_init(ObjectCl= ass *oc, const void *data) sc->memmap =3D aspeed_soc_ast2700_memmap; } =20 +static void aspeed_soc_ast2700a2_class_init(ObjectClass *oc, const void *d= ata) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a35"), + NULL + }; + DeviceClass *dc =3D DEVICE_CLASS(oc); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(oc); + + /* Reason: The Aspeed SoC can only be instantiated from a board */ + dc->user_creatable =3D false; + dc->realize =3D aspeed_soc_ast2700_realize; + + sc->valid_cpu_types =3D valid_cpu_types; + sc->silicon_rev =3D AST2700_A2_SILICON_REV; + sc->sram_size =3D 0x20000; + sc->pcie_num =3D 3; + sc->spis_num =3D 3; + sc->sgpio_num =3D 2; + sc->ehcis_num =3D 4; + sc->wdts_num =3D 8; + sc->macs_num =3D 3; + sc->uarts_num =3D 13; + sc->num_cpus =3D 4; + sc->ioexp_num =3D 2; + sc->uarts_base =3D ASPEED_DEV_UART0; + sc->irqmap =3D aspeed_soc_ast2700a1_irqmap; + sc->memmap =3D aspeed_soc_ast2700_memmap; +} + static const TypeInfo aspeed_soc_ast27x0_types[] =3D { { .name =3D TYPE_ASPEED27X0_SOC, @@ -1179,6 +1209,12 @@ static const TypeInfo aspeed_soc_ast27x0_types[] =3D= { .instance_init =3D aspeed_soc_ast2700_init, .class_init =3D aspeed_soc_ast2700a1_class_init, }, + { + .name =3D "ast2700-a2", + .parent =3D TYPE_ASPEED27X0_SOC, + .instance_init =3D aspeed_soc_ast2700_init, + .class_init =3D aspeed_soc_ast2700a2_class_init, + }, }; =20 DEFINE_TYPES(aspeed_soc_ast27x0_types) --=20 2.53.0