From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826157; cv=none; d=zohomail.com; s=zohoarc; b=cViJACyoeoNGQXh6jGwMKQjatdIhqQYGNb0b0pXCz447xopAL1xkyN4sQN4vhpPl8GSz/06A9S0eEYynuaPFbublRAWxt28WQbkFqS9ta4tCqQvUFyTHTajAKy2sbSlOm7rsWMj5sVV31jR+r+qzjmi8U3trv6WuvefAHKJqWuQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770826157; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Vs8TfYEFZWl0Kw+1FaZkTbpkVSYR/jFdpRr5z4bKU6o=; b=JoBzXEqisb5EPItRHmHzixOa/ATZXzJ3CcgGbKvS0yOm21dOArqOqUaw/4MbGZaFftQKCa4S+1ArWOUWoSXvOGHUa00vzk32JlinXgcYoZmqBegVI9cLY1uTeB21skBDxHQ+2kS1Rd3ofOQmBszlamQyYhiuQHMFvVx/2WdK0/0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770826157583423.92213346343715; Wed, 11 Feb 2026 08:09:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vqCke-0002pl-So; Wed, 11 Feb 2026 11:07:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vqCXl-0007DC-6H for qemu-devel@nongnu.org; Wed, 11 Feb 2026 10:54:21 -0500 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vqCXj-0003Pk-1F for qemu-devel@nongnu.org; Wed, 11 Feb 2026 10:54:20 -0500 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.59]) by linux.microsoft.com (Postfix) with ESMTPSA id F266C20B7168; Wed, 11 Feb 2026 07:54:15 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com F266C20B7168 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1770825257; bh=Vs8TfYEFZWl0Kw+1FaZkTbpkVSYR/jFdpRr5z4bKU6o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SEADzxsr5ex2AT9kb2p1Hi+OzePBSDhTqYCmiXcfMxH0VnUCXsZ2ZAAEFDeAOf2Cc oTM19kF8NcqFKxMGvHRt8Cx9Km3Xhs69zcTRyzXa0I7o5zyN0Na433/7yyKOqs5em0 FzTSE3di64/gXhE9yEv3bUtXYldvJFBDlmf20V5o= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Wei Liu , Zhao Liu , Paolo Bonzini , Magnus Kulke Subject: [PATCH 01/10] MAINTAINERS: fix magnuskulke email-address Date: Wed, 11 Feb 2026 16:54:01 +0100 Message-Id: <20260211155410.203883-2-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> References: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 11 Feb 2026 11:07:29 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1770826159878158500 Content-Type: text/plain; charset="utf-8" Consolidating email aliases. Signed-off-by: Magnus Kulke --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 29f88d48f3..6272d32ed4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -569,7 +569,7 @@ F: accel/stubs/whpx-stub.c F: include/system/whpx.h =20 MSHV -M: Magnus Kulke +M: Magnus Kulke R: Wei Liu S: Supported F: accel/mshv/ @@ -578,7 +578,7 @@ F: include/hw/hyperv/hvgdk*.h F: include/hw/hyperv/hvhdk*.h =20 X86 MSHV CPUs -M: Magnus Kulke +M: Magnus Kulke R: Wei Liu S: Supported F: target/i386/mshv/ --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826127; cv=none; d=zohomail.com; s=zohoarc; b=l0RXwDzCqnfIloP+6/eqk1rYvVsM9XzdKmVAYBQ6k5HV1TC/bL6UrieTVHwPU9bAZKetzY0kCES/a/HJJlXes6gsBEimUCoTUWFM7zBC3O3r9elLs+DIwGapv1m6aE9OqXXIKCVRSI7R6JluD1nTPhFkqZG5vw2UFgqjUrXIss4= ARC-Message-Signature: i=1; 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charset="utf-8" The uapi definitions are marked with __packed hints in the kernel headers, since we want to keep the contract of the Microsoft Hypervisor ABI explicit, we should also added them in our vendored files, with a few notable exceptions where the attribute is a noop. Signed-off-by: Magnus Kulke --- include/hw/hyperv/hvgdk_mini.h | 37 ++++++++++++++++++++++------------ include/hw/hyperv/hvhdk.h | 14 +++++++------ 2 files changed, 32 insertions(+), 19 deletions(-) diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index cb52cc9de2..7d7b2e9b36 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -7,6 +7,8 @@ #ifndef HW_HYPERV_HVGDK_MINI_H #define HW_HYPERV_HVGDK_MINI_H =20 +#include "qemu/compiler.h" + #define MSHV_IOCTL 0xB8 =20 typedef enum hv_register_name { @@ -211,7 +213,7 @@ enum hv_intercept_type { struct hv_u128 { uint64_t low_part; uint64_t high_part; -}; +} QEMU_PACKED; =20 union hv_x64_xmm_control_status_register { struct hv_u128 as_uint128; @@ -326,13 +328,13 @@ typedef struct hv_x64_segment_register { }; uint16_t attributes; }; -} hv_x64_segment_register; +} QEMU_PACKED hv_x64_segment_register; =20 typedef struct hv_x64_table_register { uint16_t pad[3]; uint16_t limit; uint64_t base; -} hv_x64_table_register; +} QEMU_PACKED hv_x64_table_register; =20 union hv_x64_fp_control_status_register { struct hv_u128 as_uint128; @@ -416,6 +418,10 @@ typedef union hv_register_value { union hv_x64_register_sev_control sev_control; } hv_register_value; =20 +/* + * This struct is __packed in the kernel. Since all members are naturally + * aligned, we can omit QEMU_PACKED to avoid address-of-packed-member warn= ings. + */ typedef struct hv_register_assoc { uint32_t name; /* enum hv_register_name */ uint32_t reserved1; @@ -439,7 +445,7 @@ typedef struct hv_input_get_vp_registers { uint8_t rsvd_z8; uint16_t rsvd_z16; uint32_t names[]; -} hv_input_get_vp_registers; +} QEMU_PACKED hv_input_get_vp_registers; =20 typedef struct hv_input_set_vp_registers { uint64_t partition_id; @@ -448,7 +454,7 @@ typedef struct hv_input_set_vp_registers { uint8_t rsvd_z8; uint16_t rsvd_z16; struct hv_register_assoc elements[]; -} hv_input_set_vp_registers; +} QEMU_PACKED hv_input_set_vp_registers; =20 union hv_interrupt_control { uint64_t as_uint64; @@ -468,7 +474,7 @@ struct hv_input_assert_virtual_interrupt { uint8_t target_vtl; uint8_t rsvd_z0; uint16_t rsvd_z1; -}; +} QEMU_PACKED; =20 /* /dev/mshv */ #define MSHV_CREATE_PARTITION _IOW(MSHV_IOCTL, 0x00, struct mshv_create_= partition) @@ -487,6 +493,11 @@ struct hv_input_assert_virtual_interrupt { ******************************** */ =20 +/* + * This struct is __packed in the kernel, but since all members are natura= lly + * aligned, so we can omit QEMU_PACKED to avoid address-of-packed-member + * warnings. + */ struct hv_local_interrupt_controller_state { /* HV_X64_INTERRUPT_CONTROLLER_STATE */ uint32_t apic_id; @@ -644,7 +655,7 @@ struct hv_x64_intercept_message_header { struct hv_x64_segment_register cs_segment; uint64_t rip; uint64_t rflags; -}; +} QEMU_PACKED; =20 union hv_x64_io_port_access_info { uint8_t as_uint8; @@ -669,7 +680,7 @@ typedef struct hv_x64_io_port_intercept_message { uint64_t rcx; uint64_t rsi; uint64_t rdi; -} hv_x64_io_port_intercept_message; +} QEMU_PACKED hv_x64_io_port_intercept_message; =20 union hv_x64_memory_access_info { uint8_t as_uint8; @@ -692,7 +703,7 @@ struct hv_x64_memory_intercept_message { uint64_t guest_virtual_address; uint64_t guest_physical_address; uint8_t instruction_bytes[16]; -}; +} QEMU_PACKED; =20 union hv_message_flags { uint8_t asu8; @@ -711,14 +722,14 @@ struct hv_message_header { uint64_t sender; union hv_port_id port; }; -}; +} QEMU_PACKED; =20 struct hv_message { struct hv_message_header header; union { uint64_t payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT]; } u; -}; +} QEMU_PACKED; =20 /* From github.com/rust-vmm/mshv-bindings/src/x86_64/regs.rs */ =20 @@ -731,13 +742,13 @@ struct hv_cpuid_entry { uint32_t ecx; uint32_t edx; uint32_t padding[3]; -}; +} QEMU_PACKED; =20 struct hv_cpuid { uint32_t nent; uint32_t padding; struct hv_cpuid_entry entries[0]; -}; +} QEMU_PACKED; =20 #define IA32_MSR_TSC 0x00000010 #define IA32_MSR_EFER 0xC0000080 diff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h index 866c8211bf..bf2f8cbc27 100644 --- a/include/hw/hyperv/hvhdk.h +++ b/include/hw/hyperv/hvhdk.h @@ -9,6 +9,8 @@ #ifndef HW_HYPERV_HVHDK_H #define HW_HYPERV_HVHDK_H =20 +#include "qemu/compiler.h" + #define HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS 1 =20 struct hv_input_set_partition_property { @@ -16,7 +18,7 @@ struct hv_input_set_partition_property { uint32_t property_code; /* enum hv_partition_property_code */ uint32_t padding; uint64_t property_value; -}; +} QEMU_PACKED; =20 union hv_partition_synthetic_processor_features { uint64_t as_uint64[HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS]; @@ -201,12 +203,12 @@ typedef struct hv_input_translate_virtual_address { uint32_t padding; uint64_t control_flags; uint64_t gva_page; -} hv_input_translate_virtual_address; +} QEMU_PACKED hv_input_translate_virtual_address; =20 typedef struct hv_output_translate_virtual_address { union hv_translate_gva_result translation_result; uint64_t gpa_page; -} hv_output_translate_virtual_address; +} QEMU_PACKED hv_output_translate_virtual_address; =20 typedef struct hv_register_x64_cpuid_result_parameters { struct { @@ -226,13 +228,13 @@ typedef struct hv_register_x64_cpuid_result_parameter= s { uint32_t edx; uint32_t edx_mask; } result; -} hv_register_x64_cpuid_result_parameters; +} QEMU_PACKED hv_register_x64_cpuid_result_parameters; =20 typedef struct hv_register_x64_msr_result_parameters { uint32_t msr_index; uint32_t access_type; uint32_t action; /* enum hv_unimplemented_msr_action */ -} hv_register_x64_msr_result_parameters; +} QEMU_PACKED hv_register_x64_msr_result_parameters; =20 union hv_register_intercept_result_parameters { struct hv_register_x64_cpuid_result_parameters cpuid; @@ -244,6 +246,6 @@ typedef struct hv_input_register_intercept_result { uint32_t vp_index; uint32_t intercept_type; /* enum hv_intercept_type */ union hv_register_intercept_result_parameters parameters; -} hv_input_register_intercept_result; +} QEMU_PACKED hv_input_register_intercept_result; =20 #endif /* HW_HYPERV_HVHDK_H */ --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826113; cv=none; d=zohomail.com; s=zohoarc; b=Zw7bHOznkOui2OJ9GA1XDvFTly14vZA+O2Rd+BdIS68XV3BD7XkirTs/bh7XhHbVp2W00kWwnmqS0KB6FPiQ7I4ClomslBwWBLD2p5CrzFD71Oj6EytG9FgyNlNVoQ55hZw/ewTbIVCn6GsaB2HL2Mw6q1x+uSRrkrKcjMM/VBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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charset="utf-8" When using the extended request format we can instruct the hypervisor to provision enough space for requested XSAVE features. This is required for supporting QEMU models provided via the -cpu flag properly. Signed-off-by: Magnus Kulke --- accel/mshv/mshv-all.c | 35 +++++-- include/hw/hyperv/hvgdk_mini.h | 2 + include/hw/hyperv/hvhdk.h | 185 +++++++++++++++++++++++++++++++++ 3 files changed, 214 insertions(+), 8 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index bed0fa298e..8446f7128a 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -112,19 +112,38 @@ static int resume_vm(int vm_fd) =20 static int create_partition(int mshv_fd, int *vm_fd) { - int ret; - struct mshv_create_partition args =3D {0}; + int ret, i; + uint64_t pt_flags; + union hv_partition_processor_xsave_features disabled_xsave_features; + union hv_partition_processor_features disabled_processor_features; + struct mshv_create_partition_v2 args =3D {0}; =20 /* Initialize pt_flags with the desired features */ - uint64_t pt_flags =3D (1ULL << MSHV_PT_BIT_LAPIC) | - (1ULL << MSHV_PT_BIT_X2APIC) | - (1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES); + pt_flags =3D (1ULL << MSHV_PT_BIT_LAPIC) | + (1ULL << MSHV_PT_BIT_X2APIC) | + (1ULL << MSHV_PT_BIT_GPA_SUPER_PAGES) | + (1ULL << MSHV_PT_BIT_CPU_AND_XSAVE_FEATURES); =20 - /* Set default isolation type */ - uint64_t pt_isolation =3D MSHV_PT_ISOLATION_NONE; + /* enable all */ + disabled_xsave_features.as_uint64 =3D 0; =20 + /* Enable all proc features by default */ + for (i =3D 0; i < MSHV_NUM_CPU_FEATURES_BANKS; i++) { + disabled_processor_features.as_uint64[i] =3D 0; + } + disabled_processor_features.reserved_bank0 =3D 1; + for (i =3D 0; i < MSHV_NUM_CPU_FEATURES_BANKS; i++) { + disabled_processor_features.as_uint64[i] =3D 0; + } + + /* populate args structure */ args.pt_flags =3D pt_flags; - args.pt_isolation =3D pt_isolation; + args.pt_isolation =3D MSHV_PT_ISOLATION_NONE; + args.pt_disabled_xsave =3D disabled_xsave_features.as_uint64; + args.pt_num_cpu_fbanks =3D MSHV_NUM_CPU_FEATURES_BANKS; + for (i =3D 0; i < MSHV_NUM_CPU_FEATURES_BANKS; i++) { + args.pt_cpu_fbanks[i] =3D disabled_processor_features.as_uint64[i]; + } =20 ret =3D ioctl(mshv_fd, MSHV_CREATE_PARTITION, &args); if (ret < 0) { diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index 7d7b2e9b36..a8d4b2b2b1 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -456,6 +456,8 @@ typedef struct hv_input_set_vp_registers { struct hv_register_assoc elements[]; } QEMU_PACKED hv_input_set_vp_registers; =20 +#define MSHV_VP_MAX_REGISTERS 128 + union hv_interrupt_control { uint64_t as_uint64; struct { diff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h index bf2f8cbc27..83f12a8781 100644 --- a/include/hw/hyperv/hvhdk.h +++ b/include/hw/hyperv/hvhdk.h @@ -163,6 +163,191 @@ union hv_partition_synthetic_processor_features { }; }; =20 +union hv_partition_processor_xsave_features { + struct { + uint64_t xsave_support:1; + uint64_t xsaveopt_support:1; + uint64_t avx_support:1; + uint64_t avx2_support:1; + uint64_t fma_support:1; + uint64_t mpx_support:1; + uint64_t avx512_support:1; + uint64_t avx512_dq_support:1; + uint64_t avx512_cd_support:1; + uint64_t avx512_bw_support:1; + uint64_t avx512_vl_support:1; + uint64_t xsave_comp_support:1; + uint64_t xsave_supervisor_support:1; + uint64_t xcr1_support:1; + uint64_t avx512_bitalg_support:1; + uint64_t avx512_i_fma_support:1; + uint64_t avx512_v_bmi_support:1; + uint64_t avx512_v_bmi2_support:1; + uint64_t avx512_vnni_support:1; + uint64_t gfni_support:1; + uint64_t vaes_support:1; + uint64_t avx512_v_popcntdq_support:1; + uint64_t vpclmulqdq_support:1; + uint64_t avx512_bf16_support:1; + uint64_t avx512_vp2_intersect_support:1; + uint64_t avx512_fp16_support:1; + uint64_t xfd_support:1; + uint64_t amx_tile_support:1; + uint64_t amx_bf16_support:1; + uint64_t amx_int8_support:1; + uint64_t avx_vnni_support:1; + uint64_t avx_ifma_support:1; + uint64_t avx_ne_convert_support:1; + uint64_t avx_vnni_int8_support:1; + uint64_t avx_vnni_int16_support:1; + uint64_t avx10_1_256_support:1; + uint64_t avx10_1_512_support:1; + uint64_t amx_fp16_support:1; + uint64_t reserved1:26; + }; + uint64_t as_uint64; +}; + +#define HV_PARTITION_PROCESSOR_FEATURES_BANKS 2 +#define HV_PARTITION_PROCESSOR_FEATURES_RESERVEDBANK1_BITFIELD_COUNT 4 + + +union hv_partition_processor_features { + uint64_t as_uint64[HV_PARTITION_PROCESSOR_FEATURES_BANKS]; + struct { + uint64_t sse3_support:1; + uint64_t lahf_sahf_support:1; + uint64_t ssse3_support:1; + uint64_t sse4_1_support:1; + uint64_t sse4_2_support:1; + uint64_t sse4a_support:1; + uint64_t xop_support:1; + uint64_t pop_cnt_support:1; + uint64_t cmpxchg16b_support:1; + uint64_t altmovcr8_support:1; + uint64_t lzcnt_support:1; + uint64_t mis_align_sse_support:1; + uint64_t mmx_ext_support:1; + uint64_t amd3dnow_support:1; + uint64_t extended_amd3dnow_support:1; + uint64_t page_1gb_support:1; + uint64_t aes_support:1; + uint64_t pclmulqdq_support:1; + uint64_t pcid_support:1; + uint64_t fma4_support:1; + uint64_t f16c_support:1; + uint64_t rd_rand_support:1; + uint64_t rd_wr_fs_gs_support:1; + uint64_t smep_support:1; + uint64_t enhanced_fast_string_support:1; + uint64_t bmi1_support:1; + uint64_t bmi2_support:1; + uint64_t hle_support_deprecated:1; + uint64_t rtm_support_deprecated:1; + uint64_t movbe_support:1; + uint64_t npiep1_support:1; + uint64_t dep_x87_fpu_save_support:1; + uint64_t rd_seed_support:1; + uint64_t adx_support:1; + uint64_t intel_prefetch_support:1; + uint64_t smap_support:1; + uint64_t hle_support:1; + uint64_t rtm_support:1; + uint64_t rdtscp_support:1; + uint64_t clflushopt_support:1; + uint64_t clwb_support:1; + uint64_t sha_support:1; + uint64_t x87_pointers_saved_support:1; + uint64_t invpcid_support:1; + uint64_t ibrs_support:1; + uint64_t stibp_support:1; + uint64_t ibpb_support:1; + uint64_t unrestricted_guest_support:1; + uint64_t mdd_support:1; + uint64_t fast_short_rep_mov_support:1; + uint64_t l1dcache_flush_support:1; + uint64_t rdcl_no_support:1; + uint64_t ibrs_all_support:1; + uint64_t skip_l1df_support:1; + uint64_t ssb_no_support:1; + uint64_t rsb_a_no_support:1; + uint64_t virt_spec_ctrl_support:1; + uint64_t rd_pid_support:1; + uint64_t umip_support:1; + uint64_t mbs_no_support:1; + uint64_t mb_clear_support:1; + uint64_t taa_no_support:1; + uint64_t tsx_ctrl_support:1; + uint64_t reserved_bank0:1; + + /* N.B. Begin bank 1 processor features. */ + uint64_t a_count_m_count_support:1; + uint64_t tsc_invariant_support:1; + uint64_t cl_zero_support:1; + uint64_t rdpru_support:1; + uint64_t la57_support:1; + uint64_t mbec_support:1; + uint64_t nested_virt_support:1; + uint64_t psfd_support:1; + uint64_t cet_ss_support:1; + uint64_t cet_ibt_support:1; + uint64_t vmx_exception_inject_support:1; + uint64_t enqcmd_support:1; + uint64_t umwait_tpause_support:1; + uint64_t movdiri_support:1; + uint64_t movdir64b_support:1; + uint64_t cldemote_support:1; + uint64_t serialize_support:1; + uint64_t tsc_deadline_tmr_support:1; + uint64_t tsc_adjust_support:1; + uint64_t fzl_rep_movsb:1; + uint64_t fs_rep_stosb:1; + uint64_t fs_rep_cmpsb:1; + uint64_t tsx_ld_trk_support:1; + uint64_t vmx_ins_outs_exit_info_support:1; + uint64_t hlat_support:1; + uint64_t sbdr_ssdp_no_support:1; + uint64_t fbsdp_no_support:1; + uint64_t psdp_no_support:1; + uint64_t fb_clear_support:1; + uint64_t btc_no_support:1; + uint64_t ibpb_rsb_flush_support:1; + uint64_t stibp_always_on_support:1; + uint64_t perf_global_ctrl_support:1; + uint64_t npt_execute_only_support:1; + uint64_t npt_ad_flags_support:1; + uint64_t npt1_gb_page_support:1; + uint64_t amd_processor_topology_node_id_support:1; + uint64_t local_machine_check_support:1; + uint64_t extended_topology_leaf_fp256_amd_support:1; + uint64_t gds_no_support:1; + uint64_t cmpccxadd_support:1; + uint64_t tsc_aux_virtualization_support:1; + uint64_t rmp_query_support:1; + uint64_t bhi_no_support:1; + uint64_t bhi_dis_support:1; + uint64_t prefetch_i_support:1; + uint64_t sha512_support:1; + uint64_t mitigation_ctrl_support:1; + uint64_t rfds_no_support:1; + uint64_t rfds_clear_support:1; + uint64_t sm3_support:1; + uint64_t sm4_support:1; + uint64_t secure_avic_support:1; + uint64_t guest_intercept_ctrl_support:1; + uint64_t sbpb_supported:1; + uint64_t ibpb_br_type_supported:1; + uint64_t srso_no_supported:1; + uint64_t srso_user_kernel_no_supported:1; + uint64_t vrew_clear_supported:1; + uint64_t tsa_l1_no_supported:1; + uint64_t tsa_sq_no_supported:1; + uint64_t lass_support:1; + uint64_t idle_hlt_intercept_support:1; + uint64_t msr_list_support:1; + }; +}; + enum hv_translate_gva_result_code { HV_TRANSLATE_GVA_SUCCESS =3D 0, =20 --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826155; cv=none; d=zohomail.com; s=zohoarc; b=cTTJm197lJlzltH7mxhkYFQgeDJlpdA11BrB/t2GiGbSPdi3/gQi6Ca2FEDGGkajoZUDOXhCPE4RzIo7hN6gjfM0H2MxHBODbdvx9a9EXOsuJ2/G6jPjVKTpodh8adw5h9xrlMjmoM4wBzjPOjBc/7J87ITQcMByHhfddY8ySvk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770826155; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" The list argument was missing a pointer and hence e.g. -cpu qemu64 and -cpu EPYC would produce the same of cpuid leaves. Signed-off-by: Magnus Kulke Acked-by: Wei Liu (Microsoft) --- target/i386/mshv/mshv-cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 586383b882..5c46cd67ec 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -441,7 +441,7 @@ int mshv_load_regs(CPUState *cpu) return 0; } =20 -static void add_cpuid_entry(GList *cpuid_entries, +static void add_cpuid_entry(GList **cpuid_entries, uint32_t function, uint32_t index, uint32_t eax, uint32_t ebx, uint32_t ecx, uint32_t edx) @@ -456,10 +456,10 @@ static void add_cpuid_entry(GList *cpuid_entries, entry->ecx =3D ecx; entry->edx =3D edx; =20 - cpuid_entries =3D g_list_append(cpuid_entries, entry); + *cpuid_entries =3D g_list_append(*cpuid_entries, entry); } =20 -static void collect_cpuid_entries(const CPUState *cpu, GList *cpuid_entrie= s) +static void collect_cpuid_entries(const CPUState *cpu, GList **cpuid_entri= es) { X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; @@ -615,7 +615,7 @@ static int set_cpuid2(const CPUState *cpu) struct hv_cpuid_entry *entry; GList *entries =3D NULL; =20 - collect_cpuid_entries(cpu, entries); + collect_cpuid_entries(cpu, &entries); n_entries =3D g_list_length(entries); =20 cpuid_size =3D sizeof(struct hv_cpuid) --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826082; cv=none; d=zohomail.com; s=zohoarc; b=BrhW8X6p2a6o3l7BdK1IZGHG71E1nIGv3n7M/GZ029IWVSyhvQ0kebBnHMPlnx9PzxTARhbLN6GFhMU4igozYJHoNh26a+j+N5BvxtmMOgBa1jV8Im/nalL0mrBm8ad4qMhZOLTuPZs0MZhm3RxoyFOIZZCzOsNCeI8Bx+cmaeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Wed, 11 Feb 2026 11:07:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vqCXt-0007F4-P5 for qemu-devel@nongnu.org; Wed, 11 Feb 2026 10:54:30 -0500 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vqCXs-0003Qt-2d for qemu-devel@nongnu.org; Wed, 11 Feb 2026 10:54:29 -0500 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.59]) by linux.microsoft.com (Postfix) with ESMTPSA id 8394620B7167; Wed, 11 Feb 2026 07:54:25 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 8394620B7167 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1770825267; bh=pyv1PJkyvNJjYOU3f95oHtFWtd2b0zce9KZaW4NZQOI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KzPxSyPM1tzwXTVVE9RUQMHwrhVgOhTSE5PyyR67X5OT0yvWcUVNBDfm1IIOFhyD0 0og9xjgQtfrOSiqkPml6JbfLNrr4d8R03KsZS/leG9gFgKlLeSVO/seXRDPAuNZwFf kYEd/8GOvqtXYSK9SmhjkQ+I9hZLFJ0OrjRHEIBY= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Wei Liu , Zhao Liu , Paolo Bonzini , Magnus Kulke Subject: [PATCH 05/10] target/i386/mshv: fix various cpuid traversal bugs Date: Wed, 11 Feb 2026 16:54:05 +0100 Message-Id: <20260211155410.203883-6-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> References: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" - Hardcoded max_leaf was not accurate. We query leaf 0x0 and 0x80000000 to get the actual max leaves - On all 0 zeroes on leaf 0x0d, we register 0-63 subleaves with zeros indicating XSAVE is disabled - Subleaf 0 was hardcoded, so the Hypervisor returned defaults for other subleaves - Subleaf 0 war hardcoded, so we were passing 0 instead of actual subleaf when adding entries. We now pass the correct subleaf value to add_cpuid_entry() - Leaves 0x04,0x07,0d,0f,10 weren't marked as subleaf-specific Signed-off-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 88 +++++++++++++++++++++++++------------ 1 file changed, 61 insertions(+), 27 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 5c46cd67ec..9fa93d2db1 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -465,14 +465,17 @@ static void collect_cpuid_entries(const CPUState *cpu= , GList **cpuid_entries) CPUX86State *env =3D &x86_cpu->env; uint32_t eax, ebx, ecx, edx; uint32_t leaf, subleaf; - size_t max_leaf =3D 0x1F; - size_t max_subleaf =3D 0x20; - - uint32_t leaves_with_subleaves[] =3D {0x4, 0x7, 0xD, 0xF, 0x10}; + uint32_t max_basic_leaf, max_extended_leaf; + uint32_t max_subleaf =3D 0x20; + uint32_t leaves_with_subleaves[] =3D {0x04, 0x07, 0x0d, 0x0f, 0x10}; int n_subleaf_leaves =3D ARRAY_SIZE(leaves_with_subleaves); =20 - /* Regular leaves without subleaves */ - for (leaf =3D 0; leaf <=3D max_leaf; leaf++) { + /* Get maximum basic and and extended CPUID leaves */ + cpu_x86_cpuid(env, 0, 0, &max_basic_leaf, &ebx, &ecx, &edx); + cpu_x86_cpuid(env, 0x80000000, 0, &max_extended_leaf, &ebx, &ecx, &edx= ); + + /* Collect basic leaves (0x0 to max_basic_leaf) */ + for (leaf =3D 0; leaf <=3D max_basic_leaf; leaf++) { bool has_subleaves =3D false; for (int i =3D 0; i < n_subleaf_leaves; i++) { if (leaf =3D=3D leaves_with_subleaves[i]) { @@ -483,27 +486,40 @@ static void collect_cpuid_entries(const CPUState *cpu= , GList **cpuid_entries) =20 if (!has_subleaves) { cpu_x86_cpuid(env, leaf, 0, &eax, &ebx, &ecx, &edx); - if (eax =3D=3D 0 && ebx =3D=3D 0 && ecx =3D=3D 0 && edx =3D=3D= 0) { - /* all zeroes indicates no more leaves */ - continue; - } - add_cpuid_entry(cpuid_entries, leaf, 0, eax, ebx, ecx, edx); continue; } =20 + /* + * Valid XSAVE components can exist at a higher index se we need t= o set + * all subleaves for leaf 0x0d, even if we encounter an empty one. + */ + if (leaf =3D=3D 0x0d) { + for (subleaf =3D 0; subleaf <=3D 63; subleaf++) { + cpu_x86_cpuid(env, leaf, subleaf, &eax, &ebx, &ecx, &edx); + add_cpuid_entry(cpuid_entries, leaf, subleaf, + eax, ebx, ecx, edx); + } + continue; + } + subleaf =3D 0; while (subleaf < max_subleaf) { cpu_x86_cpuid(env, leaf, subleaf, &eax, &ebx, &ecx, &edx); =20 if (eax =3D=3D 0 && ebx =3D=3D 0 && ecx =3D=3D 0 && edx =3D=3D= 0) { - /* all zeroes indicates no more leaves */ break; } - add_cpuid_entry(cpuid_entries, leaf, 0, eax, ebx, ecx, edx); + add_cpuid_entry(cpuid_entries, leaf, subleaf, eax, ebx, ecx, e= dx); subleaf++; } } + + /* Collect extended leaves (0x80000000 to max_extended_leaf) */ + for (leaf =3D 0x80000000; leaf <=3D max_extended_leaf; leaf++) { + cpu_x86_cpuid(env, leaf, 0, &eax, &ebx, &ecx, &edx); + add_cpuid_entry(cpuid_entries, leaf, 0, eax, ebx, ecx, edx); + } } =20 static int register_intercept_result_cpuid_entry(const CPUState *cpu, @@ -576,22 +592,40 @@ static int register_intercept_result_cpuid(const CPUS= tate *cpu, subleaf_specific =3D 0; always_override =3D 1; =20 - /* Intel */ - /* 0xb - Extended Topology Enumeration Leaf */ - /* 0x1f - V2 Extended Topology Enumeration Leaf */ - /* AMD */ - /* 0x8000_001e - Processor Topology Information */ - /* 0x8000_0026 - Extended CPU Topology */ - if (entry->function =3D=3D 0xb - || entry->function =3D=3D 0x1f - || entry->function =3D=3D 0x8000001e - || entry->function =3D=3D 0x80000026) { + /* + * Intel + * 0xb - Extended Topology Enumeration Leaf + * 0x1f - V2 Extended Topology Enumeration Leaf + * AMD + * 0x8000_001e - Processor Topology Information + * 0x8000_0026 - Extended CPU Topology + */ + if (entry->function =3D=3D 0xb || + entry->function =3D=3D 0x1f || + entry->function =3D=3D 0x8000001e || + entry->function =3D=3D 0x80000026) { + subleaf_specific =3D 1; + always_override =3D 1; + /* + * Feature enumeration leaves (subleaf-specific) + * 0x04: Deterministic Cache Parameters + * 0x07: Structured Extended Feature Flags + * 0x0D: Processor Extended State Enumeration + * 0x0F: Platform QoS Monitoring + * 0x10: Platform QoS Enforcement + */ + } else if (entry->function =3D=3D 0x04 || + entry->function =3D=3D 0x07 || + entry->function =3D=3D 0x0d || + entry->function =3D=3D 0x0f || + entry->function =3D=3D 0x10) { subleaf_specific =3D 1; always_override =3D 1; - } else if (entry->function =3D=3D 0x00000001 - || entry->function =3D=3D 0x80000000 - || entry->function =3D=3D 0x80000001 - || entry->function =3D=3D 0x80000008) { + /* Basic feature leaves (no subleaves) */ + } else if (entry->function =3D=3D 0x00000001 || + entry->function =3D=3D 0x80000000 || + entry->function =3D=3D 0x80000001 || + entry->function =3D=3D 0x80000008) { subleaf_specific =3D 0; always_override =3D 1; } --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826070; cv=none; d=zohomail.com; s=zohoarc; b=dy41uE82FPP4g1Y87P88VO/foJ32JoRyAlqfSp42/7ISiZ0eIFQiimTD24luFaCC9TxnFZnu/sEfHrz78gbpvmxpIenZUe7mN19tIZZUu1kTcrv9/8910Hw7RlvSEKZWGh1NiYr5KBSd7gTUEMJugSO7ttnUqB18RZOnombVXfY= ARC-Message-Signature: i=1; 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charset="utf-8" The current implementation would only override the feature bits that are enabled, however we also want to consider disabled features, hence all bits are set on the masks in the hypercall argument. Signed-off-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 9fa93d2db1..b862a7ff6a 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -538,22 +538,17 @@ static int register_intercept_result_cpuid_entry(cons= t CPUState *cpu, .input.always_override =3D always_override, .input.padding =3D 0, /* - * With regard to masks - these are to specify bits to be overwrit= ten - * The current CpuidEntry structure wouldn't allow to carry the ma= sks - * in addition to the actual register values. For this reason, the - * masks are set to the exact values of the corresponding register= bits - * to be registered for an overwrite. To view resulting values the - * hypervisor would return, HvCallGetVpCpuidValues hypercall can be - * used. + * Masks specify which bits to override. Set to 0xFFFFFFFF to + * override all bits with the values from the QEMU CPU model. */ .result.eax =3D entry->eax, - .result.eax_mask =3D entry->eax, + .result.eax_mask =3D 0xFFFFFFFF, .result.ebx =3D entry->ebx, - .result.ebx_mask =3D entry->ebx, + .result.ebx_mask =3D 0xFFFFFFFF, .result.ecx =3D entry->ecx, - .result.ecx_mask =3D entry->ecx, + .result.ecx_mask =3D 0xFFFFFFFF, .result.edx =3D entry->edx, - .result.edx_mask =3D entry->edx, + .result.edx_mask =3D 0xFFFFFFFF, }; union hv_register_intercept_result_parameters parameters =3D { .cpuid =3D cpuid_params, --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826069; cv=none; d=zohomail.com; s=zohoarc; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gwyrdKh8U3uPK5lxUJjuZWZazScYSrGEmoxY6OHr0lcVRGBFsTMCzEg7lWRf63NFP E3tp+AAeROpi8XrEnJBGeRheNCZ0Xq28BR3hOy208iaFKjMUDY43+d/ZlsJJJ0RhAD oVrq+7k53ttqpkfQgtBvTUgqaiCc2c48osRFlGUE= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Wei Liu , Zhao Liu , Paolo Bonzini , Magnus Kulke Subject: [PATCH 07/10] target/i386/mshv: set cpu model name on -cpu host Date: Wed, 11 Feb 2026 16:54:07 +0100 Message-Id: <20260211155410.203883-8-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> References: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 11 Feb 2026 11:07:32 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1770826070736154100 Content-Type: text/plain; charset="utf-8" By registering a cpu_accel_class for mshv, we can report an accurate model name on -cpu host. Signed-off-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index b862a7ff6a..38e0a045c2 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -24,10 +24,13 @@ #include "hw/i386/apic_internal.h" =20 #include "cpu.h" +#include "host-cpu.h" #include "emulate/x86_decode.h" #include "emulate/x86_emu.h" #include "emulate/x86_flags.h" =20 +#include "accel/accel-cpu-target.h" + #include "trace-accel_mshv.h" #include "trace.h" =20 @@ -1793,3 +1796,31 @@ int mshv_arch_post_init_vm(int vm_fd) =20 return ret; } + +static void mshv_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); +} + +static void mshv_cpu_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D mshv_cpu_instance_init; +} + +static const TypeInfo mshv_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("mshv"), + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D mshv_cpu_accel_class_init, + .abstract =3D true, +}; + +static void mshv_cpu_accel_register_types(void) +{ + type_register_static(&mshv_cpu_accel_type_info); +} + +type_init(mshv_cpu_accel_register_types); --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826149; cv=none; d=zohomail.com; s=zohoarc; b=GlMgpT7Axk0yAIjz5jmLW6gTWxxh65frx5AM3sSZ2SC9ugMp0l+e8TeHKRxkzq1XfAONkHtQMS4LQvgoH8OdCWc4h7t5UUgIdqoFdXIkMTg/ip4++AIUYJ2SI3Dq1BNyd481zsgzpK2v8typpImXZQNZ441TmDldsP7Ca0i1rg4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770826149; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 11 Feb 2026 10:54:36 -0500 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vqCXz-0003Ry-21 for qemu-devel@nongnu.org; Wed, 11 Feb 2026 10:54:36 -0500 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.59]) by linux.microsoft.com (Postfix) with ESMTPSA id 4692D20B7168; Wed, 11 Feb 2026 07:54:32 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 4692D20B7168 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1770825273; bh=c9Cqif7Bf9HNIGMAb4KJECjwGAGpn7SzhAVsuFQtugQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=laV4mzC5JEM0kCDYEwfuA/wWhH52A092Za0U5dHOsWsU1YIP9x1CctwgC/1fMTquX CZX+0c4zgFvGoDqEVdYpchr9AurAJDzsEL5TCX9jpWbfYaXRrWUdC3t0OQNBbXGqI1 bZMcrhtF1nXWdWKTK5nZ6t6/0pYZdT1GkNyl1dXY= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Wei Liu , Zhao Liu , Paolo Bonzini , Magnus Kulke Subject: [PATCH 08/10] target/i386: query mshv accel for supported cpuids Date: Wed, 11 Feb 2026 16:54:08 +0100 Message-Id: <20260211155410.203883-9-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> References: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We implement mshv_get_supported_cpuid() and invoke it in x86_cpu_get_supported_feature_word() retrieve the cpu features that the host is supporting. Initially we mask the virtualization capabilitities potentially we might need to mask more in the future. Signed-off-by: Magnus Kulke --- include/system/mshv.h | 3 +++ target/i386/cpu.c | 8 ++++++++ target/i386/mshv/mshv-cpu.c | 27 +++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/include/system/mshv.h b/include/system/mshv.h index 75286baf16..51b0420735 100644 --- a/include/system/mshv.h +++ b/include/system/mshv.h @@ -60,4 +60,7 @@ int mshv_irqchip_add_irqfd_notifier_gsi(const EventNotifi= er *n, const EventNotifier *rn, int virq); int mshv_irqchip_remove_irqfd_notifier_gsi(const EventNotifier *n, int vir= q); =20 +/* cpuid */ +uint32_t mshv_get_supported_cpuid(uint32_t func, uint32_t idx, int reg); + #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0a7b884528..b611afc21a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -26,6 +26,7 @@ #include "tcg/helper-tcg.h" #include "exec/translation-block.h" #include "system/hvf.h" +#include "system/mshv.h" #include "hvf/hvf-i386.h" #include "kvm/kvm_i386.h" #include "kvm/tdx.h" @@ -7958,6 +7959,13 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w) r =3D hvf_get_supported_cpuid(wi->cpuid.eax, wi->cpuid.ecx, wi->cpuid.reg); + } else if (mshv_enabled()) { + if (wi->type !=3D CPUID_FEATURE_WORD) { + return 0; + } + r =3D mshv_get_supported_cpuid(wi->cpuid.eax, + wi->cpuid.ecx, + wi->cpuid.reg); } else if (tcg_enabled()) { r =3D wi->tcg_features; } else { diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 38e0a045c2..bbb58461a4 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1757,6 +1757,33 @@ void mshv_arch_destroy_vcpu(CPUState *cpu) g_clear_pointer(&env->emu_mmio_buf, g_free); } =20 +uint32_t mshv_get_supported_cpuid(uint32_t func, uint32_t idx, int reg) +{ + uint32_t eax, ebx, ecx, edx; + uint32_t ret =3D 0; + + host_cpuid(func, idx, &eax, &ebx, &ecx, &edx); + switch (reg) { + case R_EAX: + ret =3D eax; break; + case R_EBX: + ret =3D ebx; break; + case R_ECX: + ret =3D ecx; break; + case R_EDX: + ret =3D edx; break; + } + + /* Disable nested virtualization features not yet supported by MSHV */ + if (func =3D=3D 0x80000001 && reg =3D=3D R_ECX) { + ret &=3D ~CPUID_EXT3_SVM; + } + if (func =3D=3D 0x01 && reg =3D=3D R_ECX) { + ret &=3D ~CPUID_EXT_VMX; + } + return ret; +} + /* * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a * fault to the guest if it tries to access it. It is possible to override --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826161; cv=none; d=zohomail.com; s=zohoarc; b=dRTzjyeCvS6vMXq+k6jQD6MdekJqO5Lhxtb33R1I8eoQoX5YLNT4E5i2TfU4RgPNQKtgF/RdTXSm5UqKp+OgrSxKT1cHA9S5Jz05HHxokEdBhwsxl7eOrh8gvyEM3XHRy4plBmj9OwLwmw7SarU9WhutpG1sUGX+ljAtAZLO0XE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770826161; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=y0AZrGQxkM0uQ3rXiuFiHUPhH9t2OtafmeHf8sG36kk=; b=hGtUm51dwIAnCZedSzH6AZOxOFvW0s+qkoX1kViROPdqNNRUcW4rEiu0z/0kszzOOtKM8O9Qp+JPBnptAY4z/kdOpKP55WbLFSj9D9K0Pg3zfYnAl9+bZ7N8FAKN9jyBLsg+GvsEI9MKacYeRuJs2ZlgmNlW52pLTUGiwKiEi2s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770826161609914.4146036908495; Wed, 11 Feb 2026 08:09:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vqCkn-0002sE-8t; Wed, 11 Feb 2026 11:07:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vqCY2-0007M1-TU for qemu-devel@nongnu.org; Wed, 11 Feb 2026 10:54:38 -0500 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vqCY1-0003SL-Jd for qemu-devel@nongnu.org; Wed, 11 Feb 2026 10:54:38 -0500 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.59]) by linux.microsoft.com (Postfix) with ESMTPSA id 9062F20B7167; Wed, 11 Feb 2026 07:54:34 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 9062F20B7167 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1770825276; bh=y0AZrGQxkM0uQ3rXiuFiHUPhH9t2OtafmeHf8sG36kk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=suVvrQ0x+F4cNaMUhKc5yiqiZamSBlq1POLNAYSmhtqhMRoJiApZpRTx67alO5lP/ /lXRyARzoec4nItyeeK24zf+aZD6umSZI+PsCCOiDYXgkuhy9P/ncCvLc8vyBIOD09 S6GxI70jTNKg54eeV5no83LKtwmB/IRRUn6lN4Tc= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Wei Liu , Zhao Liu , Paolo Bonzini , Magnus Kulke Subject: [PATCH 09/10] target/i386/mshv: populate xsave area offsets Date: Wed, 11 Feb 2026 16:54:09 +0100 Message-Id: <20260211155410.203883-10-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> References: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=13.77.154.182; envelope-from=magnuskulke@linux.microsoft.com; helo=linux.microsoft.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 11 Feb 2026 11:07:32 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.microsoft.com) X-ZM-MESSAGEID: 1770826161802158500 Content-Type: text/plain; charset="utf-8" This function is copied verbatim from kvm_cpu_xsave_init(), for MSHV we need to populate the offsets similarly. Signed-off-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index bbb58461a4..3a7d9237cd 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1824,11 +1824,42 @@ int mshv_arch_post_init_vm(int vm_fd) return ret; } =20 +static void mshv_cpu_xsave_init(void) +{ + static bool first =3D true; + uint32_t eax, ebx, ecx, edx; + int i; + + if (!first) { + return; + } + first =3D false; + + /* x87 and SSE states are in the legacy region of the XSAVE area. */ + x86_ext_save_areas[XSTATE_FP_BIT].offset =3D 0; + x86_ext_save_areas[XSTATE_SSE_BIT].offset =3D 0; + + for (i =3D XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { + ExtSaveArea *esa =3D &x86_ext_save_areas[i]; + + if (!esa->size) { + continue; + } + host_cpuid(0xd, i, &eax, &ebx, &ecx, &edx); + if (eax !=3D 0) { + assert(esa->size =3D=3D eax); + esa->offset =3D ebx; + esa->ecx =3D ecx; + } + } +} + static void mshv_cpu_instance_init(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 host_cpu_instance_init(cpu); + mshv_cpu_xsave_init(); } =20 static void mshv_cpu_accel_class_init(ObjectClass *oc, const void *data) --=20 2.34.1 From nobody Sun Apr 12 04:22:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.microsoft.com ARC-Seal: i=1; a=rsa-sha256; t=1770826168; cv=none; d=zohomail.com; s=zohoarc; b=ha4qwHgGi3CLrzsKK1Nh2m0dc94xMdx/WoVRZ23o3HE8+cw2PHf/vqlGiwuGCcvxBP+vve5kGQLoh+k8cPzVPlGvIgxeXF98dwPHb1fM+vinZ1ug2lSlwxo5dw8WtLRNC0lYtR2+kI7exKl9kKpcza1fBHzfYo5IXT96cmMP9Mo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770826168; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 11 Feb 2026 10:54:41 -0500 Received: from linux.microsoft.com ([13.77.154.182]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vqCY3-0003Sn-T9 for qemu-devel@nongnu.org; Wed, 11 Feb 2026 10:54:41 -0500 Received: from DESKTOP-TUU1E5L.localdomain (unknown [167.220.208.59]) by linux.microsoft.com (Postfix) with ESMTPSA id 2D83620B7168; Wed, 11 Feb 2026 07:54:37 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 2D83620B7168 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1770825278; bh=HkpGIAxAdQuzfCrev9KQdB7pHBPey4VgXUf/LiB3/ZA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZsuVw4evXQXHAL1y1HpNXhZOxfcJ/ECPdYpbsvENzG8IpSt3a3lUTiHPmOlidsi+0 iASIc82W0XwNS48yB1bIevqp5laeUrG+S9+AcnYMNqW4xmEEnPuOw3A0SSKJBr/9wT GZTZfIWfdiG1DO0D76ocKsHgoz4/wGvWMwPBuV1E= From: Magnus Kulke To: qemu-devel@nongnu.org Cc: Magnus Kulke , Wei Liu , Wei Liu , Zhao Liu , Paolo Bonzini , Magnus Kulke Subject: [PATCH 10/10] target/i386/mshv: filter out CET bits in cpuid Date: Wed, 11 Feb 2026 16:54:10 +0100 Message-Id: <20260211155410.203883-11-magnuskulke@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> References: <20260211155410.203883-1-magnuskulke@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" e46dcef1d0 introduced CET_U/CET_S xstate bits in the ExtSaveArea. The response in EBX of a 0x4,1 cpuid query will contain a size contingent on what the guest enabled in the IA32_XSS MSR (compacted xsave size). Since the MSHV accelerator currently responds with static answers to 0x4d cpuid queries, we'll have to disable those bits, even if the host supports them. Signed-off-by: Magnus Kulke --- target/i386/mshv/mshv-cpu.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c index 3a7d9237cd..4d64c54bc6 100644 --- a/target/i386/mshv/mshv-cpu.c +++ b/target/i386/mshv/mshv-cpu.c @@ -1781,6 +1781,25 @@ uint32_t mshv_get_supported_cpuid(uint32_t func, uin= t32_t idx, int reg) if (func =3D=3D 0x01 && reg =3D=3D R_ECX) { ret &=3D ~CPUID_EXT_VMX; } + + /* + * MSHV currently uses static CPUID intercept results for leaf 0xD. + * However there are feature-responses that are dynamic based on what a + * guest enables in XCR0 and XSS, such as CET shadow stack. + * + * A guest which doesn't know about those features yet would encounter= an + * unexpcted CPUID[0xD,1].EBX (compactes XSAVE size) and either fail + * or gracefully degrade by not using XSAVE at all. + * + * To avoid this, we filter out supervisor xstate features. + */ + if (func =3D=3D 0x07 && idx =3D=3D 0 && reg =3D=3D R_ECX) { + ret &=3D ~CPUID_7_0_ECX_CET_SHSTK; + } + if (func =3D=3D 0x07 && idx =3D=3D 0 && reg =3D=3D R_EDX) { + ret &=3D ~CPUID_7_0_EDX_CET_IBT; + } + return ret; } =20 --=20 2.34.1