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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1770759694344158500 Knowing the value of this register is very useful for debugging floating-point code. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Thomas Huth Signed-off-by: Ilya Leoshkevich --- target/s390x/cpu-dump.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/s390x/cpu-dump.c b/target/s390x/cpu-dump.c index 869d3a4ad54..5b852928031 100644 --- a/target/s390x/cpu-dump.c +++ b/target/s390x/cpu-dump.c @@ -63,6 +63,7 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags) (i % 4) =3D=3D 3 ? '\n' : ' '); } } + qemu_fprintf(f, "FPC=3D%08" PRIx32 "\n", env->fpc); } =20 #ifndef CONFIG_USER_ONLY --=20 2.52.0 From nobody Wed Feb 11 06:00:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1770759709; cv=none; d=zohomail.com; s=zohoarc; b=PJKRB0LgbjyV2YnaIObDaZc7QSoEjYpyUu6MlaeJXvI+wEDxKJEF9KLBKVx9LgX0QcJaYwH4G4zovkiX/yTgRXEi+bwqK6uKWxTSoVlG46EsxSizWKkImMRmDqyr8t7989FYGtCzySRczm4Zj8sd4t4d7JIkrwgxJVJt4Q28YLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770759709; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" For DIVIDE TO INTEGER it will be helpful to pass final-quotient rounding mode around explicitly rather than setting it in fpu_status implicitly. To facilitate this, extract a function for converting the mask to the rounding mode. Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth Signed-off-by: Ilya Leoshkevich --- target/s390x/tcg/fpu_helper.c | 62 +++++++++++++++++------------------ 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 1ba43715ac1..7a3ff501a46 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -56,6 +56,35 @@ uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) return s390_exc; } =20 +static int s390_get_bfp_rounding_mode(CPUS390XState *env, int m3) +{ + switch (m3) { + case 0: + /* current mode */ + return env->fpu_status.float_rounding_mode; + case 1: + /* round to nearest with ties away from 0 */ + return float_round_ties_away; + case 3: + /* round to prepare for shorter precision */ + return float_round_to_odd; + case 4: + /* round to nearest with ties to even */ + return float_round_nearest_even; + case 5: + /* round to zero */ + return float_round_to_zero; + case 6: + /* round to +inf */ + return float_round_up; + case 7: + /* round to -inf */ + return float_round_down; + default: + g_assert_not_reached(); + } +} + /* Should be called after any operation that may raise IEEE exceptions. */ static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t reta= ddr) { @@ -416,37 +445,8 @@ int s390_swap_bfp_rounding_mode(CPUS390XState *env, in= t m3) { int ret =3D env->fpu_status.float_rounding_mode; =20 - switch (m3) { - case 0: - /* current mode */ - break; - case 1: - /* round to nearest with ties away from 0 */ - set_float_rounding_mode(float_round_ties_away, &env->fpu_status); - break; - case 3: - /* round to prepare for shorter precision */ - set_float_rounding_mode(float_round_to_odd, &env->fpu_status); - break; - case 4: - /* round to nearest with ties to even */ - set_float_rounding_mode(float_round_nearest_even, &env->fpu_status= ); - break; - case 5: - /* round to zero */ - set_float_rounding_mode(float_round_to_zero, &env->fpu_status); - break; - case 6: - /* round to +inf */ - set_float_rounding_mode(float_round_up, &env->fpu_status); - break; - case 7: - /* round to -inf */ - set_float_rounding_mode(float_round_down, &env->fpu_status); - break; - default: - g_assert_not_reached(); - } + set_float_rounding_mode(s390_get_bfp_rounding_mode(env, m3), + &env->fpu_status); return ret; } =20 --=20 2.52.0 From nobody Wed Feb 11 06:00:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1770759712; cv=none; d=zohomail.com; s=zohoarc; b=Mj0JtvGK9aHJ3ko6K3GiRxcbZBu8dD91lm9huZ07AQyEtSaJUEM7/OZd2lboBsAUZYMVPL7TfheFlo6WkpWEasYfFbmppj1O7sZqLymvIRbG+c+3HXx/nstb1euPIoqWr0URWnwdKvFTN7SS8TUs77KuXA7eKfMpYvJVxMeBDHs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770759712; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Currently parts_round_to_int_normal() assumes that its input has just been unpacked and therefore doesn't expect non-zero fraction bits past target precision. The upcoming DIVIDE TO INTEGER use cases needs it to support calculations on intermediate values that utilize all fraction bits, while at the same time restricting the result's precision to frac_size. Delete the "All integral" check, because even though really large values are always integer, their low fraction bits still need to be truncated. For the same reason, make sure rnd_mask covers at least fraction bits past target precision. Signed-off-by: Ilya Leoshkevich --- fpu/softfloat-parts.c.inc | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 5e0438fc0b7..79b56014ab9 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -1118,11 +1118,6 @@ static bool partsN(round_to_int_normal)(FloatPartsN = *a, FloatRoundMode rmode, return true; } =20 - if (a->exp >=3D frac_size) { - /* All integral */ - return false; - } - if (N > 64 && a->exp < N - 64) { /* * Rounding is not in the low word -- shift lsb to bit 2, @@ -1132,8 +1127,13 @@ static bool partsN(round_to_int_normal)(FloatPartsN = *a, FloatRoundMode rmode, frac_shrjam(a, shift_adj); frac_lsb =3D 1 << 2; } else { + /* + * Rounding is in the low word -- compute the lsb offset for round= ing + * and for clamping to the target precision, then map it to an off= set + * within frac_lo. + */ shift_adj =3D 0; - frac_lsb =3D DECOMPOSED_IMPLICIT_BIT >> (a->exp & 63); + frac_lsb =3D DECOMPOSED_IMPLICIT_BIT >> (MIN(a->exp, frac_size) & = 63); } =20 frac_lsbm1 =3D frac_lsb >> 1; --=20 2.52.0 From nobody Wed Feb 11 06:00:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1770759712; cv=none; d=zohomail.com; s=zohoarc; b=ZNSgdhhgY/3mLXNfk98KXnEFAd4tnl4MSuaPs5sUqREEyYvhSUOSlAyNYn6aG22++s6eSS4Ad7A2D/QgiftaxEULePucuSRWYJc3d5bfaMj55pqLTxC/13TFvNyrMxtueoTujNuB7yULoAnXNPtLRTveIucT3qAym+Vp4+xJt60= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770759712; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8z04RsCuKhoHOLFMtBkPViPY7uVjfcbuyKVzTFWN/is=; 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charset="utf-8" DIVIDE TO INTEGER computes floating point remainder and is used by LuaJIT, so add it to QEMU. Put the main logic into fpu/, because it is way more convenient to operate on FloatParts than to convert floats back-and-forth. Reviewed-by: Richard Henderson Signed-off-by: Ilya Leoshkevich --- fpu/softfloat.c | 142 +++++++++++++++++++++++++++++++ include/fpu/softfloat.h | 11 +++ target/s390x/helper.h | 1 + target/s390x/tcg/fpu_helper.c | 56 ++++++++++++ target/s390x/tcg/insn-data.h.inc | 5 +- target/s390x/tcg/translate.c | 26 ++++++ 6 files changed, 240 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8094358c2e4..87409753483 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -5361,6 +5361,148 @@ floatx80 floatx80_round(floatx80 a, float_status *s= tatus) return floatx80_round_pack_canonical(&p, status); } =20 +static void parts_s390_divide_to_integer(FloatParts64 *a, FloatParts64 *b, + int final_quotient_rounding_mode, + bool mask_underflow, bool mask_in= exact, + const FloatFmt *fmt, + FloatParts64 *r, FloatParts64 *n, + uint32_t *cc, int *dxc, + float_status *status) +{ + /* POp table "Results: DIVIDE TO INTEGER (Part 1 of 2)" */ + if ((float_cmask(a->cls) | float_cmask(b->cls)) & float_cmask_anynan) { + *r =3D *parts_pick_nan(a, b, status); + *n =3D *r; + *cc =3D 1; + } else if (a->cls =3D=3D float_class_inf || b->cls =3D=3D float_class_= zero) { + parts_default_nan(r, status); + *n =3D *r; + *cc =3D 1; + status->float_exception_flags |=3D float_flag_invalid; + } else if (b->cls =3D=3D float_class_inf) { + *r =3D *a; + n->cls =3D float_class_zero; + n->sign =3D a->sign ^ b->sign; + *cc =3D 0; + } else { + FloatParts64 *q, q_buf, *r_precise, r_precise_buf; + int float_exception_flags =3D 0; + bool is_q_smallish; + uint32_t r_flags; + + /* Compute precise quotient */ + q_buf =3D *a; + q =3D parts_div(&q_buf, b, status); + + /* + * Check whether two closest integers can be precisely represented, + * i.e., all their bits fit into the fractional part. + */ + is_q_smallish =3D q->exp < (fmt->frac_size + 1); + + /* + * Final quotient is rounded using final-quotient-rounding method,= and + * partial quotient is rounded toward zero. + * + * Rounding of partial quotient may be inexact. This is the whole = point + * of distinguishing partial quotients, so ignore the exception. + */ + *n =3D *q; + parts_round_to_int_normal(n, + is_q_smallish ? + final_quotient_rounding_mode : + float_round_to_zero, + 0, fmt->frac_size); + + /* Compute precise remainder */ + r_precise_buf =3D *b; + r_precise =3D parts_muladd_scalbn(&r_precise_buf, n, a, 0, + float_muladd_negate_product, statu= s); + + /* Round remainder to the target format */ + *r =3D *r_precise; + status->float_exception_flags =3D 0; + parts_uncanon(r, status, fmt); + r_flags =3D status->float_exception_flags; + r->frac &=3D (1ULL << fmt->frac_size) - 1; + parts_canonicalize(r, status, fmt); + + /* POp table "Results: DIVIDE TO INTEGER (Part 2 of 2)" */ + if (is_q_smallish) { + if (r->cls !=3D float_class_zero) { + if (r->exp < 2 - (1 << (fmt->exp_size - 1))) { + if (mask_underflow) { + float_exception_flags |=3D float_flag_underflow; + *dxc =3D 0x10; + r->exp +=3D fmt->exp_re_bias; + } + } else if (r_flags & float_flag_inexact) { + float_exception_flags |=3D float_flag_inexact; + if (mask_inexact) { + bool saved_r_sign, saved_r_precise_sign; + + /* + * Check whether remainder was truncated (rounded + * toward zero) or incremented. + */ + saved_r_sign =3D r->sign; + saved_r_precise_sign =3D r_precise->sign; + r->sign =3D false; + r_precise->sign =3D false; + if (parts_compare(r, r_precise, status, true) < + float_relation_equal) { + *dxc =3D 0x8; + } else { + *dxc =3D 0xc; + } + r->sign =3D saved_r_sign; + r_precise->sign =3D saved_r_precise_sign; + } + } + } + *cc =3D 0; + } else if (n->exp > (1 << (fmt->exp_size - 1)) - 1) { + n->exp -=3D fmt->exp_re_bias; + *cc =3D r->cls =3D=3D float_class_zero ? 1 : 3; + } else { + *cc =3D r->cls =3D=3D float_class_zero ? 0 : 2; + } + + /* Adjust signs of zero results */ + if (r->cls =3D=3D float_class_zero) { + r->sign =3D a->sign; + } + if (n->cls =3D=3D float_class_zero) { + n->sign =3D a->sign ^ b->sign; + } + + status->float_exception_flags =3D float_exception_flags; + } +} + +#define DEFINE_S390_DIVIDE_TO_INTEGER(floatN) = \ +void floatN ## _s390_divide_to_integer(floatN a, floatN b, = \ + int final_quotient_rounding_mode, = \ + bool mask_underflow, bool mask_inex= act, \ + floatN *r, floatN *n, = \ + uint32_t *cc, int *dxc, = \ + float_status *status) = \ +{ = \ + FloatParts64 pa, pb, pr, pn; = \ + = \ + floatN ## _unpack_canonical(&pa, a, status); = \ + floatN ## _unpack_canonical(&pb, b, status); = \ + parts_s390_divide_to_integer(&pa, &pb, final_quotient_rounding_mode, = \ + mask_underflow, mask_inexact, = \ + &floatN ## _params, = \ + &pr, &pn, cc, dxc, status); = \ + *r =3D floatN ## _round_pack_canonical(&pr, status); = \ + *n =3D floatN ## _round_pack_canonical(&pn, status); = \ +} + +DEFINE_S390_DIVIDE_TO_INTEGER(float32) +DEFINE_S390_DIVIDE_TO_INTEGER(float64) + static void __attribute__((constructor)) softfloat_init(void) { union_float64 ua, ub, uc, ur; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index c18ab2cb609..66b0c47b5eb 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -1372,4 +1372,15 @@ static inline bool float128_unordered_quiet(float128= a, float128 b, *-------------------------------------------------------------------------= ---*/ float128 float128_default_nan(float_status *status); =20 +#define DECLARE_S390_DIVIDE_TO_INTEGER(floatN) = \ +void floatN ## _s390_divide_to_integer(floatN a, floatN b, = \ + int final_quotient_rounding_mode, = \ + bool mask_underflow, bool mask_inex= act, \ + floatN *r, floatN *n, = \ + uint32_t *cc, int *dxc, = \ + float_status *status) +DECLARE_S390_DIVIDE_TO_INTEGER(float32); +DECLARE_S390_DIVIDE_TO_INTEGER(float64); + + #endif /* SOFTFLOAT_H */ diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 1a8a76abb98..6a7426fdac7 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -46,6 +46,7 @@ DEF_HELPER_FLAGS_3(sxb, TCG_CALL_NO_WG, i128, env, i128, = i128) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(dxb, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_6(dib, void, env, i32, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 7a3ff501a46..122994960a6 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -315,6 +315,62 @@ Int128 HELPER(dxb)(CPUS390XState *env, Int128 a, Int12= 8 b) return RET128(ret); } =20 +void HELPER(dib)(CPUS390XState *env, uint32_t r1, uint32_t r2, uint32_t r3, + uint32_t m4, uint32_t bits) +{ + int final_quotient_rounding_mode =3D s390_get_bfp_rounding_mode(env, m= 4); + bool mask_underflow =3D (env->fpc >> 24) & S390_IEEE_MASK_UNDERFLOW; + bool mask_inexact =3D (env->fpc >> 24) & S390_IEEE_MASK_INEXACT; + float32 a32, b32, n32, r32; + float64 a64, b64, n64, r64; + int dxc =3D -1; + uint32_t cc; + + if (bits =3D=3D 32) { + a32 =3D env->vregs[r1][0] >> 32; + b32 =3D env->vregs[r2][0] >> 32; + + float32_s390_divide_to_integer( + a32, b32, + final_quotient_rounding_mode, + mask_underflow, mask_inexact, + &r32, &n32, &cc, &dxc, &env->fpu_status); + } else { + a64 =3D env->vregs[r1][0]; + b64 =3D env->vregs[r2][0]; + + float64_s390_divide_to_integer( + a64, b64, + final_quotient_rounding_mode, + mask_underflow, mask_inexact, + &r64, &n64, &cc, &dxc, &env->fpu_status); + } + + /* Flush the results if needed */ + if ((env->fpu_status.float_exception_flags & float_flag_invalid) && + ((env->fpc >> 24) & S390_IEEE_MASK_INVALID)) { + /* The action for invalid operation is "Suppress" */ + } else { + /* The action for other exceptions is "Complete" */ + if (bits =3D=3D 32) { + env->vregs[r1][0] =3D deposit64(env->vregs[r1][0], 32, 32, r32= ); + env->vregs[r3][0] =3D deposit64(env->vregs[r3][0], 32, 32, n32= ); + } else { + env->vregs[r1][0] =3D r64; + env->vregs[r3][0] =3D n64; + } + env->cc_op =3D cc; + } + + /* Raise an exception if needed */ + if (dxc =3D=3D -1) { + handle_exceptions(env, false, GETPC()); + } else { + env->fpu_status.float_exception_flags =3D 0; + tcg_s390_data_exception(env, dxc, GETPC()); + } +} + /* 32-bit FP multiplication */ uint64_t HELPER(meeb)(CPUS390XState *env, uint64_t f1, uint64_t f2) { diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.= h.inc index baaafe922e9..0d5392eac54 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -9,7 +9,7 @@ * OPC =3D (op << 8) | op2 where op is the major, op2 the minor opcode * NAME =3D name of the opcode, used internally * FMT =3D format of the opcode (defined in insn-format.h.inc) - * FAC =3D facility the opcode is available in (defined in DisasFacility) + * FAC =3D facility the opcode is available in (define in translate.c) * I1 =3D func in1_xx fills o->in1 * I2 =3D func in2_xx fills o->in2 * P =3D func prep_xx initializes o->*out* @@ -361,6 +361,9 @@ C(0xb91d, DSGFR, RRE, Z, r1p1, r2_32s, r1_P, 0, divs64, 0) C(0xe30d, DSG, RXY_a, Z, r1p1, m2_64, r1_P, 0, divs64, 0) C(0xe31d, DSGF, RXY_a, Z, r1p1, m2_32s, r1_P, 0, divs64, 0) +/* DIVIDE TO INTEGER */ + D(0xb35b, DIDBR, RRF_b, Z, 0, 0, 0, 0, dib, 0, 64) + D(0xb353, DIEBR, RRF_b, Z, 0, 0, 0, 0, dib, 0, 32) =20 /* EXCLUSIVE OR */ C(0x1700, XR, RR_a, Z, r1, r2, new, r1_32, xor, nz32) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 203afe265bc..92344441878 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2283,6 +2283,32 @@ static DisasJumpType op_dxb(DisasContext *s, DisasOp= s *o) return DISAS_NEXT; } =20 +static DisasJumpType op_dib(DisasContext *s, DisasOps *o) +{ + const bool fpe =3D s390_has_feat(S390_FEAT_FLOATING_POINT_EXT); + uint8_t m4 =3D get_field(s, m4); + + if (get_field(s, r1) =3D=3D get_field(s, r2) || + get_field(s, r1) =3D=3D get_field(s, r3) || + get_field(s, r2) =3D=3D get_field(s, r3)) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + if (m4 =3D=3D 2 || (!fpe && m4 =3D=3D 3) || m4 > 7) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + gen_helper_dib(tcg_env, tcg_constant_i32(get_field(s, r1)), + tcg_constant_i32(get_field(s, r2)), + tcg_constant_i32(get_field(s, r3)), tcg_constant_i32(m4= ), + tcg_constant_i32(s->insn->data)); + set_cc_static(s); + + return DISAS_NEXT; +} + static DisasJumpType op_ear(DisasContext *s, DisasOps *o) { int r2 =3D get_field(s, r2); --=20 2.52.0 From nobody Wed Feb 11 06:00:11 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1770759750582158500 Add a test to prevent regressions. Data is generated using a libFuzzer-based fuzzer and hopefully covers all the important corner cases. Acked-by: Alex Benn=C3=A9e Signed-off-by: Ilya Leoshkevich --- tests/tcg/s390x/Makefile.target | 5 + tests/tcg/s390x/divide-to-integer.c | 265 ++++++++++++++++++++++++++++ 2 files changed, 270 insertions(+) create mode 100644 tests/tcg/s390x/divide-to-integer.c diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.tar= get index da5fe71a407..0ca030ded01 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -49,14 +49,19 @@ TESTS+=3Dcvd TESTS+=3Dcvb TESTS+=3Dts TESTS+=3Dex-smc +TESTS+=3Ddivide-to-integer =20 cdsg: CFLAGS+=3D-pthread cdsg: LDFLAGS+=3D-pthread =20 +# The following tests contain inline assembly that requires inlining, +# and thus cannot be built with -O0. rxsbg: CFLAGS+=3D-O2 +divide-to-integer: CFLAGS+=3D-O2 =20 cgebra: LDFLAGS+=3D-lm clgebr: LDFLAGS+=3D-lm +divide-to-integer: LDFLAGS+=3D-lm =20 include $(S390X_SRC)/pgm-specification.mak $(PGM_SPECIFICATION_TESTS): pgm-specification-user.o diff --git a/tests/tcg/s390x/divide-to-integer.c b/tests/tcg/s390x/divide-t= o-integer.c new file mode 100644 index 00000000000..62b4787ec0e --- /dev/null +++ b/tests/tcg/s390x/divide-to-integer.c @@ -0,0 +1,265 @@ +/* + * Test DIEBR and DIDBR instructions. + * + * Most inputs were discovered by fuzzing and exercise various corner case= s in + * the helpers. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include + +static void sigfpe_handler(int sig, siginfo_t *info, void *puc) +{ + struct ucontext *uc =3D puc; + unsigned short *xr_insn; + int r; + + xr_insn =3D (unsigned short *)(uc->uc_mcontext.regs.psw.addr - 6); + r =3D *xr_insn & 0xf; + uc->uc_mcontext.regs.gprs[r] =3D sig; +} + +#define DIVIDE_TO_INTEGER(name, floatN) = \ +static inline __attribute__((__always_inline__)) int = \ +name(floatN *r1, floatN r2, floatN *r3, int m4, int *sig) = \ +{ = \ + int cc; = \ + = \ + asm(/* Make the initial CC predictable for suppression tests */ = \ + "xr %[sig],%[sig]\n" = \ + #name " %[r1],%[r3],%[r2],%[m4]\n" = \ + "ipm %[cc]\n" = \ + "srl %[cc],28" = \ + /* = \ + * Use earlyclobbers to prevent the compiler from reusing floating= \ + * point registers. This instruction doesn't like it. = \ + */ = \ + : [r1] "+&f" (*r1), [r3] "+&f" (*r3), [sig] "=3Dr" (*sig), [cc] "= =3Dd" (cc)\ + : [r2] "f" (r2), [m4] "i" (m4) = \ + : "cc"); = \ + = \ + return cc; = \ +} + +DIVIDE_TO_INTEGER(diebr, float) +DIVIDE_TO_INTEGER(didbr, double) + +#define TEST_DIVIDE_TO_INTEGER(name, intN, int_fmt, floatN, float_fmt) = \ +static inline __attribute__((__always_inline__)) int = \ +test_ ## name(unsigned intN r1i, unsigned intN r2i, int m4, int fpc, = \ + unsigned intN r1o, unsigned intN r3o, int cco, unsigned int = fpco,\ + int sigo) = \ +{ = \ + union { = \ + floatN f; = \ + unsigned intN i; = \ + } r1, r2, r3; = \ + int cc, err =3D 0, sig; = \ + = \ + r1.i =3D r1i; = \ + r2.i =3D r2i; = \ + r3.i =3D 0x12345678; = \ + printf("[ RUN ] %" float_fmt "(0x%" int_fmt = \ + ") / %" float_fmt "(0x%" int_fmt ")\n", r1.f, r1.i, r2.f, r2.i)= ; \ + asm volatile("sfpc %[fpc]" : : [fpc] "r" (fpc)); = \ + cc =3D name(&r1.f, r2.f, &r3.f, m4, &sig); = \ + asm volatile("stfpc %[fpc]" : [fpc] "=3DQ" (fpc)); = \ + if (r1.i !=3D r1o) { = \ + printf("[ FAILED ] remainder 0x%" int_fmt = \ + " !=3D expected 0x%" int_fmt "\n", r1.i, r1o); = \ + err +=3D 1; = \ + } = \ + if (r3.i !=3D r3o) { = \ + printf("[ FAILED ] quotient 0x%" int_fmt = \ + " !=3D expected 0x%" int_fmt "\n", r3.i, r3o); = \ + err +=3D 1; = \ + } = \ + if (cc !=3D cco) { = \ + printf("[ FAILED ] cc %d !=3D expected %d\n", cc, cco); = \ + err +=3D 1; = \ + } = \ + if (fpc !=3D fpco) { = \ + printf("[ FAILED ] fpc 0x%x !=3D expected 0x%x\n", fpc, fpco); = \ + err +=3D 1; = \ + } = \ + if (sig !=3D sigo) { = \ + printf("[ FAILED ] signal 0x%x !=3D expected 0x%x\n", sig, sigo)= ; \ + err +=3D 1; = \ + } = \ + = \ + return err; = \ +} + +TEST_DIVIDE_TO_INTEGER(diebr, int, "x", float, "f") +TEST_DIVIDE_TO_INTEGER(didbr, long, "lx", double, "lf") + +int main(void) +{ + struct sigaction act =3D { + .sa_sigaction =3D sigfpe_handler, + .sa_flags =3D SA_SIGINFO, + }; + int err =3D 0; + + /* Set up SIG handler */ + if (sigaction(SIGFPE, &act, NULL)) { + printf("[ FAILED ] sigaction(SIGFPE) failed\n"); + return EXIT_FAILURE; + } + + /* 451 / 460 */ + err +=3D test_diebr(0x43e1f1f1, 0x43e61616, 7, 0, + 0x43e1f1f1, 0, 0, 0, 0); + + /* 480 / 0 */ + err +=3D test_diebr(0x43f00000, 0, 0, 0, + 0x7fc00000, 0x7fc00000, 1, 0x800000, 0); + + /* QNaN / QNaN */ + err +=3D test_diebr(0xffffffff, 0xffffffff, 0, 0, + 0xffffffff, 0xffffffff, 1, 0, 0); + + /* -2.08E-8 / -2.08E-8 */ + err +=3D test_diebr(0xb2b2b2b2, 0xb2b2b2b2, 0, 0, + 0x80000000, 0x3f800000, 0, 0, 0); + + /* + * Test partial remainder without quotient scaling (cc2). + * + * a =3D 12401981 / 268435456 + * b =3D -5723991 / 72057594037927936 + * q =3D a / b =3D -3329131425038336 / 5723991 =3D~ -581610178.1 + * n =3D round(q, float32, nearest_even) =3D -581610176 + * r_precise =3D a - b * n =3D 189155 / 1125899906842624 + * r =3D round(r_precise, float32, nearest_even) =3D r_precise + */ + err +=3D test_diebr(0x3d3d3d3d, 0xaeaeaeae, 0, 0, + 0x2f38b8c0, 0xce0aaaab, 2, 0, 0); + + /* 1.07E-31 / 2.19 */ + err +=3D test_diebr(0x0c0c0c0c, 0x400c0c0c, 6, 0, + 0xc00c0c0c, 0x3f800000, 0, 0x80000, 0); + + /* + * Test partial remainder with quotient scaling (cc3). + * + * a =3D 298343530578310714772108083200 + * b =3D -592137/10384593717069655257060992658440192 + * q =3D a / b + * =3D -103272545105730134013704301472178067414107728960487231565332= 4800 / + * 197379 + * =3D~ -5232195173029052432817285601415452880707052369324357280426.6 + * n =3D round(q, float32, nearest_even) + * =3D -5232194943010009439437691768433469154159343131709361094656 + * n / 2^192 =3D -6992213 / 8388608 + * r_precise =3D a - b * n =3D 13115851209189604982784 + * r =3D round(r_precise, float32, nearest_even) =3D r_precise + */ + err +=3D test_diebr(0x7070ffff, 0x90909090, 0, 0, + 0x6431c0c0, 0xbf5562aa, 3, 0, 0); + + /* + * Test large, but representable quotient. + * + * a =3D -12040119 / 549755813888 + * b =3D 1 / 38685626227668133590597632 + * q =3D a / b =3D -847248053779631702016 + * n =3D round(q, float32, to_odd) =3D q + * r_precise =3D a - b * n =3D -0 + * r =3D round(r_precise, float32, nearest_even) =3D -0 + */ + err +=3D test_diebr(0xb7b7b7b7, 0x15000000, 7, 0, + 0x80000000, 0xe237b7b7, 0, 0, 0); + + /* 0 / 0 */ + err +=3D test_diebr(0, 0, 1, 0, + 0x7fc00000, 0x7fc00000, 1, 0x800000, 0); + + /* 4.3E-33 / -2.08E-8 with SIGFPE */ + err +=3D test_diebr(0x09b2b2b2, 0xb2b2b2b2, 0, 0xfc000007, + 0xb2b2b2b1, 0xbf800000, 0, 0xfc000807, SIGFPE); + + /* + * Test tiny remainder scaling when FPC Underflow Mask is set. + * + * 1.19E-39 / -1.28E-9 =3D { r =3D 1.19E-39 * 2^192, n =3D -0 } + */ + err +=3D test_diebr(0x000d0100, 0xb0b0b0b0, 6, 0xfc000000, + 0x5ed01000, 0x80000000, 0, 0xfc001000, SIGFPE); + + /* + * Test "inexact and incremented" DXC. + * + * a =3D 53555504 + * b =3D -520849213389117849600 + * q =3D a / b =3D -3347219 / 32553075836819865600 + * n =3D round(q, float32, to_odd) =3D -1 + * r_precise =3D a - b * n =3D -520849213389064294096 + * r =3D round(r_precise, float32, to_odd) =3D -520849213389117849600 + * abs(r) - abs(r_precise) =3D 53555504 + */ + err +=3D test_diebr(0x4c4c4c4c, 0xe1e1e1e1, 0, 0xfc000007, + 0xe1e1e1e1, 0xbf800000, 0, 0xfc000c07, SIGFPE); + + /* 0 / 0 with SIGFPE */ + err +=3D test_diebr(0, 0, 0, 0xfc000007, + 0, 0x12345678, 0, 0xfc008007, SIGFPE); + + /* 5.76E-16 / 5.39E+34 */ + err +=3D test_diebr(0x26262626, 0x79262626, 6, 0, + 0xf9262626, 0x3f800000, 0, 0x80000, 0); + + /* -4.97E+17 / 2.03E-38 */ + err +=3D test_diebr(0xdcdcdcdc, 0x00dcdcdc, 7, 0xfc000000, + 0x80000000, 0xbb800000, 1, 0xfc000000, 0); + + /* -1.23E+17 / SNaN */ + err +=3D test_diebr(0xdbdb240b, 0xffac73ff, 4, 0, + 0xffec73ff, 0xffec73ff, 1, 0x800000, 0); + + /* 2.34E-38 / 3.27E-33 with SIGFPE */ + err +=3D test_diebr(0x00ff0987, 0x0987c6f6, 6, 0x08000000, + 0x8987c6b6, 0x3f800000, 0, 0x8000800, SIGFPE); + + /* -5.93E+11 / -2.7E+4 */ + err +=3D test_diebr(0xd30a0040, 0xc6d30a00, 0, 0xc4000000, + 0xc74a4400, 0x4ba766c6, 2, 0xc4000000, 0); + + /* 9.86E-32 / -inf */ + err +=3D test_diebr(0x0c000029, 0xff800000, 0, 0, + 0xc000029, 0x80000000, 0, 0, 0); + + /* QNaN / SNaN */ + err +=3D test_diebr(0xffff94ff, 0xff94ff24, 4, 7, + 0xffd4ff24, 0xffd4ff24, 1, 0x800007, 0); + + /* 2.8E-43 / -inf */ + err +=3D test_diebr(0x000000c8, 0xff800000, 0, 0x7c000007, + 0x000000c8, 0x80000000, 0, 0x7c000007, 0); + + /* -1.7E+38 / -inf */ + err +=3D test_diebr(0xff00003d, 0xff800000, 0, 0, + 0xff00003d, 0, 0, 0, 0); + + /* 1.94E-304 / 1.94E-304 */ + err +=3D test_didbr(0x00e100e100e100e1, 0x00e100e100e100e1, 0, 1, + 0, 0x3ff0000000000000, 0, 1, 0); + + /* 4.82E-299 / 5.29E-308 */ + err +=3D test_didbr(0x0200230200230200, 0x0023020023020023, 0, 0, + 0x8001a017d247b3f4, 0x41cb2aa05f000000, 0, 0, 0); + + /* -1.38E-75 / -3.77E+208 */ + err +=3D test_didbr(0xb063eb3d63b063eb, 0xeb3d63b063eb3d63, 3, 0xe8000= 000, + 0x6b3d63b063eb3d63, 0x3ff0000000000000, 0, 0xe8000c0= 0, + SIGFPE); + + /* 4.78E-299 / 6.88E-315 */ + err +=3D test_didbr(0x0200000000000000, 0x0000000053020000, 0, 0, + 0x8000000020820000, 0x4338ac20dd47c6c1, 0, 0, 0); + + return err ? EXIT_FAILURE : EXIT_SUCCESS; +} --=20 2.52.0