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This allow to get rid of TARGET_AARCH64 in target/arm/helper.h. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper-mve.h | 14 ++++++++++++++ target/arm/helper.h | 2 -- target/arm/tcg/{helper-mve.h =3D> helper-mve-defs.h} | 0 target/arm/tcg/mve_helper.c | 4 ++++ target/arm/tcg/translate-mve.c | 1 + target/arm/tcg/translate.c | 1 + 6 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 target/arm/helper-mve.h rename target/arm/tcg/{helper-mve.h =3D> helper-mve-defs.h} (100%) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h new file mode 100644 index 00000000000..32ef3f64661 --- /dev/null +++ b/target/arm/helper-mve.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_MVE_H +#define HELPER_MVE_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-mve-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_MVE_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index f340a49a28a..44c7f3ed751 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -7,5 +7,3 @@ #include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif - -#include "tcg/helper-mve.h" diff --git a/target/arm/tcg/helper-mve.h b/target/arm/tcg/helper-mve-defs.h similarity index 100% rename from target/arm/tcg/helper-mve.h rename to target/arm/tcg/helper-mve-defs.h diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 63ddcf3fecf..f33642df1f9 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-mve.h" #include "internals.h" #include "vec_internal.h" #include "exec/helper-proto.h" @@ -27,6 +28,9 @@ #include "fpu/softfloat.h" #include "crypto/clmul.h" =20 +#define HELPER_H "tcg/helper-mve-defs.h" +#include "exec/helper-info.c.inc" + static uint16_t mve_eci_mask(CPUARMState *env) { /* diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index b1a8d6a65c0..4ca88f4d3a3 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "helper-mve.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 63735d97898..febb7f1532a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -28,6 +28,7 @@ #include "cpregs.h" #include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper-mve.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 10 Feb 2026 12:15:47 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: anjo@rev.ng, Jim MacArthur , kvm@vger.kernel.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson Subject: [PATCH v3 02/12] target/arm: extract helper-a64.h from helper.h Date: Tue, 10 Feb 2026 12:15:30 -0800 Message-ID: <20260210201540.1405424-3-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260210201540.1405424-1-pierrick.bouvier@linaro.org> References: <20260210201540.1405424-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770754602900158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper-a64.h | 14 ++++++++++++++ target/arm/helper.h | 1 - target/arm/tcg/{helper-a64.h =3D> helper-a64-defs.h} | 0 target/arm/tcg/helper-a64.c | 4 ++++ target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/pauth_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/vec_helper.c | 1 + 9 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 target/arm/helper-a64.h rename target/arm/tcg/{helper-a64.h =3D> helper-a64-defs.h} (100%) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h new file mode 100644 index 00000000000..cda7e039b72 --- /dev/null +++ b/target/arm/helper-a64.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_A64_H +#define HELPER_A64_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-a64-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_A64_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 44c7f3ed751..79f8de1e169 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -3,7 +3,6 @@ #include "tcg/helper.h" =20 #ifdef TARGET_AARCH64 -#include "tcg/helper-a64.h" #include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64-defs.h similarity index 100% rename from target/arm/tcg/helper-a64.h rename to target/arm/tcg/helper-a64-defs.h diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index e4d2c2e3928..07ddfb895dd 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" +#include "helper-a64.h" #include "qemu/host-utils.h" #include "qemu/log.h" #include "qemu/main-loop.h" @@ -43,6 +44,9 @@ #endif #include "vec_internal.h" =20 +#define HELPER_H "tcg/helper-a64-defs.h" +#include "exec/helper-info.c.inc" + /* C2.4.7 Multiply and divide */ /* special cases for 0 and LLONG_MIN are mandated by the standard */ uint64_t HELPER(udiv64)(uint64_t num, uint64_t den) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 08b8e7176a6..01b7f099f4a 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -31,6 +31,7 @@ #endif #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" +#include "helper-a64.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index c591c3052c3..5a20117ae89 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -22,6 +22,7 @@ #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" +#include "helper-a64.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index c442fcb540d..0600eea47c7 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" +#include "helper-a64.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7a8cd99e004..1a54337b6a8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "exec/target_page.h" +#include "helper-a64.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 33a136b90a6..7451a283efa 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "helper-a64.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 10 Feb 2026 12:15:47 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: anjo@rev.ng, Jim MacArthur , kvm@vger.kernel.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson Subject: [PATCH v3 03/12] target/arm: extract helper-sve.h from helper.h Date: Tue, 10 Feb 2026 12:15:31 -0800 Message-ID: <20260210201540.1405424-4-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260210201540.1405424-1-pierrick.bouvier@linaro.org> References: <20260210201540.1405424-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770754574829158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper-sve.h | 14 ++++++++++++++ target/arm/helper.h | 1 - target/arm/tcg/{helper-sve.h =3D> helper-sve-defs.h} | 0 target/arm/tcg/gengvec64.c | 3 ++- target/arm/tcg/sve_helper.c | 3 +++ target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/translate-sme.c | 2 ++ target/arm/tcg/translate-sve.c | 2 ++ target/arm/tcg/vec_helper.c | 1 + 9 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 target/arm/helper-sve.h rename target/arm/tcg/{helper-sve.h =3D> helper-sve-defs.h} (100%) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h new file mode 100644 index 00000000000..ae4f46c70a0 --- /dev/null +++ b/target/arm/helper-sve.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_SVE_H +#define HELPER_SVE_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-sve-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_SVE_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 79f8de1e169..2f724643d39 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -3,6 +3,5 @@ #include "tcg/helper.h" =20 #ifdef TARGET_AARCH64 -#include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve-defs.h similarity index 100% rename from target/arm/tcg/helper-sve.h rename to target/arm/tcg/helper-sve-defs.h diff --git a/target/arm/tcg/gengvec64.c b/target/arm/tcg/gengvec64.c index c425d2b1490..c7bdd1ea82f 100644 --- a/target/arm/tcg/gengvec64.c +++ b/target/arm/tcg/gengvec64.c @@ -18,10 +18,11 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" =20 - static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) { tcg_gen_rotli_i64(d, m, 1); diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 0600eea47c7..16e528e41a6 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -25,6 +25,7 @@ #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "helper-a64.h" +#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" @@ -38,6 +39,8 @@ #include "user/page-protection.h" #endif =20 +#define HELPER_H "tcg/helper-sve-defs.h" +#include "exec/helper-info.c.inc" =20 /* Return a value for NZCV as per the ARM PredTest pseudofunction. * diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1a54337b6a8..31fb2ea9cc3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "exec/target_page.h" #include "helper-a64.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 091c56da4f4..463ece97ab8 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -18,6 +18,8 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" =20 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 64adb5c1ce3..c68a44aff8c 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -18,6 +18,8 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 7451a283efa..bc64c8ff374 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "helper-a64.h" +#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 10 Feb 2026 12:15:48 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: anjo@rev.ng, Jim MacArthur , kvm@vger.kernel.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson Subject: [PATCH v3 04/12] target/arm: extract helper-sme.h from helper.h Date: Tue, 10 Feb 2026 12:15:32 -0800 Message-ID: <20260210201540.1405424-5-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260210201540.1405424-1-pierrick.bouvier@linaro.org> References: <20260210201540.1405424-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770754616259154100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper-sme.h | 14 ++++++++++++++ target/arm/helper.h | 4 ---- target/arm/tcg/{helper-sme.h =3D> helper-sme-defs.h} | 0 target/arm/tcg/sme_helper.c | 3 +++ target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/translate-sme.c | 1 + target/arm/tcg/translate-sve.c | 1 + target/arm/tcg/vec_helper.c | 1 + 8 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 target/arm/helper-sme.h rename target/arm/tcg/{helper-sme.h =3D> helper-sme-defs.h} (100%) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h new file mode 100644 index 00000000000..27c85fdeef1 --- /dev/null +++ b/target/arm/helper-sme.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_SME_H +#define HELPER_SME_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-sme-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_SME_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 2f724643d39..b1e83196b3b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,7 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 #include "tcg/helper.h" - -#ifdef TARGET_AARCH64 -#include "tcg/helper-sme.h" -#endif diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme-defs.h similarity index 100% rename from target/arm/tcg/helper-sme.h rename to target/arm/tcg/helper-sme-defs.h diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 075360d8b8a..7729732369f 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -22,6 +22,7 @@ #include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "helper-sme.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" @@ -29,6 +30,8 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" =20 +#define HELPER_H "tcg/helper-sme-defs.h" +#include "exec/helper-info.c.inc" =20 static bool vectors_overlap(ARMVectorReg *x, unsigned nx, ARMVectorReg *y, unsigned ny) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 31fb2ea9cc3..5d261a5e32b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "exec/target_page.h" #include "helper-a64.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 463ece97ab8..7d25ac5a51f 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index c68a44aff8c..db25636fa3b 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index bc64c8ff374..a070ac90579 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "helper-a64.h" +#include "helper-sme.h" #include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Our new helper pattern always include helper-*-common.h, which ends up including include/tcg/tcg.h, which contains one occurrence of CONFIG_USER_ONLY. Thus, common files not being duplicated between system and target relying on helpers will fail to compile. Existing occurrences are: - target/arm/tcg/arith_helper.c - target/arm/tcg/crypto_helper.c This occurrence of CONFIG_USER_ONLY is for defining variable tcg_use_softmmu, and we rely on dead code elimination with it in various tcg-target.c.inc. Thus, move its definition to tcg/tcg-internal.h, so helpers can be included by common files. Also, change it to a define, as it has fixed values for now. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- include/tcg/tcg.h | 6 ------ tcg/tcg-internal.h | 6 ++++++ tcg/tcg.c | 4 ---- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 60942ce05c2..45c7e118c3d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -445,12 +445,6 @@ static inline bool temp_readonly(TCGTemp *ts) return ts->kind >=3D TEMP_FIXED; } =20 -#ifdef CONFIG_USER_ONLY -extern bool tcg_use_softmmu; -#else -#define tcg_use_softmmu true -#endif - extern __thread TCGContext *tcg_ctx; extern const void *tcg_code_gen_epilogue; extern uintptr_t tcg_splitwx_diff; diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2cbfb5d5caa..26156846120 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -34,6 +34,12 @@ extern TCGContext **tcg_ctxs; extern unsigned int tcg_cur_ctxs; extern unsigned int tcg_max_ctxs; =20 +#ifdef CONFIG_USER_ONLY +#define tcg_use_softmmu false +#else +#define tcg_use_softmmu true +#endif + void tcg_region_init(size_t tb_size, int splitwx, unsigned max_threads); bool tcg_region_alloc(TCGContext *s); void tcg_region_initial_alloc(TCGContext *s); diff --git a/tcg/tcg.c b/tcg/tcg.c index e7bf4dad4ee..3111e1f4265 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -236,10 +236,6 @@ static TCGAtomAlign atom_and_align_for_opc(TCGContext = *s, MemOp opc, MemOp host_atom, bool allow_two= _ops) __attribute__((unused)); =20 -#ifdef CONFIG_USER_ONLY -bool tcg_use_softmmu; -#endif - TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770754657; cv=none; d=zohomail.com; s=zohoarc; b=UPI8OHYMPVyMG6a2YwjKkeKO7jv6ew3nvKZjN9RjaqiWq9ZJNFQccm3/+jgFikXUB0YfjmXu+DKf0XjQt+9CKZvHX7jCrzj+IxMFzcIJNW91q9b9PR+g0mtsrsm9bL3Htxr9lP+2rdkgQsTwUPnEGtcbx1YH9H5lkgfoMqtI/7Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770754657; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XNDpa+JQHOniHzUT0Ozar04kohZ49T4fHdN5SF9nmyk=; b=hh2EgSFYA9Gxs2FCjCb6ZnhuVHQoKVIZfnFT+SqPypNJbhU+RSZ0QLWLJ3a5aRrJLahzaWBmO9TQTOmMZA+IRDIQcBCTVhLeq50U+F+bHx0nzzacpuOloJAej0AX9rpN2D1YhodtmkKxpX/ED7Cjh4veddggAmXx2L1WyQu3eaA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770754657287352.1033225421436; Tue, 10 Feb 2026 12:17:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpu9d-0008QC-Ox; Tue, 10 Feb 2026 15:16:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpu9K-0007ru-S2 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:55 -0500 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpu9I-0008Ai-7W for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:54 -0500 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-c61342a69b9so1640144a12.0 for ; Tue, 10 Feb 2026 12:15:51 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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This way, all helpers use the same pattern, and helper include details are limited to those headers. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper.h | 13 ++++++++++++- target/arm/tcg/{helper.h =3D> helper-defs.h} | 0 target/arm/tcg/translate.h | 2 +- target/arm/debug_helper.c | 4 +--- target/arm/helper.c | 5 +++-- target/arm/tcg/arith_helper.c | 4 +--- target/arm/tcg/crypto_helper.c | 4 +--- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/hflags.c | 4 +--- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/mve_helper.c | 2 +- target/arm/tcg/neon_helper.c | 4 +--- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/pauth_helper.c | 2 +- target/arm/tcg/psci.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/arm/tcg/tlb_helper.c | 4 +--- target/arm/tcg/translate.c | 6 +----- target/arm/tcg/vec_helper.c | 2 +- target/arm/tcg/vfp_helper.c | 4 +--- 22 files changed, 34 insertions(+), 40 deletions(-) rename target/arm/tcg/{helper.h =3D> helper-defs.h} (100%) diff --git a/target/arm/helper.h b/target/arm/helper.h index b1e83196b3b..b1c26c180ea 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,3 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#include "tcg/helper.h" +#ifndef HELPER__H +#define HELPER__H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER__H */ diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper-defs.h similarity index 100% rename from target/arm/tcg/helper.h rename to target/arm/tcg/helper-defs.h diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 1e30d7c77c3..027769271c9 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -6,7 +6,7 @@ #include "tcg/tcg-op-gvec.h" #include "exec/translator.h" #include "exec/translation-block.h" -#include "exec/helper-gen.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" =20 diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 579516e1541..ec6a2b0c179 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -8,15 +8,13 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "cpregs.h" #include "exec/watchpoint.h" #include "system/tcg.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - #ifdef CONFIG_TCG /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) diff --git a/target/arm/helper.c b/target/arm/helper.c index e86ceb130ce..70227263612 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10,6 +10,7 @@ #include "qemu/log.h" #include "trace.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "exec/page-protection.h" @@ -36,8 +37,8 @@ #include "target/arm/gtimer.h" #include "qemu/plugin.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" +#define HELPER_H "tcg/helper-defs.h" +#include "exec/helper-info.c.inc" =20 static void switch_mode(CPUARMState *env, int mode); =20 diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c index 97c6362992c..cc081c8f966 100644 --- a/target/arm/tcg/arith_helper.c +++ b/target/arm/tcg/arith_helper.c @@ -8,11 +8,9 @@ #include "qemu/osdep.h" #include "qemu/bswap.h" #include "qemu/crc32c.h" +#include "helper.h" #include /* for crc32 */ =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Note that signed overflow is undefined in C. The following routines are * careful to use unsigned types where modulo arithmetic is required. diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 3428bd1bf0b..11977cb7723 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -15,11 +15,9 @@ #include "tcg/tcg-gvec-desc.h" #include "crypto/aes-round.h" #include "crypto/sm4.h" +#include "helper.h" #include "vec_internal.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - union CRYPTO_STATE { uint8_t bytes[16]; uint32_t words[4]; diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 07ddfb895dd..2dec587d386 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -21,7 +21,7 @@ #include "qemu/units.h" #include "cpu.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-a64.h" #include "qemu/host-utils.h" #include "qemu/log.h" diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 5c9b9bec3b2..7e6f8d36475 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -7,15 +7,13 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - static inline bool fgt_svc(CPUARMState *env, int el) { /* diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 3fb24c77900..5a75e8b3e11 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -8,10 +8,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/bitops.h" #include "qemu/log.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 01b7f099f4a..a9fb979f639 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "exec/target_page.h" #include "exec/page-protection.h" @@ -32,7 +33,6 @@ #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "helper-a64.h" -#include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" #include "qapi/error.h" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index f33642df1f9..a67d90d6c75 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -19,10 +19,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "helper-mve.h" #include "internals.h" #include "vec_internal.h" -#include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" #include "tcg/tcg.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index 8d288f3a700..69147969b23 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -9,13 +9,11 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "vec_internal.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 4fbd219555d..5a510730ece 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 5a20117ae89..67c0d59d9e9 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -19,11 +19,11 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" #include "helper-a64.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" =20 diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 2d409301578..bca6058e41a 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -18,7 +18,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "kvm-consts.h" #include "qemu/main-loop.h" #include "system/runstate.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 7729732369f..ab5999c5925 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "internals.h" #include "tcg/tcg-gvec-desc.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-sme.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/helper-retaddr.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 16e528e41a6..062d8881bd0 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -21,9 +21,9 @@ #include "cpu.h" #include "internals.h" #include "exec/page-protection.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" +#include "helper.h" #include "helper-a64.h" #include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5c689d3b69f..565954269f9 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -7,12 +7,10 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Returns true if the stage 1 translation regime is using LPAE format page * tables. Used when raising alignment exceptions, whose FSR changes depen= ding diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index febb7f1532a..982c83ef42a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -26,14 +26,10 @@ #include "arm_ldst.h" #include "semihosting/semihost.h" #include "cpregs.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper.h" #include "helper-mve.h" =20 -#define HELPER_H "helper.h" -#include "exec/helper-info.c.inc" -#undef HELPER_H - #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index a070ac90579..1223b843bf1 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-a64.h" #include "helper-sme.h" #include "helper-sve.h" diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index e156e3774ad..45f2eb0930f 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -19,14 +19,12 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "fpu/softfloat.h" #include "qemu/log.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Set the float_status behaviour to match the Arm defaults: * * tininess-before-rounding --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770754691; cv=none; d=zohomail.com; s=zohoarc; b=lvcDIJVotiknzsCFHCXigNhSLp20nSR284LmdkEmqFBdTmRXk3T7rzYO8o/CUbhfq/XaYIzdvCIyuXUNHGI3gS9Z6EqRRLgL2Grx+KDOKMtqtr/iBc5Qws5Cpo9CrROZMlxShCIBWFeR5mpIu4hUqDFGlgF/nkz82x6g7auNHGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770754691; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YT0JTFA3AzBVK9ga3zHInUh8zrTWOg2tWQne/H6KqWQ=; b=aQE9zOWLqTPA+8gtdzPNn/GDSyrqJsY5c5sWb1wZpMt8GUI3oZDkuiLbJhuASkBRqbFoiA5AU2b4iC9xPusvEsN2dlj2Kf2RQt45sQ2qUN9FGvQSKRenKWqmbmKih2wrRn6tNUyl8zWq3IwyD1fBeVBe2ctyuS33lXZ7c7+gCqA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770754691522530.38469686129; Tue, 10 Feb 2026 12:18:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpu9i-0000Sm-8J; Tue, 10 Feb 2026 15:16:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpu9K-0007rv-RR for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:55 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpu9I-0008BB-VW for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:54 -0500 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-2ab077e3f32so8457475ad.3 for ; Tue, 10 Feb 2026 12:15:52 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier --- target/arm/tcg/psci.c | 2 +- target/arm/tcg/meson.build | 5 +---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index bca6058e41a..56754bde951 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -68,7 +68,7 @@ void arm_handle_psci_call(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; uint64_t param[4]; uint64_t context_id, mpidr; - target_ulong entry; + uint64_t entry; int32_t ret =3D 0; int i; =20 diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 1b115656c46..144a8cd9474 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -49,10 +49,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sve_helper.c', )) =20 -arm_system_ss.add(files( - 'psci.c', -)) - arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) =20 @@ -67,6 +63,7 @@ arm_common_system_ss.add(files( 'cpregs-at.c', 'hflags.c', 'neon_helper.c', + 'psci.c', 'tlb_helper.c', 'tlb-insns.c', 'vfp_helper.c', --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770754685; cv=none; d=zohomail.com; s=zohoarc; b=lW1m4010a2Y0wtn+sDREaxT5Z4tgj/+TK6tq8H85Av5dHsRwIF4E6NAN21Iwa7F+seatEqkHxFWhrNn/sVu5ahllrVa7zY8PSI+ied2uyR/FoE0WvBxRHMpdKIAMzToKKylhxrdB7rsaoTftzXzHdmgbkFmAVODKKkgZVYJoKYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770754685; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GM4hRM+kWCtJL3aHlm91z/yjeKpryvOkWyfDNo2+duQ=; b=iMnAwbVHIXogGNaNU7LBr4vxndE3jVo05EEE4J+U5wjfi52D2Lu/1rEKreSU5mAhrbMhgz17X1E9XxILKjyl2CqzqPhbd8Qev1lFvyPjoYMDkSUasl0A3gy12H0+/fC0aTrjcQ73Sz8Wd63Zkm2bENEbxmotItZc2e4csHOrpaE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177075468578119.448904009482135; Tue, 10 Feb 2026 12:18:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpu9d-0008MW-8Y; Tue, 10 Feb 2026 15:16:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpu9L-0007wn-Su for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:57 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpu9K-0008BV-0S for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:55 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-8230c2d3128so641997b3a.0 for ; Tue, 10 Feb 2026 12:15:53 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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Tue, 10 Feb 2026 12:15:52 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: anjo@rev.ng, Jim MacArthur , kvm@vger.kernel.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier , Peter Maydell , qemu-arm@nongnu.org, Richard Henderson Subject: [PATCH v3 08/12] target/arm/tcg/cpu-v7m.c: make compilation unit common Date: Tue, 10 Feb 2026 12:15:36 -0800 Message-ID: <20260210201540.1405424-9-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260210201540.1405424-1-pierrick.bouvier@linaro.org> References: <20260210201540.1405424-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770754687393154100 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier --- target/arm/tcg/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 144a8cd9474..08ac5ec9906 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -49,7 +49,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sve_helper.c', )) =20 -arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) +arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c= ')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) =20 arm_common_ss.add(zlib) --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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As well, DO_3OP_PAIR was defined twice, so rename the second variant to DO_3OP_PAIR_NO_STATUS to reflect what it does. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/tcg/vec_internal.h | 49 ++++++++ target/arm/tcg/vec_helper.c | 225 +++------------------------------- target/arm/tcg/vec_helper64.c | 142 +++++++++++++++++++++ target/arm/tcg/meson.build | 4 +- 4 files changed, 212 insertions(+), 208 deletions(-) create mode 100644 target/arm/tcg/vec_helper64.c diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index cf41b03dbcd..4edd2b4fc18 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -450,4 +450,53 @@ static inline void depositn(uint64_t *p, unsigned pos, } } =20 +#define DO_3OP(NAME, FUNC, TYPE) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + intptr_t i, oprsz =3D simd_oprsz(desc); = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + for (i =3D 0; i < oprsz / sizeof(TYPE); i++) { = \ + d[i] =3D FUNC(n[i], m[i], stat); = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + +#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + ARMVectorReg scratch; = \ + intptr_t oprsz =3D simd_oprsz(desc); = \ + intptr_t half =3D oprsz / sizeof(TYPE) / 2; = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + if (unlikely(d =3D=3D m)) { = \ + m =3D memcpy(&scratch, m, oprsz); = \ + } = \ + for (intptr_t i =3D 0; i < half; ++i) { = \ + d[H(i)] =3D FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); = \ + } = \ + for (intptr_t i =3D 0; i < half; ++i) { = \ + d[H(i + half)] =3D FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + +#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) = \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + intptr_t i, j, oprsz =3D simd_oprsz(desc); = \ + intptr_t segment =3D MIN(16, oprsz) / sizeof(TYPE); = \ + intptr_t idx =3D simd_data(desc); = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + for (i =3D 0; i < oprsz / sizeof(TYPE); i +=3D segment) { = \ + TYPE mm =3D m[H(i + idx)]; = \ + for (j =3D 0; j < segment; j++) { = \ + d[i + j] =3D ADD(d[i + j], MUL(n[i + j], mm, stat), stat); = \ + } = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + #endif /* TARGET_ARM_VEC_INTERNAL_H */ diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 1223b843bf1..91e98d28aea 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -20,9 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "helper.h" -#include "helper-a64.h" -#include "helper-sme.h" -#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" @@ -1458,18 +1455,6 @@ static float32 float32_rsqrts_nf(float32 op1, float3= 2 op2, float_status *stat) return float32_div(op1, float32_two, stat); } =20 -#define DO_3OP(NAME, FUNC, TYPE) \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - intptr_t i, oprsz =3D simd_oprsz(desc); = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - for (i =3D 0; i < oprsz / sizeof(TYPE); i++) { = \ - d[i] =3D FUNC(n[i], m[i], stat); = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - DO_3OP(gvec_fadd_b16, bfloat16_add, float16) DO_3OP(gvec_fadd_h, float16_add, float16) DO_3OP(gvec_fadd_s, float32_add, float32) @@ -1541,49 +1526,6 @@ DO_3OP(gvec_recps_nf_s, float32_recps_nf, float32) DO_3OP(gvec_rsqrts_nf_h, float16_rsqrts_nf, float16) DO_3OP(gvec_rsqrts_nf_s, float32_rsqrts_nf, float32) =20 -#ifdef TARGET_AARCH64 -DO_3OP(gvec_fdiv_h, float16_div, float16) -DO_3OP(gvec_fdiv_s, float32_div, float32) -DO_3OP(gvec_fdiv_d, float64_div, float64) - -DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16) -DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32) -DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64) - -DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) -DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) -DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) - -DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) -DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) -DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) - -DO_3OP(gvec_ah_recps_h, helper_recpsf_ah_f16, float16) -DO_3OP(gvec_ah_recps_s, helper_recpsf_ah_f32, float32) -DO_3OP(gvec_ah_recps_d, helper_recpsf_ah_f64, float64) - -DO_3OP(gvec_ah_rsqrts_h, helper_rsqrtsf_ah_f16, float16) -DO_3OP(gvec_ah_rsqrts_s, helper_rsqrtsf_ah_f32, float32) -DO_3OP(gvec_ah_rsqrts_d, helper_rsqrtsf_ah_f64, float64) - -DO_3OP(gvec_ah_fmax_h, helper_vfp_ah_maxh, float16) -DO_3OP(gvec_ah_fmax_s, helper_vfp_ah_maxs, float32) -DO_3OP(gvec_ah_fmax_d, helper_vfp_ah_maxd, float64) - -DO_3OP(gvec_ah_fmin_h, helper_vfp_ah_minh, float16) -DO_3OP(gvec_ah_fmin_s, helper_vfp_ah_mins, float32) -DO_3OP(gvec_ah_fmin_d, helper_vfp_ah_mind, float64) - -DO_3OP(gvec_fmax_b16, bfloat16_max, bfloat16) -DO_3OP(gvec_fmin_b16, bfloat16_min, bfloat16) -DO_3OP(gvec_fmaxnum_b16, bfloat16_maxnum, bfloat16) -DO_3OP(gvec_fminnum_b16, bfloat16_minnum, bfloat16) -DO_3OP(gvec_ah_fmax_b16, helper_sme2_ah_fmax_b16, bfloat16) -DO_3OP(gvec_ah_fmin_b16, helper_sme2_ah_fmin_b16, bfloat16) - -#endif -#undef DO_3OP - /* Non-fused multiply-add (unlike float16_muladd etc, which are fused) */ static float16 float16_muladd_nf(float16 dest, float16 op1, float16 op2, float_status *stat) @@ -1769,23 +1711,6 @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8) =20 #undef DO_MLA_IDX =20 -#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) = \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - intptr_t i, j, oprsz =3D simd_oprsz(desc); = \ - intptr_t segment =3D MIN(16, oprsz) / sizeof(TYPE); = \ - intptr_t idx =3D simd_data(desc); = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - for (i =3D 0; i < oprsz / sizeof(TYPE); i +=3D segment) { = \ - TYPE mm =3D m[H(i + idx)]; = \ - for (j =3D 0; j < segment; j++) { = \ - d[i + j] =3D ADD(d[i + j], MUL(n[i + j], mm, stat), stat); = \ - } = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - #define nop(N, M, S) (M) =20 DO_FMUL_IDX(gvec_fmul_idx_b16, nop, bfloat16_mul, float16, H2) @@ -1793,14 +1718,6 @@ DO_FMUL_IDX(gvec_fmul_idx_h, nop, float16_mul, float= 16, H2) DO_FMUL_IDX(gvec_fmul_idx_s, nop, float32_mul, float32, H4) DO_FMUL_IDX(gvec_fmul_idx_d, nop, float64_mul, float64, H8) =20 -#ifdef TARGET_AARCH64 - -DO_FMUL_IDX(gvec_fmulx_idx_h, nop, helper_advsimd_mulxh, float16, H2) -DO_FMUL_IDX(gvec_fmulx_idx_s, nop, helper_vfp_mulxs, float32, H4) -DO_FMUL_IDX(gvec_fmulx_idx_d, nop, helper_vfp_mulxd, float64, H8) - -#endif - #undef nop =20 /* @@ -1812,8 +1729,6 @@ DO_FMUL_IDX(gvec_fmla_nf_idx_s, float32_add, float32_= mul, float32, H4) DO_FMUL_IDX(gvec_fmls_nf_idx_h, float16_sub, float16_mul, float16, H2) DO_FMUL_IDX(gvec_fmls_nf_idx_s, float32_sub, float32_mul, float32, H4) =20 -#undef DO_FMUL_IDX - #define DO_FMLA_IDX(NAME, TYPE, H, NEGX, NEGF) = \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, = \ float_status *stat, uint32_t desc) = \ @@ -2530,31 +2445,6 @@ void HELPER(neon_pmull_h)(void *vd, void *vn, void *= vm, uint32_t desc) clear_tail(d, 16, simd_maxsz(desc)); } =20 -#ifdef TARGET_AARCH64 -void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) -{ - int shift =3D simd_data(desc) * 8; - intptr_t i, opr_sz =3D simd_oprsz(desc); - uint64_t *d =3D vd, *n =3D vn, *m =3D vm; - - for (i =3D 0; i < opr_sz / 8; ++i) { - d[i] =3D clmul_8x4_even(n[i] >> shift, m[i] >> shift); - } -} - -void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc) -{ - intptr_t sel =3D H4(simd_data(desc)); - intptr_t i, opr_sz =3D simd_oprsz(desc); - uint32_t *n =3D vn, *m =3D vm; - uint64_t *d =3D vd; - - for (i =3D 0; i < opr_sz / 8; ++i) { - d[i] =3D clmul_32(n[2 * i + sel], m[2 * i + sel]); - } -} -#endif - #define DO_CMP0(NAME, TYPE, OP) \ void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ { \ @@ -2628,26 +2518,6 @@ DO_ABA(gvec_uaba_d, uint64_t) =20 #undef DO_ABA =20 -#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - ARMVectorReg scratch; = \ - intptr_t oprsz =3D simd_oprsz(desc); = \ - intptr_t half =3D oprsz / sizeof(TYPE) / 2; = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - if (unlikely(d =3D=3D m)) { = \ - m =3D memcpy(&scratch, m, oprsz); = \ - } = \ - for (intptr_t i =3D 0; i < half; ++i) { = \ - d[H(i)] =3D FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); = \ - } = \ - for (intptr_t i =3D 0; i < half; ++i) { = \ - d[H(i + half)] =3D FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - DO_3OP_PAIR(gvec_faddp_h, float16_add, float16, H2) DO_3OP_PAIR(gvec_faddp_s, float32_add, float32, H4) DO_3OP_PAIR(gvec_faddp_d, float64_add, float64, ) @@ -2668,19 +2538,7 @@ DO_3OP_PAIR(gvec_fminnump_h, float16_minnum, float16= , H2) DO_3OP_PAIR(gvec_fminnump_s, float32_minnum, float32, H4) DO_3OP_PAIR(gvec_fminnump_d, float64_minnum, float64, ) =20 -#ifdef TARGET_AARCH64 -DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2) -DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4) -DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, ) - -DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2) -DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4) -DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, ) -#endif - -#undef DO_3OP_PAIR - -#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ +#define DO_3OP_PAIR_NO_STATUS(NAME, FUNC, TYPE, H) \ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ { \ ARMVectorReg scratch; \ @@ -2700,29 +2558,29 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uin= t32_t desc) \ } =20 #define ADD(A, B) (A + B) -DO_3OP_PAIR(gvec_addp_b, ADD, uint8_t, H1) -DO_3OP_PAIR(gvec_addp_h, ADD, uint16_t, H2) -DO_3OP_PAIR(gvec_addp_s, ADD, uint32_t, H4) -DO_3OP_PAIR(gvec_addp_d, ADD, uint64_t, ) +DO_3OP_PAIR_NO_STATUS(gvec_addp_b, ADD, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_addp_h, ADD, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_addp_s, ADD, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_addp_d, ADD, uint64_t, /**/) #undef ADD =20 -DO_3OP_PAIR(gvec_smaxp_b, MAX, int8_t, H1) -DO_3OP_PAIR(gvec_smaxp_h, MAX, int16_t, H2) -DO_3OP_PAIR(gvec_smaxp_s, MAX, int32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_b, MAX, int8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_h, MAX, int16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_s, MAX, int32_t, H4) =20 -DO_3OP_PAIR(gvec_umaxp_b, MAX, uint8_t, H1) -DO_3OP_PAIR(gvec_umaxp_h, MAX, uint16_t, H2) -DO_3OP_PAIR(gvec_umaxp_s, MAX, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_b, MAX, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_h, MAX, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_s, MAX, uint32_t, H4) =20 -DO_3OP_PAIR(gvec_sminp_b, MIN, int8_t, H1) -DO_3OP_PAIR(gvec_sminp_h, MIN, int16_t, H2) -DO_3OP_PAIR(gvec_sminp_s, MIN, int32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_b, MIN, int8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_h, MIN, int16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_s, MIN, int32_t, H4) =20 -DO_3OP_PAIR(gvec_uminp_b, MIN, uint8_t, H1) -DO_3OP_PAIR(gvec_uminp_h, MIN, uint16_t, H2) -DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_b, MIN, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_h, MIN, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_s, MIN, uint32_t, H4) =20 -#undef DO_3OP_PAIR +#undef DO_3OP_PAIR_NO_STATUS =20 #define DO_VCVT_FIXED(NAME, FUNC, TYPE) \ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t des= c) \ @@ -2797,53 +2655,6 @@ DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32= _t) =20 #undef DO_VRINT_RMODE =20 -#ifdef TARGET_AARCH64 -void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc) -{ - const uint8_t *indices =3D vm; - size_t oprsz =3D simd_oprsz(desc); - uint32_t rn =3D extract32(desc, SIMD_DATA_SHIFT, 5); - bool is_tbx =3D extract32(desc, SIMD_DATA_SHIFT + 5, 1); - uint32_t table_len =3D desc >> (SIMD_DATA_SHIFT + 6); - union { - uint8_t b[16]; - uint64_t d[2]; - } result; - - /* - * We must construct the final result in a temp, lest the output - * overlaps the input table. For TBL, begin with zero; for TBX, - * begin with the original register contents. Note that we always - * copy 16 bytes here to avoid an extra branch; clearing the high - * bits of the register for oprsz =3D=3D 8 is handled below. - */ - if (is_tbx) { - memcpy(&result, vd, 16); - } else { - memset(&result, 0, 16); - } - - for (size_t i =3D 0; i < oprsz; ++i) { - uint32_t index =3D indices[H1(i)]; - - if (index < table_len) { - /* - * Convert index (a byte offset into the virtual table - * which is a series of 128-bit vectors concatenated) - * into the correct register element, bearing in mind - * that the table can wrap around from V31 to V0. - */ - const uint8_t *table =3D (const uint8_t *) - aa64_vfp_qreg(env, (rn + (index >> 4)) % 32); - result.b[H1(i)] =3D table[H1(index % 16)]; - } - } - - memcpy(vd, &result, 16); - clear_tail(vd, oprsz, simd_maxsz(desc)); -} -#endif - /* * NxN -> N highpart multiply * diff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c new file mode 100644 index 00000000000..249a257177e --- /dev/null +++ b/target/arm/tcg/vec_helper64.c @@ -0,0 +1,142 @@ +/* + * ARM AdvSIMD / SVE Vector Operations + * + * Copyright (c) 2026 Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "helper.h" +#include "helper-a64.h" +#include "helper-sme.h" +#include "helper-sve.h" +#include "tcg/tcg-gvec-desc.h" +#include "fpu/softfloat.h" +#include "qemu/int128.h" +#include "crypto/clmul.h" +#include "vec_internal.h" + +DO_3OP(gvec_fdiv_h, float16_div, float16) +DO_3OP(gvec_fdiv_s, float32_div, float32) +DO_3OP(gvec_fdiv_d, float64_div, float64) + +DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16) +DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32) +DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64) + +DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) +DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) +DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) + +DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) +DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) +DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) + +DO_3OP(gvec_ah_recps_h, helper_recpsf_ah_f16, float16) +DO_3OP(gvec_ah_recps_s, helper_recpsf_ah_f32, float32) +DO_3OP(gvec_ah_recps_d, helper_recpsf_ah_f64, float64) + +DO_3OP(gvec_ah_rsqrts_h, helper_rsqrtsf_ah_f16, float16) +DO_3OP(gvec_ah_rsqrts_s, helper_rsqrtsf_ah_f32, float32) +DO_3OP(gvec_ah_rsqrts_d, helper_rsqrtsf_ah_f64, float64) + +DO_3OP(gvec_ah_fmax_h, helper_vfp_ah_maxh, float16) +DO_3OP(gvec_ah_fmax_s, helper_vfp_ah_maxs, float32) +DO_3OP(gvec_ah_fmax_d, helper_vfp_ah_maxd, float64) + +DO_3OP(gvec_ah_fmin_h, helper_vfp_ah_minh, float16) +DO_3OP(gvec_ah_fmin_s, helper_vfp_ah_mins, float32) +DO_3OP(gvec_ah_fmin_d, helper_vfp_ah_mind, float64) + +DO_3OP(gvec_fmax_b16, bfloat16_max, bfloat16) +DO_3OP(gvec_fmin_b16, bfloat16_min, bfloat16) +DO_3OP(gvec_fmaxnum_b16, bfloat16_maxnum, bfloat16) +DO_3OP(gvec_fminnum_b16, bfloat16_minnum, bfloat16) +DO_3OP(gvec_ah_fmax_b16, helper_sme2_ah_fmax_b16, bfloat16) +DO_3OP(gvec_ah_fmin_b16, helper_sme2_ah_fmin_b16, bfloat16) + +#define nop(N, M, S) (M) + +DO_FMUL_IDX(gvec_fmulx_idx_h, nop, helper_advsimd_mulxh, float16, H2) +DO_FMUL_IDX(gvec_fmulx_idx_s, nop, helper_vfp_mulxs, float32, H4) +DO_FMUL_IDX(gvec_fmulx_idx_d, nop, helper_vfp_mulxd, float64, H8) + +#undef nop + +void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + int shift =3D simd_data(desc) * 8; + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; ++i) { + d[i] =3D clmul_8x4_even(n[i] >> shift, m[i] >> shift); + } +} + +void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t sel =3D H4(simd_data(desc)); + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint32_t *n =3D vn, *m =3D vm; + uint64_t *d =3D vd; + + for (i =3D 0; i < opr_sz / 8; ++i) { + d[i] =3D clmul_32(n[2 * i + sel], m[2 * i + sel]); + } +} + +DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2) +DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4) +DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, /**/) + +DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2) +DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4) +DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, /**/) + +void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc) +{ + const uint8_t *indices =3D vm; + size_t oprsz =3D simd_oprsz(desc); + uint32_t rn =3D extract32(desc, SIMD_DATA_SHIFT, 5); + bool is_tbx =3D extract32(desc, SIMD_DATA_SHIFT + 5, 1); + uint32_t table_len =3D desc >> (SIMD_DATA_SHIFT + 6); + union { + uint8_t b[16]; + uint64_t d[2]; + } result; + + /* + * We must construct the final result in a temp, lest the output + * overlaps the input table. For TBL, begin with zero; for TBX, + * begin with the original register contents. Note that we always + * copy 16 bytes here to avoid an extra branch; clearing the high + * bits of the register for oprsz =3D=3D 8 is handled below. + */ + if (is_tbx) { + memcpy(&result, vd, 16); + } else { + memset(&result, 0, 16); + } + + for (size_t i =3D 0; i < oprsz; ++i) { + uint32_t index =3D indices[H1(i)]; + + if (index < table_len) { + /* + * Convert index (a byte offset into the virtual table + * which is a series of 128-bit vectors concatenated) + * into the correct register element, bearing in mind + * that the table can wrap around from V31 to V0. + */ + const uint8_t *table =3D (const uint8_t *) + aa64_vfp_qreg(env, (rn + (index >> 4)) % 32); + result.b[H1(i)] =3D table[H1(index % 16)]; + } + } + + memcpy(vd, &result, 16); + clear_tail(vd, oprsz, simd_maxsz(desc)); +} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 08ac5ec9906..3b501df7425 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -33,7 +33,6 @@ arm_ss.add(files( 'm_helper.c', 'mve_helper.c', 'op_helper.c', - 'vec_helper.c', )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( @@ -47,6 +46,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'pauth_helper.c', 'sme_helper.c', 'sve_helper.c', + 'vec_helper64.c', )) =20 arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c= ')) @@ -66,11 +66,13 @@ arm_common_system_ss.add(files( 'psci.c', 'tlb_helper.c', 'tlb-insns.c', + 'vec_helper.c', 'vfp_helper.c', )) arm_user_ss.add(files( 'hflags.c', 'neon_helper.c', 'tlb_helper.c', + 'vec_helper.c', 'vfp_helper.c', )) --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770754591; cv=none; d=zohomail.com; s=zohoarc; b=nqAFWy8PPh9/g5MRLfeUAyn8ZAHlkNVpkm9QnJmvQAzGEFb2X0vtDOV5jm7mxcV5AV8g2ZJ5/ZhDWoku09r2uZaeqmguAGsIJJRN+XWuJJigCxubiiEqqWYnaFcVKmJCDCSDcSFRZ6m8Vc7Pe6D17IdgHOwx4g9i+IzqMd713/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770754591; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=P+C4usfFJxntIkaYUwqttNHLWY0mMsZx1f8GtcALX8k=; b=NTQ15sOL+JCPTanxGowIF4amxIJQis+P0s4ODUGrfm2FOzE8AGeqThJKpv6DKEDxs79qPqlDucvZNWRkWfox0LSwyMqXM5ZxYb7EXg+q5Mpe+qXwZB6BOkGxeukYg5AZy8LiAwy9n9Flh62kaC+JQPPL5SdmKxWOjTTyy8DgRx0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770754591268588.9549563187022; Tue, 10 Feb 2026 12:16:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpu9e-00005N-DU; Tue, 10 Feb 2026 15:16:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpu9N-0007yd-8R for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:57 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpu9L-0008C8-9t for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:56 -0500 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-2a79998d35aso43705625ad.0 for ; Tue, 10 Feb 2026 12:15:54 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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For convenience, the @@ -56,8 +56,8 @@ typedef struct DisasContext { * pc_save contains -1 to indicate that relative updates are no * longer possible. */ - target_ulong pc_save; - target_ulong page_start; + vaddr pc_save; + vaddr page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770754585; cv=none; d=zohomail.com; s=zohoarc; b=cUvnHB4GzuQCOlNoWpAx01YB+zLSZRw2NuKdixsaueAvI/vP+XsD75ZcoHFWbToec+MACHxVRb6mINDp07sDaxEGp20jpwTtm4xdmyD9eWpAQA7H3XpO5UibhaRtArBMcVqzqc8K3Rh7vSvazVFtL+FCsq81ZSsHCEu/qNvS1TE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770754585; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pB7XVSfYiRDewWhWw/+06EtFsDlqvDtO9a2FWjRT+oU=; b=i/A8tl0EHmxn2QdTUPpsijUi1LDLQ0tRlwxzXNneF2ppPBfFm9hD4KVhg+ruidHCiagMdlbuKlPI4iFXXO52y0MrBFGCOJ01cR9VY7zrU0w9pFKY/MyRXsObQGJFDMwf9VjWGileER8A4STs8QQm6MD2IaVZcxVzdNDi9NRv1oY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770754585832701.1669552231302; Tue, 10 Feb 2026 12:16:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpu9f-0000Gb-UJ; Tue, 10 Feb 2026 15:16:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpu9P-00081A-Du for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:59 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpu9N-0008Cc-0a for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:15:58 -0500 Received: by mail-pl1-x642.google.com with SMTP id d9443c01a7336-2aaed195901so12617155ad.0 for ; Tue, 10 Feb 2026 12:15:55 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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Checked all call sites to make sure we were already passing signed values, so extending works as expected. Use vaddr for pc_curr and pc_save. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier --- target/arm/tcg/translate-a32.h | 2 +- target/arm/tcg/translate.h | 12 ++++++------ target/arm/tcg/translate.c | 18 +++++++++--------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h index 0b1fa57965c..a8df364171b 100644 --- a/target/arm/tcg/translate-a32.h +++ b/target/arm/tcg/translate-a32.h @@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele,= MemOp memop); TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); void gen_set_cpsr(TCGv_i32 var, uint32_t mask); void gen_set_condexec(DisasContext *s); -void gen_update_pc(DisasContext *s, target_long diff); +void gen_update_pc(DisasContext *s, int64_t diff); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 2c8358dd7fa..3e3094a463e 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -27,8 +27,8 @@ typedef struct DisasLabel { typedef struct DisasDelayException { struct DisasDelayException *next; TCGLabel *lab; - target_long pc_curr; - target_long pc_save; + vaddr pc_curr; + vaddr pc_save; int condexec_mask; int condexec_cond; uint32_t excp; @@ -359,14 +359,14 @@ static inline int curr_insn_len(DisasContext *s) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_a64_update_pc(DisasContext *s, target_long diff); +void gen_a64_update_pc(DisasContext *s, int64_t diff); extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_a64_update_pc(DisasContext *s, target_long diff) +static inline void gen_a64_update_pc(DisasContext *s, int64_t diff) { } #endif @@ -377,9 +377,9 @@ void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); void gen_exception_internal(int excp); -void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, +void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, uint32_t target_el); -void gen_exception_insn(DisasContext *s, target_long pc_diff, +void gen_exception_insn(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn); TCGLabel *delay_exception_el(DisasContext *s, int excp, uint32_t syn, uint32_t target_el); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 982c83ef42a..42b2785fb06 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -250,12 +250,12 @@ static inline int get_a32_user_mem_index(DisasContext= *s) } =20 /* The pc_curr difference for an architectural jump. */ -static target_long jmp_diff(DisasContext *s, target_long diff) +static int64_t jmp_diff(DisasContext *s, int64_t diff) { return diff + (s->thumb ? 4 : 8); } =20 -static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long di= ff) +static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int64_t diff) { assert(s->pc_save !=3D -1); if (tb_cflags(s->base.tb) & CF_PCREL) { @@ -735,7 +735,7 @@ void gen_set_condexec(DisasContext *s) } } =20 -void gen_update_pc(DisasContext *s, target_long diff) +void gen_update_pc(DisasContext *s, int64_t diff) { gen_pc_plus_diff(s, cpu_R[15], diff); s->pc_save =3D s->pc_curr + diff; @@ -1055,7 +1055,7 @@ static void gen_exception(int excp, uint32_t syndrome) tcg_constant_i32(syndrome)); } =20 -static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff, +static void gen_exception_insn_el_v(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_e= l) { if (s->aarch64) { @@ -1068,14 +1068,14 @@ static void gen_exception_insn_el_v(DisasContext *s= , target_long pc_diff, s->base.is_jmp =3D DISAS_NORETURN; } =20 -void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, +void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, uint32_t target_el) { gen_exception_insn_el_v(s, pc_diff, excp, syn, tcg_constant_i32(target_el)); } =20 -void gen_exception_insn(DisasContext *s, target_long pc_diff, +void gen_exception_insn(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn) { if (s->aarch64) { @@ -1310,7 +1310,7 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long= diff) +static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t dif= f) { if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) { /* @@ -1337,7 +1337,7 @@ static void gen_goto_tb(DisasContext *s, unsigned tb_= slot_idx, target_long diff) } =20 /* Jump, specifying which TB number to use if we gen_goto_tb() */ -static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno) +static void gen_jmp_tb(DisasContext *s, int64_t diff, int tbno) { if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ @@ -1380,7 +1380,7 @@ static void gen_jmp_tb(DisasContext *s, target_long d= iff, int tbno) } } =20 -static inline void gen_jmp(DisasContext *s, target_long diff) +static inline void gen_jmp(DisasContext *s, int64_t diff) { gen_jmp_tb(s, diff, 0); } --=20 2.47.3 From nobody Wed Feb 11 04:02:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770754627; cv=none; d=zohomail.com; s=zohoarc; b=HLTj1tgjP/T5/tmoqjihJGMj/OXtXYVooFSl6Rve7/53FBC/0GFrizPvPJeKeEAL3xkoIVgWNabvda7FsT+UC4BFD5WMxVraVjMiJduIPUVM4tRy2sVjh8+DrS+YoVZegGH8LwX7ATh9w2uZ7lc6SyiDmFSntC0JCYOpPbO6TKs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770754627; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iUFL9nxPB9bUeP42+0V7hNRdWE9EqDSh0B0IVvPLqNg=; b=NOpERjzSZJHqr0pmZ4sUfM9xwPi9l/H/LWc7GCGdRefhINqx4fM4K1d23G0yHbnqmNLAHFBrimLyoCGZfw6Xl2zR5osX7PyokaiGW+YjGGTtBHWPPuWolqzyDBoErMoBlTaYDJdz0yYlzVR5FvyJjoow+sde8evwpYjcOn2nU1M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770754627805602.6672068955819; Tue, 10 Feb 2026 12:17:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpu9g-0000M9-LG; Tue, 10 Feb 2026 15:16:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpu9R-00083f-KQ for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:16:01 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpu9O-0008D9-0H for qemu-devel@nongnu.org; Tue, 10 Feb 2026 15:16:01 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2aaecf9c325so1278845ad.1 for ; Tue, 10 Feb 2026 12:15:57 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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Since all arch have a single call site (in translate.c), this is as good documentation as having a single define. The notable exception is target/arm, which has two different translate files for 32/64 bits. Since it's the only one, we accept to have two call sites for this. As well, we update parameter type to use uint64_t instead of target_ulong, so it can be called from common code. Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-op-common.h | 8 ++++++++ include/tcg/tcg-op.h | 29 ----------------------------- target/alpha/cpu-param.h | 2 -- target/arm/cpu-param.h | 7 ------- target/avr/cpu-param.h | 2 -- target/hexagon/cpu-param.h | 2 -- target/hppa/cpu-param.h | 2 -- target/i386/cpu-param.h | 2 -- target/loongarch/cpu-param.h | 2 -- target/m68k/cpu-param.h | 2 -- target/microblaze/cpu-param.h | 2 -- target/mips/cpu-param.h | 2 -- target/or1k/cpu-param.h | 2 -- target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h | 7 ------- target/rx/cpu-param.h | 2 -- target/s390x/cpu-param.h | 2 -- target/sh4/cpu-param.h | 2 -- target/sparc/cpu-param.h | 2 -- target/tricore/cpu-param.h | 2 -- target/xtensa/cpu-param.h | 2 -- target/alpha/translate.c | 4 ++-- target/avr/translate.c | 2 +- target/hexagon/translate.c | 2 +- target/i386/tcg/translate.c | 2 +- target/loongarch/tcg/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/or1k/translate.c | 2 +- target/ppc/translate.c | 2 +- target/rx/translate.c | 2 +- target/sh4/translate.c | 4 ++-- target/sparc/translate.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/translate.c | 2 +- 35 files changed, 24 insertions(+), 93 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f752ef440b2..e02f209c093 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -30,6 +30,14 @@ TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t o= ff, const char *name); TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *na= me); =20 /* Generic ops. */ +static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, + uint64_t a2) +{ + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); + tcg_set_insn_start_param(op, 0, pc); + tcg_set_insn_start_param(op, 1, a1); + tcg_set_insn_start_param(op, 2, a2); +} =20 void gen_set_label(TCGLabel *l); void tcg_gen_br(TCGLabel *l); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index ee379994e76..7024be938e6 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -28,35 +28,6 @@ # error Mismatch with insn-start-words.h #endif =20 -#if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 -static inline void tcg_gen_insn_start(target_ulong pc) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, 0); - tcg_set_insn_start_param(op, 2, 0); -} -#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, a1); - tcg_set_insn_start_param(op, 2, 0); -} -#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, - target_ulong a2) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, a1); - tcg_set_insn_start_param(op, 2, a2); -} -#else -#error Unhandled TARGET_INSN_START_EXTRA_WORDS value -#endif - #if TARGET_LONG_BITS =3D=3D 32 typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index a799f42db31..c9da620ab3e 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -24,6 +24,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 8b46c7c5708..7de0099cbfa 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,11 +32,4 @@ # define TARGET_PAGE_BITS_LEGACY 10 #endif /* !CONFIG_USER_ONLY */ =20 -/* - * ARM-specific extra insn start words: - * 1: Conditional execution bits - * 2: Partial exception syndrome for data aborts - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f74bfc25804..ea7887919a7 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -25,6 +25,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e743..45ee7b46409 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -23,6 +23,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 9bf7ac76d0c..e0b2c7c9157 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -19,6 +19,4 @@ =20 #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index ebb844bcc83..909bc027923 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -22,6 +22,4 @@ #endif #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 58cc45a377e..071567712b3 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,4 @@ =20 #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 256a2b5f8b2..7afbf6d302d 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -17,6 +17,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index e0a37945136..6a0714bb3d7 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -27,6 +27,4 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 58f450827f7..a71e7383d24 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -20,6 +20,4 @@ #endif #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/or1k/cpu-param.h b/target/or1k/cpu-param.h index b4f57bbe692..3011bf5fcca 100644 --- a/target/or1k/cpu-param.h +++ b/target/or1k/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index e4ed9080ee9..ca7602d8983 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -37,6 +37,4 @@ # define TARGET_PAGE_BITS 12 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index cfdc67c258c..039e877891a 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -17,13 +17,6 @@ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ =20 -/* - * RISC-V-specific extra insn start words: - * 1: Original instruction opcode - * 2: more information about instruction - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* * The current MMU Modes are: * - U mode 0b000 diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 84934f3bcaf..ef1970a09e9 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -24,6 +24,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index abfae3bedfb..a5f798eeae7 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index f328715ee86..2b6e11dd0ac 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -16,6 +16,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 45eea9d6bac..6e8e2a51469 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -21,6 +21,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index eb33a67c419..790242ef3d2 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 7a0c22c9005..06d85218b84 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,6 +16,4 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 4442462891e..4d22d7d5a45 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2899,9 +2899,9 @@ static void alpha_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 if (ctx->pcrel) { - tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK); + tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK, 0, 0); } else { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } } =20 diff --git a/target/avr/translate.c b/target/avr/translate.c index 78ae83df219..649dd4b0112 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2689,7 +2689,7 @@ static void avr_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->npc); + tcg_gen_insn_start(ctx->npc, 0, 0); } =20 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index e88e19cc1af..1c9ab29bd12 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -978,7 +978,7 @@ static void hexagon_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7186517239c..14210d569f7 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3501,7 +3501,7 @@ static void i386_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) if (tb_cflags(dcbase->tb) & CF_PCREL) { pc_arg &=3D ~TARGET_PAGE_MASK; } - tcg_gen_insn_start(pc_arg, dc->cc_op); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); } =20 static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 30f375b33f0..b9ed13d19c6 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -159,7 +159,7 @@ static void loongarch_tr_insn_start(DisasContextBase *d= cbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 /* diff --git a/target/m68k/translate.c b/target/m68k/translate.c index a0309939012..abc1c79f3cd 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6041,7 +6041,7 @@ static void m68k_tr_tb_start(DisasContextBase *dcbase= , CPUState *cpu) static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); } =20 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0be3c98dc17..2af67beecec 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1630,7 +1630,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, C= PUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); =20 - tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK, 0); } =20 static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) diff --git a/target/or1k/translate.c b/target/or1k/translate.c index ce2dc466dc7..de81dc6ef8d 100644 --- a/target/or1k/translate.c +++ b/target/or1k/translate.c @@ -1552,7 +1552,7 @@ static void openrisc_tr_insn_start(DisasContextBase *= dcbase, CPUState *cs) DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) - | (dc->base.num_insns > 1 ? 2 : 0)); + | (dc->base.num_insns > 1 ? 2 : 0), 0); } =20 static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e9acfa239ec..a09a6df93fd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6575,7 +6575,7 @@ static void ppc_tr_tb_start(DisasContextBase *db, CPU= State *cs) =20 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } =20 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) diff --git a/target/rx/translate.c b/target/rx/translate.c index 26d41548294..a245b9db8fe 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2217,7 +2217,7 @@ static void rx_tr_insn_start(DisasContextBase *dcbase= , CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b3ae0a3814c..b1057727c55 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2181,7 +2181,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) * tb->icount * insn_start. */ for (i =3D 1; i < max_insns; ++i) { - tcg_gen_insn_start(pc + i * 2, ctx->envflags); + tcg_gen_insn_start(pc + i * 2, ctx->envflags, 0); ctx->base.insn_start =3D tcg_last_op(); } } @@ -2241,7 +2241,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); + tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags, 0); } =20 static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 57b50ff8b9a..7e8558dbbd8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5735,7 +5735,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) g_assert_not_reached(); } } - tcg_gen_insn_start(dc->pc, npc); + tcg_gen_insn_start(dc->pc, npc, 0); } =20 static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 18d8726af6d..0eaf7a82f87 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8410,7 +8410,7 @@ static void tricore_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index bb8d2ed86cf..5e3707d3fdf 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcba= se, CPUState *cpu) =20 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } =20 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) --=20 2.47.3