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Tue, 10 Feb 2026 12:13:59 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Alexandre Iooss , Pierrick Bouvier , alistair.francis@wdc.com, Mahmoud Mandour , manos.pitsidianakis@linaro.org, philmd@linaro.org, anjo@rev.ng, brian.cain@oss.qualcomm.com Subject: [PATCH 4/4] contrib/plugins/uftrace: add riscv64 support Date: Tue, 10 Feb 2026 12:13:44 -0800 Message-ID: <20260210201344.1403613-5-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260210201344.1403613-1-pierrick.bouvier@linaro.org> References: <20260210201344.1403613-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770754478697154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Pierrick Bouvier --- docs/about/emulation.rst | 10 +++-- contrib/plugins/uftrace.c | 87 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+), 3 deletions(-) diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index f547e118eef..76c6ea92ca9 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -836,8 +836,8 @@ Uftrace This plugin generates a binary trace compatible with `uftrace `_. =20 -Plugin supports aarch64 and x64, and works in user and system mode, allowi= ng to -trace a system boot, which is not something possible usually. +Plugin supports aarch64, x64 and riscv64, and works in user and system mod= e, +allowing to trace a system boot, which is not something possible usually. =20 In user mode, the memory mapping is directly copied from ``/proc/self/maps= `` at the end of execution. Uftrace should be able to retrieve symbols by itself, @@ -872,7 +872,7 @@ Performance wise, overhead compared to normal tcg execu= tion is around x5-x15. - Description * - trace-privilege-level=3D[on|off] - Generate separate traces for each privilege level (Exception Level + - Security State on aarch64, Rings on x64). + Security State on aarch64, Privilege levels on riscv64 and Rings on = x64). =20 .. list-table:: uftrace_symbols.py arguments :widths: 20 80 @@ -976,6 +976,10 @@ You can follow the exact same instructions for a x64 s= ystem, combining edk2, Linux, and Ubuntu, simply by switching to `x86_64 `_ bra= nch. =20 +You can follow the exact same instructions for a riscv64 system, combining +opensbi, Linux, and Ubuntu, simply by switching to +`riscv64 `_ b= ranch. + To build and run the system:: =20 # Install dependencies diff --git a/contrib/plugins/uftrace.c b/contrib/plugins/uftrace.c index 21ac1402047..e3c65a1c930 100644 --- a/contrib/plugins/uftrace.c +++ b/contrib/plugins/uftrace.c @@ -99,6 +99,19 @@ typedef struct { struct qemu_plugin_register *reg_cr0; } X64Cpu; =20 +typedef struct { + struct qemu_plugin_register *reg_fp; + struct qemu_plugin_register *reg_priv; +} Riscv64Cpu; + +typedef enum { + RISCV64_USER, + RISCV64_SUPERVISOR, + RISCV64_RESERVED, + RISCV64_MACHINE, + RISCV64_PRIVILEGE_LEVEL_MAX, +} Riscv64PrivilegeLevel; + typedef struct { uint64_t timestamp; uint64_t data; @@ -681,6 +694,78 @@ static CpuOps x64_ops =3D { .does_insn_modify_frame_pointer =3D x64_does_insn_modify_frame_pointer, }; =20 +static uint8_t riscv64_num_privilege_levels(void) +{ + return RISCV64_PRIVILEGE_LEVEL_MAX; +} + +static const char *riscv64_get_privilege_level_name(uint8_t pl) +{ + switch (pl) { + case RISCV64_USER: return "User"; + case RISCV64_SUPERVISOR: return "Supervisor"; + case RISCV64_RESERVED: return "Unknown"; + case RISCV64_MACHINE: return "Machine"; + default: + g_assert_not_reached(); + } +} + +static uint8_t riscv64_get_privilege_level(Cpu *cpu_) +{ + Riscv64Cpu *cpu =3D cpu_->arch; + return cpu_read_register64(cpu_, cpu->reg_priv); +} + +static uint64_t riscv64_get_frame_pointer(Cpu *cpu_) +{ + Riscv64Cpu *cpu =3D cpu_->arch; + return cpu_read_register64(cpu_, cpu->reg_fp); +} + +static uint64_t riscv64_get_next_frame_pointer(Cpu *cpu_, uint64_t fp) +{ + return cpu_read_memory64(cpu_, fp - 16); +} + +static uint64_t riscv64_get_next_return_address(Cpu *cpu_, uint64_t fp) +{ + return cpu_read_memory64(cpu_, fp - 8); +} + +static void riscv64_init(Cpu *cpu_) +{ + Riscv64Cpu *cpu =3D g_new0(Riscv64Cpu, 1); + cpu_->arch =3D cpu; + cpu->reg_fp =3D plugin_find_register("fp"); + g_assert(cpu->reg_fp); + cpu->reg_priv =3D plugin_find_register("priv"); + g_assert(cpu->reg_priv); +} + +static void riscv64_end(Cpu *cpu) +{ + g_free(cpu->arch); +} + +static bool riscv64_does_insn_modify_frame_pointer(const char *disas) +{ + /* fp is s0 in disassembly */ + return strstr(disas, "s0"); +} + +static CpuOps riscv64_ops =3D { + .init =3D riscv64_init, + .end =3D riscv64_end, + .get_frame_pointer =3D riscv64_get_frame_pointer, + .get_next_frame_pointer =3D riscv64_get_next_frame_pointer, + .get_next_return_address =3D riscv64_get_next_return_address, + .get_privilege_level =3D riscv64_get_privilege_level, + .num_privilege_levels =3D riscv64_num_privilege_levels, + .get_privilege_level_name =3D riscv64_get_privilege_level_name, + .does_insn_modify_frame_pointer =3D riscv64_does_insn_modify_frame_poi= nter, +}; + static void track_privilege_change(unsigned int cpu_index, void *udata) { Cpu *cpu =3D qemu_plugin_scoreboard_find(score, cpu_index); @@ -890,6 +975,8 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_= id_t id, arch_ops =3D aarch64_ops; } else if (!strcmp(info->target_name, "x86_64")) { arch_ops =3D x64_ops; + } else if (!strcmp(info->target_name, "riscv64")) { + arch_ops =3D riscv64_ops; } else { fprintf(stderr, "plugin uftrace: %s target is not supported\n", info->target_name); --=20 2.47.3