From nobody Tue Feb 10 21:40:03 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731676; cv=none; d=zohomail.com; s=zohoarc; b=PNbQ1hGeccPxQBbi2oqQy9W5/O0kahYQk3fs8xg5yT1pyZQTU3JTl0mF6HNlhLi+BhEvCMLWI5tyIAjgnSLytqmL7PNIMV0NpwB3wJoFSIX6eTFBUX6ox3msnYKdzhY9jNyLbj1HrMGvyF5reGAn0bOWbRLdo6WVMJOim5H3GuU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731676; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=5xPq2fNqcw/oH0dNiPR3/K9/+sAUVQTjTaQpF6aGozQ=; b=RqQlui+fCQ4BkwGhIOvfGoM21RHsjpecoQ5hKqUztMPkymE8qvxOnfxpggyuP31WnP62Ak4NhMclvoKPJjHiUUaT09W74RopxKr6J3pwLwCe1mM8+wa1CCXRvzFrACyhJGIbrYKGf6KfV1mWi4zEee78zfsfODeEInqWMWlfX1Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731676924158.96920336081484; Tue, 10 Feb 2026 05:54:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAG-0002BG-UQ; Tue, 10 Feb 2026 08:52:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAD-00026d-S9 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:25 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAB-0006LZ-5f for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:25 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-48336a6e932so16499115e9.3 for ; Tue, 10 Feb 2026 05:52:19 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731539; x=1771336339; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5xPq2fNqcw/oH0dNiPR3/K9/+sAUVQTjTaQpF6aGozQ=; b=m7nLKRFItcahzz3AkSBg6nlbmGeI+NHTWkJ0gpJbCydA8pZOl/CEMfqAG6k9WJgySO fYxQcQpCpqcrMvfY0uPkfx5o8YrXZQMI8xJ/eZuGaaXFh92xnP94nD44KY1Y92DWu6NW XnjMp2i0nzRWQW+CgnMATGLJ0Wp8jGtIu9HcY1gYiwqVdZyb3b9GM8BD2Lxv5FqS3wdg bywwH06A09ybx72EUfQIuue4hYkzdDC/9R1tuOYHY0SNyoEHF9TvQtQCfydwFaNMSYwt 8zOT4ds6Nm+VWlxd+IVcz0/6Ff+3pee1BcJW0jTnh1Oiq6bDgtoDCT3A3vtLhUwPTkpn 348Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731539; x=1771336339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=5xPq2fNqcw/oH0dNiPR3/K9/+sAUVQTjTaQpF6aGozQ=; b=TNYp5z4HIiMccbjiCV2luSSbwQY4AqtAwXl9+oc8bktZcGSWpu8QMxTnHnySx4tD1A i3AJSX0lBzfk+6Ks2MMhmJNSXp/SfSwE2uNqT5I8U6I512LO0giK6akJM9i4wgjAnNp2 B0PVFdii0yHdyWsmcpNVx9NG6NFYRr4OukCmQktg1tdNtK58tvbhdmuvXEYk0sBQcGQA h/WjAidMS6giikO4d1S2klLcW7tXE53LQCt9IZ2fYnioahKzT7m2ExplAYmmq99TtXKT L0Q5pdZfNidr2rrSxxsj+n+L2Bkkj05JG7L1tQkJh0FBGDevcEqfNZQw3VDiWbFIRmQu l7UA== X-Gm-Message-State: AOJu0YxmmTKdSUipPRB9bu+NMi0Q2Uw7o2T05DJWTfN4ninptEQLKJAg pybMhl0bA7oRcSI4hQ1ZgBhrKFFoU4m5DliT0gypgFB82FP25u/VRLGKgYfnp7PL5+DRujzuwd6 toNJd X-Gm-Gg: AZuq6aKxAX/zdU5qC0VhR4jYG35fAWK0ph+oAFko9DF+Wt1LPfjWXoUDFzPjJcKmczx eRW/jQQq5mGn6zjoRVuqWltj04kNCZIGBdISNYOUWKhZnTp/De2sWWmDHE+njusPvBsVd6vyrZV Eofh8u1ncGKTfXhn0iD4xXOcsCipKb8X90778suUDwzKb75/bhNM5/TfKzLNFPEkel0F5/Gnegn bk3zytWXwFfpFqWcVtR3EgZ/+tEMgxPLdCOsM/Gyp7kOVVjQyKNqnXrpqGa/Dpbt0hSW0xvcm3K gR4FsX4maVDwAEcoVmbTvJReWb7lixJuQPJwEb9Bqw8XcATv+coq1CkqwLBvCziWx2L2ww0J9ze 8E23nDyALpy+RUTuwIq9/U2jcNWVzjEahAUD2bdlfOXcX4WpdL4X8oiMIsHxJSlPSbmUpeS6ZPN hxJ8imwQkKtXaKWLfvYfyJDej49sh7MgIRT/XlFoUWToghfm0cNp1Q18Muep2aoWnvMcVliwoyS q4+oUrvHC5UVfwKGbqiTSXjoLdGGE89QXhc3eNNjQ== X-Received: by 2002:a05:600c:34c5:b0:480:1b65:b744 with SMTP id 5b1f17b1804b1-4832021e972mr211015325e9.28.1770731538591; Tue, 10 Feb 2026 05:52:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/26] hw, target, accel: whpx: change apic_in_platform to kernel_irqchip Date: Tue, 10 Feb 2026 13:51:53 +0000 Message-ID: <20260210135206.229528-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731677460154100 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Change terminology to match the KVM one, as APIC is x86-specific. And move out whpx_irqchip_in_kernel() to make it usable from common code even when not compiling with WHPX support. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + accel/stubs/whpx-stub.c | 1 + accel/whpx/whpx-accel-ops.c | 2 +- accel/whpx/whpx-common.c | 10 +- hw/arm/virt.c | 9 ++ hw/i386/x86-cpu.c | 4 +- hw/intc/arm_gicv3_common.c | 3 + hw/intc/arm_gicv3_whpx.c | 237 +++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + include/hw/intc/arm_gicv3_common.h | 3 + include/system/whpx-internal.h | 1 - include/system/whpx.h | 5 +- target/i386/cpu-apic.c | 2 +- target/i386/whpx/whpx-all.c | 14 +- 14 files changed, 270 insertions(+), 23 deletions(-) create mode 100644 hw/intc/arm_gicv3_whpx.c diff --git a/MAINTAINERS b/MAINTAINERS index 54326b1a5a..c6af6e10bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,7 @@ M: Mohamed Mediouni S: Supported F: accel/whpx/ F: target/i386/whpx/ +F: hw/intc/arm_gicv3_whpx.c F: accel/stubs/whpx-stub.c F: include/system/whpx.h F: include/system/whpx-accel-ops.h diff --git a/accel/stubs/whpx-stub.c b/accel/stubs/whpx-stub.c index c564c89fd0..4529dc4f78 100644 --- a/accel/stubs/whpx-stub.c +++ b/accel/stubs/whpx-stub.c @@ -10,3 +10,4 @@ #include "system/whpx.h" =20 bool whpx_allowed; +bool whpx_irqchip_in_kernel; diff --git a/accel/whpx/whpx-accel-ops.c b/accel/whpx/whpx-accel-ops.c index c84a25c273..50fadea0fd 100644 --- a/accel/whpx/whpx-accel-ops.c +++ b/accel/whpx/whpx-accel-ops.c @@ -78,7 +78,7 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) =20 static bool whpx_vcpu_thread_is_idle(CPUState *cpu) { - return !whpx_apic_in_platform(); + return !whpx_irqchip_in_kernel(); } =20 static void whpx_accel_ops_class_init(ObjectClass *oc, const void *data) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index c0610815d9..05f9e520b7 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -35,6 +35,7 @@ #include =20 bool whpx_allowed; +bool whpx_irqchip_in_kernel; static bool whp_dispatch_initialized; static HMODULE hWinHvPlatform; #ifdef HOST_X86_64 @@ -488,15 +489,6 @@ static const TypeInfo whpx_cpu_accel_type =3D { .abstract =3D true, }; =20 -/* - * Partition support - */ - -bool whpx_apic_in_platform(void) -{ - return whpx_global.apic_in_platform; -} - static void whpx_accel_class_init(ObjectClass *oc, const void *data) { AccelClass *ac =3D ACCEL_CLASS(oc); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index aa5e992712..b7eb0cec5e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -49,6 +49,7 @@ #include "system/tcg.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/whpx.h" #include "system/qtest.h" #include "system/system.h" #include "hw/core/loader.h" @@ -2114,6 +2115,8 @@ static void finalize_gic_version(VirtMachineState *vm= s) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; + } else if (whpx_enabled()) { + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { @@ -2154,6 +2157,8 @@ static void finalize_msi_controller(VirtMachineState = *vms) if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_AUTO) { if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } else if (whpx_enabled()) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } else { vms->msi_controller =3D VIRT_MSI_CTRL_ITS; } @@ -2169,6 +2174,10 @@ static void finalize_msi_controller(VirtMachineState= *vms) error_report("GICv2 + ITS is an invalid configuration."); exit(1); } + if (whpx_enabled()) { + error_report("ITS not supported on WHPX."); + exit(1); + } } =20 assert(vms->msi_controller !=3D VIRT_MSI_CTRL_AUTO); diff --git a/hw/i386/x86-cpu.c b/hw/i386/x86-cpu.c index 276f2b0cdf..95e08e3c2a 100644 --- a/hw/i386/x86-cpu.c +++ b/hw/i386/x86-cpu.c @@ -45,7 +45,7 @@ static void pic_irq_request(void *opaque, int irq, int le= vel) =20 trace_x86_pic_interrupt(irq, level); if (cpu_is_apic_enabled(cpu->apic_state) && !kvm_irqchip_in_kernel() && - !whpx_apic_in_platform()) { + !whpx_irqchip_in_kernel()) { CPU_FOREACH(cs) { cpu =3D X86_CPU(cs); if (apic_accept_pic_intr(cpu->apic_state)) { @@ -71,7 +71,7 @@ int cpu_get_pic_interrupt(CPUX86State *env) X86CPU *cpu =3D env_archcpu(env); int intno; =20 - if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { + if (!kvm_irqchip_in_kernel() && !whpx_irqchip_in_kernel()) { intno =3D apic_get_interrupt(cpu->apic_state); if (intno >=3D 0) { return intno; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 0a2e5a3e2f..9054143ea7 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,6 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" +#include "system/whpx.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -663,6 +664,8 @@ const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { return "kvm-arm-gicv3"; + } else if (whpx_enabled()) { + return TYPE_WHPX_GICV3; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/hw/intc/arm_gicv3_whpx.c b/hw/intc/arm_gicv3_whpx.c new file mode 100644 index 0000000000..849a005242 --- /dev/null +++ b/hw/intc/arm_gicv3_whpx.c @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller using HVF platform support + * + * Copyright (c) 2025 Mohamed Mediouni + * Based on vGICv3 KVM code by Pavel Fedin + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "system/runstate.h" +#include "system/whpx.h" +#include "system/whpx-internal.h" +#include "gicv3_internal.h" +#include "vgic_common.h" +#include "migration/blocker.h" +#include "qom/object.h" +#include "target/arm/cpregs.h" + +#include "hw/arm/bsa.h" +#include +#include +#include + +struct WHPXARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +OBJECT_DECLARE_TYPE(GICv3State, WHPXARMGICv3Class, WHPX_GICV3) + +/* TODO: Implement GIC state save-restore */ +static void whpx_gicv3_check(GICv3State *s) +{ +} + +static void whpx_gicv3_put(GICv3State *s) +{ + whpx_gicv3_check(s); +} + +static void whpx_gicv3_get(GICv3State *s) +{ +} + +static void whpx_gicv3_set_irq(void *opaque, int irq, int level) +{ + struct whpx_state *whpx =3D &whpx_global; + GICv3State *s =3D opaque; + WHV_INTERRUPT_CONTROL interrupt_control =3D { + .InterruptControl.InterruptType =3D WHvArm64InterruptTypeFixed, + .RequestedVector =3D GIC_INTERNAL + irq, + .InterruptControl.Asserted =3D level + }; + + if (irq > s->num_irq) { + return; + } + + + whp_dispatch.WHvRequestInterrupt(whpx->partition, &interrupt_control, + sizeof(interrupt_control)); +} + +static void whpx_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3CPUState *c; + + c =3D env->gicv3state; + + c->icc_pmr_el1 =3D 0; + /* + * Architecturally the reset value of the ICC_BPR registers + * is UNKNOWN. We set them all to 0 here; when the kernel + * uses these values to program the ICH_VMCR_EL2 fields that + * determine the guest-visible ICC_BPR register values, the + * hardware's "writing a value less than the minimum sets + * the field to the minimum value" behaviour will result in + * them effectively resetting to the correct minimum value + * for the host GIC. + */ + c->icc_bpr[GICV3_G0] =3D 0; + c->icc_bpr[GICV3_G1] =3D 0; + c->icc_bpr[GICV3_G1NS] =3D 0; + + c->icc_sre_el1 =3D 0x7; + memset(c->icc_apr, 0, sizeof(c->icc_apr)); + memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); +} + +static void whpx_gicv3_reset_hold(Object *obj, ResetType type) +{ + GICv3State *s =3D ARM_GICV3_COMMON(obj); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_GET_CLASS(s); + + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj, type); + } + + whpx_gicv3_put(s); +} + + +/* + * CPU interface registers of GIC needs to be reset on CPU reset. + * For the calling arm_gicv3_icc_reset() on CPU reset, we register + * below ARMCPRegInfo. As we reset the whole cpu interface under single + * register reset, we define only one register of CPU interface instead + * of defining all the registers. + */ +static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { + { .name =3D "ICC_CTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 4, + /* + * If ARM_CP_NOP is used, resetfn is not called, + * So ARM_CP_NO_RAW is appropriate type. + */ + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, + .readfn =3D arm_cp_read_zero, + .writefn =3D arm_cp_write_ignore, + /* + * We hang the whole cpu interface reset routine off here + * rather than parcelling it out into one little function + * per register + */ + .resetfn =3D whpx_gicv3_icc_reset, + }, +}; + +static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_gicv3_realize(DeviceState *dev, Error **errp) +{ + ERRP_GUARD(); + GICv3State *s =3D WHPX_GICV3(dev); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_GET_CLASS(s); + int i; + + kgc->parent_realize(dev, errp); + if (*errp) { + return; + } + + if (s->revision !=3D 3) { + error_setg(errp, "unsupported GIC revision %d for platform GIC", + s->revision); + return; + } + + if (s->security_extn) { + error_setg(errp, "the platform vGICv3 does not implement the " + "security extensions"); + return; + } + + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the platform GIC"); + return; + } + + if (s->nb_redist_regions > 1) { + error_setg(errp, "Multiple VGICv3 redistributor regions are not " + "supported by WHPX"); + error_append_hint(errp, "A maximum of %d VCPUs can be used", + s->redist_region_count[0]); + return; + } + + gicv3_init_irqs_and_mmio(s, whpx_gicv3_set_irq, NULL); + + for (i =3D 0; i < s->num_cpu; i++) { + CPUState *cpu_state =3D qemu_get_cpu(i); + ARMCPU *cpu =3D ARM_CPU(cpu_state); + WHV_REGISTER_VALUE val =3D {.Reg64 =3D 0x080A0000 + (GICV3_REDIST_= SIZE * i)}; + whpx_set_reg(cpu_state, WHvArm64RegisterGicrBaseGpa, val); + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + } + + if (s->maint_irq) { + error_setg(errp, "Nested virtualisation not currently supported by= WHPX."); + return; + } + + error_setg(&s->migration_blocker, + "Live migration disabled because GIC state save/restore not suppor= ted on WHPX"); + if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { + error_report_err(*errp); + } +} + +static void whpx_gicv3_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_CLASS(klass); + + agcc->pre_save =3D whpx_gicv3_get; + agcc->post_load =3D whpx_gicv3_put; + + device_class_set_parent_realize(dc, whpx_gicv3_realize, + &kgc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, whpx_gicv3_reset_hold, NU= LL, + &kgc->parent_phases); +} + +static const TypeInfo whpx_arm_gicv3_info =3D { + .name =3D TYPE_WHPX_GICV3, + .parent =3D TYPE_ARM_GICV3_COMMON, + .instance_size =3D sizeof(GICv3State), + .class_init =3D whpx_gicv3_class_init, + .class_size =3D sizeof(WHPXARMGICv3Class), +}; + +static void whpx_gicv3_register_types(void) +{ + type_register_static(&whpx_arm_gicv3_info); +} + +type_init(whpx_gicv3_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index faae20b93d..96742df090 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic= .c', 'apic_common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_= common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpui= f.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) +specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('a= rm_gicv3_whpx.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 3d24ad22d2..c55cf18120 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -313,6 +313,9 @@ typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass, ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON) =20 +/* Types for GICv3 kernel-irqchip */ +#define TYPE_WHPX_GICV3 "whpx-arm-gicv3" + struct ARMGICv3CommonClass { /*< private >*/ SysBusDeviceClass parent_class; diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 609d0e1c08..8ded54a39b 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -45,7 +45,6 @@ struct whpx_state { =20 bool kernel_irqchip_allowed; bool kernel_irqchip_required; - bool apic_in_platform; }; =20 extern struct whpx_state whpx_global; diff --git a/include/system/whpx.h b/include/system/whpx.h index 00f6a3e523..4217a27e91 100644 --- a/include/system/whpx.h +++ b/include/system/whpx.h @@ -25,11 +25,12 @@ =20 #ifdef CONFIG_WHPX_IS_POSSIBLE extern bool whpx_allowed; +extern bool whpx_irqchip_in_kernel; #define whpx_enabled() (whpx_allowed) -bool whpx_apic_in_platform(void); +#define whpx_irqchip_in_kernel() (whpx_irqchip_in_kernel) #else /* !CONFIG_WHPX_IS_POSSIBLE */ #define whpx_enabled() 0 -#define whpx_apic_in_platform() (0) +#define whpx_irqchip_in_kernel() (0) #endif /* !CONFIG_WHPX_IS_POSSIBLE */ =20 #endif /* QEMU_WHPX_H */ diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c index f7ad7b5139..eaa10ad2a3 100644 --- a/target/i386/cpu-apic.c +++ b/target/i386/cpu-apic.c @@ -33,7 +33,7 @@ APICCommonClass *apic_get_class(Error **errp) apic_type =3D "kvm-apic"; } else if (xen_enabled()) { apic_type =3D "xen-apic"; - } else if (whpx_apic_in_platform()) { + } else if (whpx_irqchip_in_kernel()) { apic_type =3D "whpx-apic"; } =20 diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 052cda42bf..8210250dc3 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -607,7 +607,7 @@ void whpx_get_registers(CPUState *cpu) hr); } =20 - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { /* * Fetch the TPR value from the emulated APIC. It may get overwrit= ten * below with the value from CR8 returned by @@ -749,7 +749,7 @@ void whpx_get_registers(CPUState *cpu) =20 assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names)); =20 - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { whpx_apic_get(x86_cpu->apic_state); } =20 @@ -1379,7 +1379,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } =20 /* Get pending hard interruption or replay one that was overwritten */ - if (!whpx_apic_in_platform()) { + if (!whpx_irqchip_in_kernel()) { if (!vcpu->interruption_pending && vcpu->interruptable && (env->eflags & IF_MASK)) { assert(!new_int.InterruptionPending); @@ -1553,7 +1553,7 @@ int whpx_vcpu_run(CPUState *cpu) =20 if (exclusive_step_mode =3D=3D WHPX_STEP_NONE) { whpx_vcpu_process_async_events(cpu); - if (cpu->halted && !whpx_apic_in_platform()) { + if (cpu->halted && !whpx_irqchip_in_kernel()) { cpu->exception_index =3D EXCP_HLT; qatomic_set(&cpu->exit_request, false); return 0; @@ -1642,7 +1642,7 @@ int whpx_vcpu_run(CPUState *cpu) break; =20 case WHvRunVpExitReasonX64ApicEoi: - assert(whpx_apic_in_platform()); + assert(whpx_irqchip_in_kernel()); ioapic_eoi_broadcast(vcpu->exit_ctx.ApicEoi.InterruptVector); break; =20 @@ -2187,7 +2187,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } } else { - whpx->apic_in_platform =3D true; + whpx_irqchip_in_kernel =3D true; } } =20 @@ -2196,7 +2196,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) prop.ExtendedVmExits.X64MsrExit =3D 1; prop.ExtendedVmExits.X64CpuidExit =3D 1; prop.ExtendedVmExits.ExceptionExit =3D 1; - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { prop.ExtendedVmExits.X64ApicInitSipiExitTrap =3D 1; } =20 --=20 2.43.0