From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731656; cv=none; d=zohomail.com; s=zohoarc; b=NBDmno2XlIDQ+Akxl9vEuZEfpQgMnRG/8DOPnfPW+2BXn3uL6vE7h+svMuoYLrzT+Hn9aKNY1RgNwW8PT3zEh66dosIWUX+V5xlNTxi+Ob+nvsB4zlytFd+vxPt7QdKTeTP5hP6fW0v/R53AOm/NQranKNs0jpbVUdw7F5YBINI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731656; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=uGmUMAxaPIgZzI2J5wAhB0++mAJXpnT/oS5kHIdBbGg=; b=M7od3HN2wNbuPV0NBo1ZTIaXO4OPwJ2E1014QSW+eXLsBHaS5Dr5Pky0EjhkYO+CFg2TB8gjGpTiH2wAuZK2YufkNaAJISpFKeXMKk7b/8pID/2NMilcdnBQR38aD3iuaoVTbn3kdykW6g4p7/zZJPmWF4dxENdmKkkI2AyWKGI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731655990861.2034105554657; Tue, 10 Feb 2026 05:54:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoA2-0001wK-0M; Tue, 10 Feb 2026 08:52:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA1-0001vX-9R for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:13 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpo9y-0006J5-5q for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:13 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4801eb2c0a5so53541425e9.3 for ; Tue, 10 Feb 2026 05:52:09 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731529; x=1771336329; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=uGmUMAxaPIgZzI2J5wAhB0++mAJXpnT/oS5kHIdBbGg=; b=wgWFHVuIqYagCgeSRVJqvGq4rNrt9QDvOBgyFDAQX1s5fHWCbh0LTbA5b6/y6hcrWE Jx475wcI9q9kfyGwc+SGRhWnbNk0FbWjp2PXDvbbo8kafRGW4bx+0N24q/eIDCaZT5Ou TP5hT4rl3laPOwizIcNIjetSEWmerHLSeqDmjmXiyXhQSTlbCV/av3NAEz4SaO3RlrRj FoyDmxP+/89tsmd37GiBLkslaa9Tkg+8lUUzQIhjJJzlHXAbzI/cD4kE18ry+iIySLC/ 1bLA+znSCOTHRX7ACkqRCGyKATO2rb1QxAdY2VxUwogQ2tqlqTQZdlJFUTh3hNSPo8B+ LoLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731529; x=1771336329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=uGmUMAxaPIgZzI2J5wAhB0++mAJXpnT/oS5kHIdBbGg=; b=pp0RT0YYuKmd8E8K0XgpPs01oSsZISj8CtLQoYybewDfST+zVSUgrSli0Gm3aGNZY0 bGQ9LweWd92u6cvz5LYcGJ0Ym0qYvbYyD6i++Ikps+gNTjaZ4n4o3CqRmRLrzUVm2Jyo J236g9vXDySx8dGGYUszpX/0zYP01wbTMvLXdVmIdjzcKncpHRV5NNJ722wEE8ODO29v B2D7Ym9EgW990/zYvsl6lrQA+lmlh6CRMIyaPjZxXOVdxdXQePvh6EQsjpKNMpuDtA4L aB4RE1yd3pAktqNpEb93mqiJvHJ3RkDc4ovf6kLEaAxy8fWB0w4Hnw09LiSzyEYjrVXw KPRg== X-Gm-Message-State: AOJu0YwdsEXfDZzVOMEHAkYSDsttYDuBKNJ9ONKXyP3DJ7qbucazJKMs KB9OHQqMy1lX7vvysFh6CJkbW2LIeEijLjI+79BPShA77dhxzy5Bn40UXY2g+f86Iq3z3MCDPJh mT9AL X-Gm-Gg: AZuq6aKu+SkbNOEk09EEsSpDhNa2vVlUM0r4YHGXf9HoluV4z9hpTEDuLjAnVHkfDH4 0WPGpVG/iXiYPWo3CcDQ9pK5fDgzzERU7z9BjfqOJBYqcpsen1kRP5qHsWS1p8JTbvj1eWb6sJa a5JeccV1MJwZ80ChTOq3E8oGMJWODW1wHiZeyU9zxPG1Au2RGCGLvb1McOYuhGmBBbH4CNhDMrX OuKVQGGls1WfG7acvXZLKj131+SVxO9VVVHzQYbPkdOqrDt90PuvUBi985STSMSCOQI/HJzXfDR 5WfM6H6BnkZwUeXbytL0lu9tnchx8xiIJFcow1gAqSENmJOWpyoRjvc84/hII9iGIK82Ix0if5f 9uPlzS37un2uEPj26mcxbmzCBjtaNq4DyQviXmSkuXAVbKwxOdyI7468UXtTz0zWWuyNrI0ot94 ToD1MNLFQ8w7M6oF5iMiTJWo9tZ12k3Dqfsz51QNrlm9Vz8V9IfWDaiebO8Kj5wAyCJ5Qv6zb3h CmgAo+ByX25culagG1m/UvhSv5sjfU= X-Received: by 2002:a05:600c:45cb:b0:482:ef72:5778 with SMTP id 5b1f17b1804b1-483507d15bbmr35436695e9.8.1770731528694; Tue, 10 Feb 2026 05:52:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/26] target/arm/kvm: add constants for new PSCI versions Date: Tue, 10 Feb 2026 13:51:41 +0000 Message-ID: <20260210135206.229528-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731659006154100 From: Sebastian Ott Add constants for PSCI version 1_2 and 1_3. Signed-off-by: Sebastian Ott Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm-consts.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index 54ae5da7ce..9fba3e886d 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -97,6 +97,8 @@ MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_F= N_PSCI_FEATURES); #define QEMU_PSCI_VERSION_0_2 0x00002 #define QEMU_PSCI_VERSION_1_0 0x10000 #define QEMU_PSCI_VERSION_1_1 0x10001 +#define QEMU_PSCI_VERSION_1_2 0x10002 +#define QEMU_PSCI_VERSION_1_3 0x10003 =20 MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_= MP); /* We don't bother to check every possible version value */ --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731612; cv=none; d=zohomail.com; s=zohoarc; b=WKC2Bqh9u80l3hTZHupnWE/M4HogVPyvSSGV84jPi9NcgJg+yimkECtmshGMSmSwHAVFDjKIe85CfBD+cjerFFgd6aEu9e5jpLCdvkBoIVjc+3wVDDVykRZ4ZsssBGTGJGjZaofrsLLOARmJquuVoPkuvsHEJubbMSGK4wctuNI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731612; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8ZYllfqCxHjZfO9L3URwSmEVOZS07oqfLdpX+lY9NZ8=; b=WnINcTMP+YnDoAS5F5VHoK+URg19+FNnh3gVq8Patv+UtuXP07HWEWds4XUk8gwwONXkm3knXiKg1jLCHYFzTiCSu48DQiuJjv/a5oacDgttf4vixVek7RYS2wDxxqt2kuOeABFlAWzNQyn5wOttcvTLbr0lGrlDbR2ygR/ab2Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731612151701.7623420948923; Tue, 10 Feb 2026 05:53:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoA3-0001wd-Kn; Tue, 10 Feb 2026 08:52:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA1-0001vq-GB for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:13 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpo9z-0006JF-DM for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:13 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4834826e5a0so9780885e9.2 for ; Tue, 10 Feb 2026 05:52:11 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731530; x=1771336330; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8ZYllfqCxHjZfO9L3URwSmEVOZS07oqfLdpX+lY9NZ8=; b=lCNu7NFdU35WyW2/sL/no8BKVjsEA3t+vr+VuGx7FZhyWHZNU4XxPjpZMMmC0Yqky9 TMvsJ5MXhslAP0+nzwUSRYlbyLahCyYNJgfrLIXpMuC1xbIuXQMXRblFMuNPvTk5rToQ f26VQKKjC6DtNh6G7WQ2LY7IcpRnTCs2SLkpoRCn6lfwC1KM9CKNuj30/PVRne/mkL3Z ktZYl1XFvS8tyV/WxxI23jX7q0BuwY5nAHSc3/zj/CrAOOfxIbeVmdImLxIRhvW6WrVK jfrNX8TT3IQcZXdkbihT4piah0LvyM3HUg0iFjsKdH11MBhvQs3r4R4tOUViXh3Xxn+H kmOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731530; x=1771336330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=8ZYllfqCxHjZfO9L3URwSmEVOZS07oqfLdpX+lY9NZ8=; b=vNqlstdgiJ2hNhE15MNnHbavksg0pT+GTnDyLv9Fm9aUB5Xq5L6lG6p6iEYsOE63A5 YnutgVL6XXOnyyZa+zNI2YSMYz/NDlpInXATtZhQRWCRTKZNhQufYgofxUlElAtiAfCn 23E6Ei9ToO4N6OF4xkKf14ITfWnzn1iKMovTUa+izHmKAQegolv45S+SeFB76zp8rcuq K0hGodZrBkWOE4Ce0nwlnaUuXVRHq8a66+okR3qVmFpqmuXN9UhgFc91RzrvCwgcA/sb yUzk5WQWIgKWl6FuxEVY5k17vo+Yk3+H2Wwyn3UPOzaQ52OLRPL6LuzOMw9WcvWqmnhN +uMw== X-Gm-Message-State: AOJu0Yzowy1KWp2ThlN/E1qdrY9DyvZ4w7y+uuE/Rm9FMymiTfcYTObq jQCE/UuF/3bry6sCx3k+gA8Tai3XfXDbp66IxLLicm9lwCnk2LHxX/VKG3E+UsfnByvqA7/4+zX xSeZt X-Gm-Gg: AZuq6aIdwOVdTUxtCqaNZqoxKAAvIq4Us5CI89FEb6Hg2SAdRD0y0KlpfPY0nXPlZmU IidCIAy1nHURXmJsqVuPRjb5RLdxYBbb36SXr0oZntOMbKYRnSSqNkSGFRcylNliBWcB9TVwIuj sCXnxzHMcgdm+Dn2DfOHp542MVqeHJzYmIUoZJTuzgiruiQGnvnVD2s6nnx3q9YvVN33oMKBnBU unFvd/WboNSw37r8B+ilC5mrB/7XSbdyzZgPImcO4kubPkv6JRqbKgs6tgSEQa2YSDSzvwCw2/8 9ScUanZe7YvVAaoixQ9mzIaldMpkLv5rw/3TNxAO/C1HQSOiLxGiIfxXnWh89AxufMXm6lqpTdm 7/Jr0vYEYZX38cmGlEaRwf3/kn2Ah5coSbJu4rXUJ9KoEpEoGruwfkCJ7cJASFqrRUhFCYmwHS9 TqxjI1HyUcx+i1gZViZqX/4x0OEjmilqxgrZsNWfNna9SldCjbCEL1Isz5qFd1BN4qZS2q10gc8 pji9PLvgROPCsE/W8WX0E8/houX3TU= X-Received: by 2002:a05:600c:4f8a:b0:480:3230:6c9b with SMTP id 5b1f17b1804b1-483201dd004mr213407675e9.7.1770731529465; Tue, 10 Feb 2026 05:52:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/26] accel/system: Introduce hwaccel_enabled() helper Date: Tue, 10 Feb 2026 13:51:42 +0000 Message-ID: <20260210135206.229528-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731613561158500 From: Philippe Mathieu-Daud=C3=A9 hwaccel_enabled() return whether any hardware accelerator is enabled. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- include/system/hw_accel.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/system/hw_accel.h b/include/system/hw_accel.h index 55497edc29..628a50e066 100644 --- a/include/system/hw_accel.h +++ b/include/system/hw_accel.h @@ -40,4 +40,17 @@ void cpu_synchronize_pre_loadvm(CPUState *cpu); void cpu_synchronize_post_reset(CPUState *cpu); void cpu_synchronize_post_init(CPUState *cpu); =20 +/** + * hwaccel_enabled: + * + * Returns: %true if a hardware accelerator is enabled, %false otherwise. + */ +static inline bool hwaccel_enabled(void) +{ + return hvf_enabled() + || kvm_enabled() + || nvmm_enabled() + || whpx_enabled(); +} + #endif /* QEMU_HW_ACCEL_H */ --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731545; cv=none; d=zohomail.com; s=zohoarc; b=KgMmLzBJH/AlE0bAU1E5sKvGGmzH3u/N6MnuebsqFaSS/RaWtXhrAEf0UUh50nh5LNVKdK30SaJMssoqcLtWHdbYxh7LG4ZaWkT6cDNo79B6YliKcTsIx+sg/SLLdYQMX/c5hXixqTRITO0G+GaZ3wPgOQstZFaTBN+PGTj63bQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731545; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=kRnQjA9jSF81pcrYcyyCazxZX5v6kwI9Yceq4/A0UbA=; b=cYnY7t5sKZuy/vY2HQbY5oRBZLRR0/whBqglySFSIjFwq50wOwPuxxlGWmeIjzdCB923xnFzdEjYHxzABZarTcwjyF7H/j1ylqCN+sdJjL6iuLKLptlbxOX8Qg4iDmYakrGlVEao6+hmbXZNzEALenh+WqUunPH1ajWkHYgAWeE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731545757850.9852844618434; Tue, 10 Feb 2026 05:52:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAB-0001zz-6o; Tue, 10 Feb 2026 08:52:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA1-0001vw-GL for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:13 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpo9z-0006JI-Ry for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:13 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4834826e5a0so9780955e9.2 for ; Tue, 10 Feb 2026 05:52:11 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731530; x=1771336330; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kRnQjA9jSF81pcrYcyyCazxZX5v6kwI9Yceq4/A0UbA=; b=mFU8Hhplivkc0cojLcWM+36U0mikYcT2SpZKZ58LYz6eHtyVKPyWotI/aCJQYGdivJ mVHORUmu7p6cq031DccXqR2OgGjlVt/wrv3FDORj4ZJ8gBIsmMU5XhwtHxQOyrPWpv85 u4F8iD6V5Aa0DbFmKmNROszhgXkb9o5CqaP/10VEunOg25OoxeDE3kau24RWbS2IUENj MBERhJAo8aW7Ciz7vVAAsUeg6rZ9T7OnuHfkbsLlrc54IojgAT1mvA/M+R+a8+8Z5mC7 xde0ki41yRtbuRBvAjDYrYIKKEe3LgEzF0XhuDsOxJdz/BwF5Uv+O7SHCag/kdpIkIZw nxsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731530; x=1771336330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kRnQjA9jSF81pcrYcyyCazxZX5v6kwI9Yceq4/A0UbA=; b=RtzPu5PxCPdoQuui6jNc4Zvu/AU5Cp/JAnMPZ7eCgnMAgS0/7IYsLyaqnb36msS1fs 1/cBmOLeIYZ5dM5b1Cul+n5xiwRgd027/dT2Ktu62s9vHz+xR+gvpWxTUXSgQ9rFyss1 8bZFZ8rU6PKA7aiQU/Nf26E+CHSmucs2c1+xX9N9luMyuvHFO/yTVo7ZlTFG07TvAUFG tsXq9bmnjK8pp6hiG2PbGFj4UbLnqj9eG1oHk06/81jlQ3FEFmZNSElWJUFbPhEbfyMM /EgxoljMWeTgO1XyA3C+l188EC/gkHuO/LeBebOP3SJMqG1g100N9sm8dx1T+4iOnF8H uRRw== X-Gm-Message-State: AOJu0YzocIDuPV8aJFtTk0WjCT/QPmNy1JLO3RqIFs0F5DP5rNa0yIRL XkPhJqR94iBEofP0LN/dwE4adkoPzIAxAHWQrD3t84ZC9xi/ZCwSvvKzm3/OOUbUVq2WtEfqtlN tG4Cz X-Gm-Gg: AZuq6aL34YaLxTNNTrKXn+QFBKMaYqHIJtajEjXsy8m2ab2kryH3r0FsH6Wf9wgZikO WTKJkJiw2Clgod3je5XHj3qBAtRoY+5x06ggAFT/EPfnhyO4Q7UKD9N6OI5iMxHGrP+egpTLjGY x1kIv44IN/ERMWtmh6TwPL3ehheWndvaYfiiGbX9MO1StObT330wBXpXREEYItcDv2sGwXwT95h 2kNT+Z9pJyQX69qMwOAwuQ1sPNbYjbzKdAqSFiany+67KSxCfwqocaO/WByUhc7Px9qj8GSqSlP 3uDBkOXZT04Wq8nNkeuHSsh3pquW/v9x7rC0/1t0mtQODKEUDf9a7W+dWuWPMARLz6G8MG/7pK9 NKMW0cHZF0PRE7khByP00sAbXDlv39c1IzggeyQmjNjX6WTtKwTAKHkfEN3MAUWVbeZT6/tGuFy qI0rnCBDVTw5bZlUGpaa1dHoAHQOt1ZhHVNIWt9artfNgiSTLn9ENaQI2uhJz9yUkkKh9OAkS5K dSHZylwto6Vm5+E3JLLBb4jfGV1FdQ= X-Received: by 2002:a05:600c:3f08:b0:465:a51d:d4 with SMTP id 5b1f17b1804b1-483201dd06bmr224740775e9.6.1770731530369; Tue, 10 Feb 2026 05:52:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/26] qtest: hw/arm: virt: skip ACPI test for IORT with GICv2 Date: Tue, 10 Feb 2026 13:51:43 +0000 Message-ID: <20260210135206.229528-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731547256154100 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Signed-off-by: Mohamed Mediouni Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..7acaf464dd 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/IORT", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731649; cv=none; d=zohomail.com; s=zohoarc; b=TnVpYaf+cYotxtS31zHMPVp/ORBaJehLcclxWXFbF/lRZGlhhoMcZJNcSb32XEpDD/jq8i5YMCWDMKm+K3HJBp/OkUMiyRRXKnrUDz0ERCPaYMhV5FLl+fxu5mqTTM8E1bNrsNkFFK/wMkiiuQC8FwtVkgTympQOKefF/CLaoqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731649; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2HDpSufvcJSJA6ud+97uY5GnYwnUWYupJFSv2xK/Nuc=; b=AHEg4bseQs8IKUYEZgNaPLN8j8arhUn8THFoeCKtVdtvb9HvguONwFhnxQ/kM/3SRvY/WwvebG3aohy+56BK30NgE8Jfo5aGYWrtl4vgT64UVeQGT/6rJ0wnKoIpFo+Wtr9BUrAiOLoIo/E4zbjSYRGT/su4/4lsPe2h6ZlGQBo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17707316488987.677937171837243; Tue, 10 Feb 2026 05:54:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAC-00022V-G4; Tue, 10 Feb 2026 08:52:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA3-0001wc-Gh for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:15 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA1-0006JY-Du for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:15 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-47edd6111b4so82572605e9.1 for ; Tue, 10 Feb 2026 05:52:12 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731531; x=1771336331; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2HDpSufvcJSJA6ud+97uY5GnYwnUWYupJFSv2xK/Nuc=; b=E+GGB2spPJtJsZFPcDLjQRA1nZhLteD8dFX62TITn0yP4NmXiqcRw8RZxHdKLPAks1 G2HphIW59MaPNuDUlc0IZ75rEfxuy7u4NruUoVCl+qkAocpGWDh10W+KhtqlIZYFyt5T P4nqSN/E2WgPcJ9kdWFqRRQyjGV/IC0gJSvMebEg9D/cxsNr5JqKzZAhanvHpgnNT3oj soDGp9er46zVqKbCEFI0elNQkxxOkoDUhD+7QgTF9I72sX5sOfp5P+z6cdAaI8qp9Pyw 07DumJyBcG0S300JlHDB3O/5h+riRpzKVYQhxDei9VwrerkydL9h+7ZuphMBVw7MeXv1 Axdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731531; x=1771336331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=2HDpSufvcJSJA6ud+97uY5GnYwnUWYupJFSv2xK/Nuc=; b=T+KWNR6N7CSxsC37uN6dfny1RtjiUZQvuSqPBTMh4Z8My2YvUnASUWNTsmnQVilm39 X4d+MUhVTfnBQbo7ibX1u5ZgF8yswdbLf0EeBNfJp18lOgI94HAtRvfe9+J8NNV4EWtB l4CUcbzWYp19v2Rf26GPaVIHK23Glvy/aJryqScnyTbnP3qOaGyiQro0iPhixhtB//pE FYOlect7xhMgmwuk74A6DOcdX4TiVoHV4Yp7uYdsDKLP9xkIynlXs8/zJ69NpVuSpXgd soMsax+HMGMKXnmiQzlvL4SGpnVMy1yBOJfvghgAkNybJ1sgjNv+KwNMa1DRMbOnlLc6 fBag== X-Gm-Message-State: AOJu0YwmoLdivoymUQ16I4EeU8lX6xq7v2P2FaKGonMni/3NWYvpisbA /DbDSdPOlhCan0juVqdaEmBfu5cDTndWj5Up2lZg2Ip9gGe7rA51N0WYM2yfcagKGkUZRTX5JRK cM/a3 X-Gm-Gg: AZuq6aL+CBUEFtOmJJzRcABbLMjlega37j4JM8Gqc+H6pb6vePGiBlOVD8Udx9yuwHi DuzepqZaA6nRGFKT6OnUDk8wL7iEZMCpoFeOVp5xqEBwPnUB2ZfBC8rK/Ao+9soK9i4RuXmAfwM EAzv9SwLdwrMU7dx995y7J5PCTA3cKkMTrP4+pj5pVsa3eo+4z1nDvQj/0REassDiBKTWh0ZOsc RHeU2L8pRwGBS56jZh/8H8IqzO5X1zuGrMRRzS7ajn+cPFBEMovxfDAQ3Qg5EwbHndUFv6oj83M Itix0hwamXVd96qL02gWiHp/cH7Mzv923g+nRQqDpaLIsm3GqGNO4uDMsw8shAbC3XSMibgxlzz S237ssPLDmMoQfzP4buGq/hkqUJe7wo+yjSmZdulyNqajQOENsqaXjoVzNq1yXREK2COOixQg70 s/JMHb4WgStSOZcv6HWKsV2o+K7+IVzQuI1ogWo+BSOMmeF6GvmIILSekMD9aYALWKAIyJC43Cz /Wzsz8CtL6BlBhic/2uS/ZKEbQccac= X-Received: by 2002:a05:600c:828e:b0:47d:6140:3284 with SMTP id 5b1f17b1804b1-48350835edfmr28495215e9.37.1770731531246; Tue, 10 Feb 2026 05:52:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/26] hw: arm: virt: rework MSI-X configuration Date: Tue, 10 Feb 2026 13:51:44 +0000 Message-ID: <20260210135206.229528-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731650944154100 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Introduce a -M msi=3D argument to be able to control MSI-X support independ= ently from ITS, as part of supporting GICv3 + GICv2m platforms. Remove vms->its as it's no longer needed after that change. Signed-off-by: Mohamed Mediouni Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 20 ++++--- hw/arm/virt.c | 119 ++++++++++++++++++++++++++++++++++++--- include/hw/arm/virt.h | 5 +- 3 files changed, 128 insertions(+), 16 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index c145678185..544004615d 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -569,7 +569,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) nb_nodes =3D num_smmus + 1; /* RC and SMMUv3 */ rc_mapping_count =3D rc_smmu_idmaps_len; =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { /* * Knowing the ID ranges from the RC to the SMMU, it's possibl= e to * determine the ID ranges from RC that go directly to ITS. @@ -590,7 +590,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } } else { - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { nb_nodes =3D 2; /* RC and ITS */ rc_mapping_count =3D 1; /* Direct map to ITS */ } else { @@ -605,7 +605,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { /* Table 12 ITS Group Format */ build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Ty= pe */ node_size =3D 20 /* fixed header size */ + 4 /* 1 GIC ITS Identif= ier */; @@ -624,7 +624,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) int smmu_mapping_count, offset_to_id_array; int irq =3D sdev->irq; =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { smmu_mapping_count =3D 1; /* ITS Group node */ offset_to_id_array =3D SMMU_V3_ENTRY_SIZE; /* Just after the h= eader */ } else { @@ -717,7 +717,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { /* * Map bypassed (don't go through the SMMU) RIDs (input) to * ITS Group node directly: RC -> ITS. @@ -735,7 +735,9 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) * SMMU: RC -> ITS. * Output IORT node is the ITS Group node (the first node). */ - build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET, 0); + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { + build_iort_id_mapping(table_data, 0, 0x10000, IORT_NODE_OFFSET= , 0); + } } =20 build_iort_rmr_nodes(table_data, smmuv3_devs, &id); @@ -1053,7 +1055,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) memmap[VIRT_HIGH_GIC_REDIST2].si= ze); } =20 - if (vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { /* * ACPI spec, Revision 6.0 Errata A * (original 6.0 definition has invalid Length) @@ -1067,7 +1069,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].bas= e, 8); build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } - } else { + } + + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_GICV2M) { const uint16_t spi_base =3D vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BA= SE; =20 /* 5.2.12.16 GIC MSI Frame Structure */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 390845c503..aa5e992712 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -737,7 +737,6 @@ static void create_its(VirtMachineState *vms) { DeviceState *dev; =20 - assert(vms->its); if (!kvm_irqchip_in_kernel() && !vms->tcg_its) { /* * Do nothing if ITS is neither supported by the host nor emulated= by @@ -957,9 +956,9 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 fdt_add_gic_node(vms); =20 - if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { create_its(vms); - } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + } else if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_GICV2M) { create_v2m(vms); } } @@ -2137,6 +2136,44 @@ static void finalize_gic_version(VirtMachineState *v= ms) gics_supported, max_cpus); } =20 +static void finalize_msi_controller(VirtMachineState *vms) +{ + /* + * VIRT_MSI_LEGACY_OPT_ITS_OFF is an option to replicate + * behavior of its=3Doff when running with a GICv2, where a + * GICv2m is still present. Otherwise, it behaves the same + * as msi=3Doff. + */ + if (vms->msi_controller =3D=3D VIRT_MSI_LEGACY_OPT_ITS_OFF) { + if (vms->gic_version =3D=3D 2) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } else { + vms->msi_controller =3D VIRT_MSI_CTRL_NONE; + } + } + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_AUTO) { + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } else { + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; + } + } + + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + /* + * The legacy its=3D option in earlier releases allowed specif= ying + * this configuration and treated it as GICv3 + GICv2m. + * Diagnose it as an error even for that case. + */ + error_report("GICv2 + ITS is an invalid configuration."); + exit(1); + } + } + + assert(vms->msi_controller !=3D VIRT_MSI_CTRL_AUTO); +} + /* * virt_post_cpus_gic_realized() must be called after the CPUs and * the GIC have both been realized. @@ -2256,6 +2293,7 @@ static void machvirt_init(MachineState *machine) * KVM is not available yet */ finalize_gic_version(vms); + finalize_msi_controller(vms); =20 if (vms->secure) { /* @@ -2705,18 +2743,76 @@ static void virt_set_highmem_mmio_size(Object *obj,= Visitor *v, extended_memmap[VIRT_HIGH_PCIE_MMIO].size =3D size; } =20 +static char *virt_get_msi(Object *obj, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + const char *val; + + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_NONE: + case VIRT_MSI_LEGACY_OPT_ITS_OFF: + val =3D "off"; + break; + case VIRT_MSI_CTRL_ITS: + val =3D "its"; + break; + case VIRT_MSI_CTRL_GICV2M: + val =3D "gicv2m"; + break; + case VIRT_MSI_CTRL_AUTO: + val =3D "auto"; + break; + default: + g_assert_not_reached(); + } + return g_strdup(val); +} + +static void virt_set_msi(Object *obj, const char *value, Error **errp) +{ + ERRP_GUARD(); + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + if (!strcmp(value, "auto")) { + vms->msi_controller =3D VIRT_MSI_CTRL_AUTO; /* Will be overriden l= ater */ + } else if (!strcmp(value, "its")) { + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; + } else if (!strcmp(value, "gicv2m")) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } else if (!strcmp(value, "off")) { + vms->msi_controller =3D VIRT_MSI_CTRL_NONE; + } else { + error_setg(errp, "Invalid msi value"); + error_append_hint(errp, "Valid values are auto, gicv2m, its, off\n= "); + } +} + static bool virt_get_its(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - return vms->its; + switch (vms->msi_controller) { + case VIRT_MSI_CTRL_AUTO: + case VIRT_MSI_CTRL_ITS: + return true; + case VIRT_MSI_CTRL_NONE: + case VIRT_MSI_CTRL_GICV2M: + case VIRT_MSI_LEGACY_OPT_ITS_OFF: + return false; + default: + g_assert_not_reached(); + } } =20 static void virt_set_its(Object *obj, bool value, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - vms->its =3D value; + if (value) { + vms->msi_controller =3D VIRT_MSI_CTRL_ITS; + } else { + vms->msi_controller =3D VIRT_MSI_LEGACY_OPT_ITS_OFF; + } } =20 static bool virt_get_dtb_randomness(Object *obj, Error **errp) @@ -3043,6 +3139,9 @@ static void virt_machine_device_pre_plug_cb(HotplugHa= ndler *hotplug_dev, db_start =3D base_memmap[VIRT_GIC_V2M].base; db_end =3D db_start + base_memmap[VIRT_GIC_V2M].size - 1; break; + case VIRT_MSI_CTRL_AUTO: + case VIRT_MSI_LEGACY_OPT_ITS_OFF: + g_assert_not_reached(); } resv_prop_str =3D g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u", db_start, db_end, @@ -3463,6 +3562,12 @@ static void virt_machine_class_init(ObjectClass *oc,= const void *data) "Set on/off to enable/disable " "ITS instantiation"); =20 + object_class_property_add_str(oc, "msi", virt_get_msi, + virt_set_msi); + object_class_property_set_description(oc, "msi", + "Set MSI settings. " + "Valid values are auto, gicv2m, = its and off"); + object_class_property_add_bool(oc, "dtb-randomness", virt_get_dtb_randomness, virt_set_dtb_randomness); @@ -3518,8 +3623,8 @@ static void virt_instance_init(Object *obj) vms->highmem_mmio =3D true; vms->highmem_redists =3D true; =20 - /* Default allows ITS instantiation */ - vms->its =3D true; + /* Default allows ITS instantiation if available */ + vms->msi_controller =3D VIRT_MSI_CTRL_AUTO; /* Allow ITS emulation if the machine version supports it */ vms->tcg_its =3D !vmc->no_tcg_its; =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 3b382bdf49..8069422769 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -101,6 +101,10 @@ typedef enum VirtIOMMUType { =20 typedef enum VirtMSIControllerType { VIRT_MSI_CTRL_NONE, + /* This value is overriden at runtime.*/ + VIRT_MSI_CTRL_AUTO, + /* Legacy option: its=3Doff provides a GICv2m when using GICv2 */ + VIRT_MSI_LEGACY_OPT_ITS_OFF, VIRT_MSI_CTRL_GICV2M, VIRT_MSI_CTRL_ITS, } VirtMSIControllerType; @@ -146,7 +150,6 @@ struct VirtMachineState { bool highmem_ecam; bool highmem_mmio; bool highmem_redists; - bool its; bool tcg_its; bool virt; bool ras; --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731560; cv=none; d=zohomail.com; s=zohoarc; b=AC05OAUuNg+BHP5vsWQBBlB+laLrIjq+4kR9g03sEzC8edbk5QKAr/fE3+VtRJYPdwuUns4G2du4ctg4ds1QHPTRG+kz4eQ+TajkrfgI+lOGomyPN8wok6tknTiM7tyOxRbzDL3REcbmt6YeZ0PXi3RfZyz68FVJzVVGxg3M/xA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731560; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Zta9umikbAPUw+uUWP55d9xpJhXgxfyHHlklUmDXa7k=; b=CbSL4VZQennP+7n6R73afnO5KG5TSVrrKS2kSEbZfEoSz9YqBwKGkCi6lFBD3Vj8lwQmDwPdnWyETp8P7Ml5EU5Axu65PIn16++5CNHGx3T8kw1zhWgBtMem2V3FMcPTA81maSn8lbSyddhsMFmJXGELQyS10v3zf241KQXhZgU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731560003273.1641786929888; Tue, 10 Feb 2026 05:52:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAC-00022q-VG; Tue, 10 Feb 2026 08:52:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA5-0001yo-8R for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:17 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA1-0006Jh-S2 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:16 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4833115090dso8111455e9.3 for ; Tue, 10 Feb 2026 05:52:13 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731532; x=1771336332; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Zta9umikbAPUw+uUWP55d9xpJhXgxfyHHlklUmDXa7k=; b=fClKSFuaACpNYtQ6D/HmhHTtl9AB4rVEr83BZY+NkfdLoQtX8TtqdAoJQ8BSESU3zr rbuYYWc1BdUe0tgvMjXXbeoSC/3J5/VMbhSNLIdBS75ZNxt9s9KqRounFY9n0qPeqj68 ms/XJ7Qp2hL+kyXlifPA6IayATTB0/s2QfVEXmQEZ7VT+oGSiehsBQOw/8M5lR8HsJrj 4Od+27CfKWRFZCKi7mYhmuQwEIEYqmC5X0hxsvTwYQ7dMprsKWsDzE/Kxi7+PSNiRE2G jxyUMwzICVdSO+PbJuy5Qc7d9VILPlH7nO7M1dc5O2HmtZ5hMYTxCL4d1lR88bbeHczS XYVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731532; x=1771336332; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Zta9umikbAPUw+uUWP55d9xpJhXgxfyHHlklUmDXa7k=; b=X95FogecbPRFuK2Jl/FJGeKhaOhW2TAg3VEhN0rRoCQPMiIPbuzVcY67jkjRSTLgX0 mI7x3t0+RS+avAdJaVP51htTNyUx+UfjX+XFC3GeVeVnjdy6A5PBCXrtXZfyP42Shdv7 +gMTgbPfUnoOImyKIjQEF92OuqrC6MMzRC17rnZdhqvF9ptLI6oierwmAsbVj8YS/I3L 8UbmJZAUSbVUR0dhRfbqAEikEkKnFZ+auBB95aS0/jBCOsrY7X5loKhR6T88WfZkNvR+ RcZ9Ui5i+t4xhYbwSf6dWD0MhQH20fCk+YvtpTtWzVRn8MM7f3gnyetp6APmpyWMtnqL 9D1Q== X-Gm-Message-State: AOJu0YxFVHeP8gBZ5TRyI9cQI3Ck/XIjQlnRxhCE08JZ/SsvaY06BsEl /kRZNk1xip9DR9ARZ9CtBJ1x7omXX5sYLYdAhjMuemhYb0XGUEdwJgw45fh5lbvs9+zhNq1qmrB +Jyoa X-Gm-Gg: AZuq6aI5kNYdLWJcIeWXvjqLPtFwfI/+Z/GCFMpFNT5p663Zm5i9g4pPhSUnbKx7x1Y syVgVU7X4f5tX0JmBC05G9d97kRja78Rx0pOzEaDu+Pkdpb/R7q+wz5S0MDjz0PJEHJi/m0xUvg B4l4uL/UWalI9soBTxFW8SKQJGBV1pcAw6We1moMLqh1ZszEabNidX6qTUPmlqD82Xgq3I+2hKO gVLXviPVpHv2Iiaw15yNtjZFuRgNBth1db9MwiLKbW3KvSO7DWaKY4J+Gr0m+eIGRpyZX02jJrx PKhP0Dk4ku3B3MachUKOQYcLOQFz9Xhe279gv8o5WoeR4uioRUzKEbz09naWDtJFyYP0t1flbGj RHuU+4IbJx882Wr4SBInUh4p3EWalT74O61t/hNdkRjPSEnTqpnEeSkQv60wBasr/KYf1FudDYr DCBuE0VYWQGbO+57ZuNrEGUux1UgM6ARslhXHmJ9V1HYc5HmdvJ7Q/aSj8qyUkk32DZIfraMjQF EawRKg4wc8H0LE0OSocjgN+5P9QpzA= X-Received: by 2002:a05:600c:674f:b0:471:13dd:bae7 with SMTP id 5b1f17b1804b1-4832022aee5mr194308745e9.30.1770731532085; Tue, 10 Feb 2026 05:52:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/26] tests: data: update AArch64 ACPI tables Date: Tue, 10 Feb 2026 13:51:45 +0000 Message-ID: <20260210135206.229528-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731561324158500 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni After the previous commit introducing GICv3 + GICv2m configurations, update the AArch64 ACPI tables for the GICv2 case. Changes to the ACPI tables: tests/data/acpi/aarch64/virt/IORT.dsl: @@ -11,68 +11,49 @@ */ [000h 0000 004h] Signature : "IORT" [IO Remapping Tab= le] -[004h 0004 004h] Table Length : 00000080 +[004h 0004 004h] Table Length : 00000054 [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : B1 +[009h 0009 001h] Checksum : 3C [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 -[024h 0036 004h] Node Count : 00000002 +[024h 0036 004h] Node Count : 00000001 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 -[030h 0048 001h] Type : 00 -[031h 0049 002h] Length : 0018 -[033h 0051 001h] Revision : 01 +[030h 0048 001h] Type : 02 +[031h 0049 002h] Length : 0024 +[033h 0051 001h] Revision : 03 [034h 0052 004h] Identifier : 00000000 [038h 0056 004h] Mapping Count : 00000000 -[03Ch 0060 004h] Mapping Offset : 00000000 +[03Ch 0060 004h] Mapping Offset : 00000024 -[040h 0064 004h] ItsCount : 00000001 -[044h 0068 004h] Identifiers : 00000000 - -[048h 0072 001h] Type : 02 -[049h 0073 002h] Length : 0038 -[04Bh 0075 001h] Revision : 03 -[04Ch 0076 004h] Identifier : 00000001 -[050h 0080 004h] Mapping Count : 00000001 -[054h 0084 004h] Mapping Offset : 00000024 - -[058h 0088 008h] Memory Properties : [IORT Memory Access Propert= ies] -[058h 0088 004h] Cache Coherency : 00000001 -[05Ch 0092 001h] Hints (decoded below) : 00 +[040h 0064 008h] Memory Properties : [IORT Memory Access Propert= ies] +[040h 0064 004h] Cache Coherency : 00000001 +[044h 0068 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 -[05Dh 0093 002h] Reserved : 0000 -[05Fh 0095 001h] Memory Flags (decoded below) : 03 +[045h 0069 002h] Reserved : 0000 +[047h 0071 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 Ensured Coherency of Accesses : 0 -[060h 0096 004h] ATS Attribute : 00000000 -[064h 0100 004h] PCI Segment Number : 00000000 -[068h 0104 001h] Memory Size Limit : 40 -[069h 0105 002h] PASID Capabilities : 0000 -[06Bh 0107 001h] Reserved : 00 +[048h 0072 004h] ATS Attribute : 00000000 +[04Ch 0076 004h] PCI Segment Number : 00000000 +[050h 0080 001h] Memory Size Limit : 40 +[051h 0081 002h] PASID Capabilities : 0000 +[053h 0083 001h] Reserved : 00 -[06Ch 0108 004h] Input base : 00000000 -[070h 0112 004h] ID Count : 0000FFFF -[074h 0116 004h] Output Base : 00000000 -[078h 0120 004h] Output Reference : 00000030 -[07Ch 0124 004h] Flags (decoded below) : 00000000 - Single Mapping : 0 +Raw Table Data: Length 84 (0x54) -Raw Table Data: Length 128 (0x80) - - 0000: 49 4F 52 54 80 00 00 00 05 B1 42 4F 43 48 53 20 // IORT......BO= CHS + 0000: 49 4F 52 54 54 00 00 00 05 3C 42 4F 43 48 53 20 // IORTT.... Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/data/acpi/aarch64/virt/IORT | Bin 128 -> 84 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-dev | Bin 364 -> 260 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 276 -> 192 bytes tests/qtest/bios-tables-test-allowed-diff.h | 3 --- 4 files changed, 3 deletions(-) diff --git a/tests/data/acpi/aarch64/virt/IORT b/tests/data/acpi/aarch64/vi= rt/IORT index a234aae4c2d04668d34313836d32ca20e19c0880..389f7a8d7d6fa47a3e2b6116960= 4e580afe0e07b 100644 GIT binary patch delta 42 ocmZo*4B_(h4+;rkU|?XinaCw2$_Qi`05J$KsW32u850Ag0fA}+)Bpeg literal 128 zcmebD4+?2uU|?X~=3D;ZJ05v<@85#X!<1dKp25F11@0kHuPgMkDCNC*yK93~3}W)K^M VRiHGGVg_O`aDdYP|3ers^8jQ#3IPBB diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev b/tests/data/acpi= /aarch64/virt/IORT.smmuv3-dev index 43a15fe2bf6cc650ffcbceff86919ea892928c0e..60cfed1361976ef26b280c11ba2= e233f1cfd9383 100644 GIT binary patch delta 107 zcmaFE)WXE&=3D^qrr!pOkD>N$~1N|Kp@fx!TXL4d`Dfd#?>k`qJCc|ig|l@Ks-tvM%? f4+Aq3kjpfgkx^X+rjJ2@f#E+$5s)r{C}scviuDRY literal 364 zcmZ{fJr2S!3`R{GHjrRr?7#sy0%{q`R0Iq?1S1FGpOxcq8mQ3)t zYVYaX4D^|s{hfQ^-WA=3D^4SmP&+-xs-&ISG36s0{Cg_tMzsZpm|Mj~NF{9%j*{g48; Ly=3D4r0!Ej@55yu$; diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy b/tests/data/a= cpi/aarch64/virt/IORT.smmuv3-legacy index 5779d0e225a62b9cd70bebbacb7fd1e519c9e3c4..e2de4049f044bdfe5b3e656b942= 82ddf17832d9f 100644 GIT binary patch delta 74 zcmbQjbbyh|(?2NW00RR9tIR|$DM=3D$0E=3D4*h5!Hn literal 276 zcmX|*F%E-33 (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731546038574.0700632654738; Tue, 10 Feb 2026 05:52:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoA6-0001z8-Ba; Tue, 10 Feb 2026 08:52:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA4-0001wl-Ch for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:16 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA2-0006K1-ST for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:16 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4806e0f6b69so43254925e9.3 for ; Tue, 10 Feb 2026 05:52:14 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731533; x=1771336333; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=R0wmLJLjqxq45RUQOtCvknbHxTskZboCDzivlPkD7iw=; b=cuYQPKXrroVjzJB4EEjENiwP0GT2YgVFjkJuyh/k4Oie3cGYofIHM8dj5ksaGn2FGa /At1sl9SN9HnR/h4/3vyDi+Qzf1SQ9xcIqFPczMa/nhnhOwEOeB+jYsMnntAPvqO982q diDYMb/G1eSW1xi6sqOp2xwniVC0y3JyqyfwdWOl5BJeX6b+k5dxoHS+qJ1V2YejczhP uj1CXPqrAqmFJ4KgOpypYMxdZzcJ4fpXfT8LL5kWKwlxleXvDKQwytsceq1IJO5xA+G6 zqnyUSP885iQZvApm6YFjIi/+Te+4DPkppZCr0Vn3n7fKHasxghmu7Qmzm4gh6h65tXa VXDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731533; x=1771336333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=R0wmLJLjqxq45RUQOtCvknbHxTskZboCDzivlPkD7iw=; b=F7Fhdm50nY4JQ1RCwsAPohVjO8c2nqZOQoHtknRxQEkWwWwoznEXwns9LlMsUvMf/+ v0CW2adwhB741gdB7SgSfFbqLcLs2Mns3EWYct6ZBSazxEbkdXpftyKf7FwDK9QJGm6e jiePp+pU41IRRM8u7KiFaxRhbEMF7NGIgnNA3IDlLWd8ChegfWIbyI9tgOCzYPxxdegD lI7/yN+XMzYVnxjKrn5BXDCTKLbFwBXgich8jqyJYVWFHZfjVLZvMRS5pv/Fr0IOiD0y KkUxLL4g6uajfiYfn0mvFJwSDzYjzLaslXFlcmm1xc7h5EMbr3BD70hTYEPliLXh/SOY 2Y3g== X-Gm-Message-State: AOJu0YxLoOx+JvOSFSlSWWM2PGwqCLoe3DDuljnA171ycKmzg28LATG4 ZIMfzH54uPHZe1evx+9TSQrtjRX72+9PWJlUMdQXsSTJtxyP59jJSHZYnRh9nKV9ksLnVzmjADp 697s8 X-Gm-Gg: AZuq6aJ7SgQ3y+E32UO/rQ8cg5F7Vx/CYg++rpCeJHLpcCJ9u7n0rx67liQEGlH3Rsx IOtINqCDOO92QLh8aZELe9We4Hl7Bd2Mc2foTx24zhF6jbFm+uZTtYr0e7GwExTfLZkHZY6yEj7 yX6iqYafDyRYoRrF0lNDvqabn6Nn/qGJKbtQ/2s8emCuM+3702DUyvwJ7p7AMEB4LmS5oQcXmaS ymcHnWbPMFKdS/mI+3wLSUh6A9j1dOs0UIBkRq2+n1tZkP1po/7ORRYPeHg+rOZwDTSCMdd0aoP eZABhacOonr6dPcEkjIiYjJcdtqli7SOKc0LLkfgJffKBW2eVdubUslvwp2ZNXViuy79GEQCFCE lqLrM5rWuZ56WApfC98FNxe5uZdiG9iaV9XP0IrRcmfHkr1cBddwKMYhmPI0Ga6aogyohJQkkT2 UwKkE2fcML8vDyD/Fx6nk0p2esG12r0e/EmA3mbhB0cFEmjXK8BMHCaghpiqLR7V/UXhsT08iTy 67kpUSzWai8VhrHT7C6MPPrmjotahU= X-Received: by 2002:a05:600c:1548:b0:47e:e20e:bb9c with SMTP id 5b1f17b1804b1-483507cff93mr33300125e9.8.1770731532886; Tue, 10 Feb 2026 05:52:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/26] qtest: hw/arm: virt: add ACPI tables for new GICv3 + GICv2m test case Date: Tue, 10 Feb 2026 13:51:46 +0000 Message-ID: <20260210135206.229528-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731547214158500 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Signed-off-by: Mohamed Mediouni Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/data/acpi/aarch64/virt/APIC.msi_gicv2m | Bin 0 -> 188 bytes tests/data/acpi/aarch64/virt/IORT.msi_gicv2m | Bin 0 -> 172 bytes 2 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 tests/data/acpi/aarch64/virt/APIC.msi_gicv2m create mode 100644 tests/data/acpi/aarch64/virt/IORT.msi_gicv2m diff --git a/tests/data/acpi/aarch64/virt/APIC.msi_gicv2m b/tests/data/acpi= /aarch64/virt/APIC.msi_gicv2m new file mode 100644 index 0000000000000000000000000000000000000000..16a01a17c0af605daf64f3cd2de= 3572be9e60cab GIT binary patch literal 188 zcmZ<^@O0k8z`(#_;N}2A literal 0 HcmV?d00001 diff --git a/tests/data/acpi/aarch64/virt/IORT.msi_gicv2m b/tests/data/acpi= /aarch64/virt/IORT.msi_gicv2m new file mode 100644 index 0000000000000000000000000000000000000000..0cf52b52f671637bf4dbc9e0fc8= 0c3c73d0b01d3 GIT binary patch literal 172 zcmebD4+>esz`(#d)yd!4BUr&HBEVSz2pEB4AU23*0%8Lo1_2fq1{MelMzV5(SRi%i nAPXpv4aB)XoP#9EWWm4;QV+r^P#Q=3Dv12GslK (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177073159451513.883699694775373; Tue, 10 Feb 2026 05:53:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAB-00020I-Cn; Tue, 10 Feb 2026 08:52:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA4-0001x7-Tb for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:16 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA3-0006KE-EG for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:16 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-47ee0291921so40445955e9.3 for ; Tue, 10 Feb 2026 05:52:15 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731534; x=1771336334; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gFf1z45G5YUmVjhRjNyUdMmLPtBu36lYSS9gfoGGAvU=; b=Sorr4/N+lBly7PyYXEXKE/TukDPdS24wK+zabvChqZdUhdWSXCY3PFQo4DEIwQvDlg VZ2qJKQNrI9P29NULi2/dMyb2xw3RUk4rO9klEV618HF2NQ9rCq3lnPpx3iialFbKR7o H9gOGqi/3mMUn1Jc59aoDVFlVfK9HaiXHA1s0Yhkrdvng39mJN6GCLeB0b3UsU2gLQLk TiD5VyYle+2D2uGXnoLHFDNQA2I95SKKB8hZvVfyLqrQwvt5xiSjKsZGGKL1RyseSw+N 22z5ZQueA3Asc8ecMD417zChtaj7nC4ie+naJUAVdFeaeHGWCdYz8JVwnhSDtB5R4vo3 L1Gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731534; x=1771336334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=gFf1z45G5YUmVjhRjNyUdMmLPtBu36lYSS9gfoGGAvU=; b=eJxDgQoGfI5D5pr5mH3mT6KxmPpw4pESeTsUj465XdCRQU6FZimmW1VEqxJ9wLChoD ie3BF/4cL4W8lrI9JFqKUdRpPMj7sedySvtIDAHMzqQvqxwKvdVfexwHLGZkmeV3Dsnb lbyO4adOxZayprNv7MkfFpVbZZrcWdv4DoRuYaHR9PeVK6c0r1r50KwG00AdwYkdL4oJ 2L/8PpeaFuSfr5FYApj8QYByve9NKm1LWgKBvHbbb0qEeFu0AfnUhuGeZBx1a9YLJcaS BHLQcsdArtL4Nx89348Kuz5AwbkTPMAXWT3aUP+S3QyiyMDL2L6PVF+g+OsazmKLZj/z 4h/g== X-Gm-Message-State: AOJu0Yw+8EGKIj3dADj13O/7RbHktX6Zdynl3n5IyqBVwo/PmQkCH4mT uhuh0REfudo//BvMKTmMjDOkZeQZoG9QcEO0x0ZDlypSk9ipR5EHBNrHnk+YZ2kd6cDEV5Dpjbh js4Rp X-Gm-Gg: AZuq6aLXbriVDOl0B7kB/GxZuNy0IXFBJrcjWiQfTz0AsY+ACwT5z2rOnwwm8/NCBzf aGL1QoJUSytpZivcr7t0Ld4FB4i5dPEvXQlefgj5zCsciRdQSkOTHOHsj2JmCy3P7I0B2HTvmEI FpKFaA8ULFzgrkluFVdaiKcznAwLTbbxX9aimGRV4wNPxUm/Xde3j5s+qdEnTEOaHqlG5NQ9Lq9 fAHQYIVrwWbA7F2iVpCV0UMdcuu/OSMw/jUOwiqblkVnFIShwFRJpbcxppveGQox5/w1KrQqLvc hk1/I+Zv4tVy0P5hPUneftHT7zRddOyzN3wMSYAyfFL5LrBfFHyhJwGszJiPK0ff1cf/I9zUybL hV60b++UDExatOIQwTKjyej/Iye8Ef1DDZaX8nhn4gzU0RNJzX3TiWMRMrXKOcyLjN/LbCrlQZg jDtDCJ8s2VQLA9ck6939+pdwFUfTbWMHoF0Y5w+IA22YmhK531HbUX7IuF04JvE1b4sQA1qNwrN xiMx9oUTjqh4pU0S+shLEGoD3XtnvM= X-Received: by 2002:a05:600c:528b:b0:482:f12f:f35e with SMTP id 5b1f17b1804b1-483201e3759mr219385725e9.12.1770731533663; Tue, 10 Feb 2026 05:52:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/26] qtest: hw/arm: virt: add new test case for GICv3 + GICv2m Date: Tue, 10 Feb 2026 13:51:47 +0000 Message-ID: <20260210135206.229528-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731595428158500 From: Mohamed Mediouni Signed-off-by: Mohamed Mediouni Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- tests/qtest/bios-tables-test.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index e489d94331..a5a5b8807b 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2252,6 +2252,25 @@ static void test_acpi_aarch64_virt_tcg_its_off(void) free_test_data(&data); } =20 +static void test_acpi_aarch64_virt_tcg_msi_gicv2m(void) +{ + test_data data =3D { + .machine =3D "virt", + .arch =3D "aarch64", + .variant =3D ".msi_gicv2m", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .cd =3D "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.= qcow2", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * 1024 * 1024, + }; + + test_acpi_one("-cpu cortex-a57 " + "-M gic-version=3D3,iommu=3Dsmmuv3,msi=3Dgicv2m", &data); + free_test_data(&data); +} + static void test_acpi_q35_viot(void) { test_data data =3D { @@ -2834,6 +2853,8 @@ int main(int argc, char *argv[]) test_acpi_aarch64_virt_tcg_topology); qtest_add_func("acpi/virt/its_off", test_acpi_aarch64_virt_tcg_its_off); + qtest_add_func("acpi/virt/msi_gicv2m", + test_acpi_aarch64_virt_tcg_msi_gicv2m); qtest_add_func("acpi/virt/numamem", test_acpi_aarch64_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_aarch64_virt_tcg_m= emhp); --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731727; cv=none; d=zohomail.com; s=zohoarc; b=S7JHWXIISbgWfqmCA/q8oIvYVnRxESRaESiWXLiKpyaFpb4swEqgslyy0+lLyZzpu52Wv8at7NwT/BwWqCoa4RRrXB3U8DFePqqdFm54PxgbpHbn0rCTOe3gJxRuTlvbCOhWrCyOzO7Tt0+ORCx8B48J3QYQrL0ueyYFkaKFIow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731727; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=adjSQwHk3KULK9zaYzFCqBvXl4nV3J4QFwlScJUJ8xc=; b=AZs946eH3sKPZbUzmcqu3UTRglILkAndljm1jOa9ec3nRdIHXMm3vv4O0RR+rX6T3tk3t2/HX0rEZD5zwPxNsY7ebmxz8MtdyJJzfmoP5Opa4vqRlSeqL20llzPDHhjJLSh0lU0coLq2sRAmBbbj0AdLDLE+cHe5LJkHUQVbf0A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731727141194.6361548940538; Tue, 10 Feb 2026 05:55:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAD-00026N-O8; Tue, 10 Feb 2026 08:52:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA5-0001zC-NU for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:18 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA4-0006KO-3D for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:17 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4806f3fc50bso47910075e9.0 for ; Tue, 10 Feb 2026 05:52:15 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731534; x=1771336334; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=adjSQwHk3KULK9zaYzFCqBvXl4nV3J4QFwlScJUJ8xc=; b=pj24DzaKM5Tn9WIc9wjzMu3u3wRgkP1ggHGUlqwxMTA6KzQPaX+Rkj7rdbXLFIgp0Y lEEqY1I6bnOsJNeYieNB0vf8l3qFxsJWxWVJQJ2Q6NnGFTnX65uf2yo0vAhXCEs9aTq5 ZXvNkcDOMbaWO80avzirj3zg6hbAjs2FDwfO3a4NnK/N6qLXi3AQ8Tox+NAxQ8wXepAJ 7i7w5LCncRYi5TkGeNy4pjQOgr3R6mJJOR503xwGtDDs88niDURsutWgK+j8wMpXpBzE R2WsYSoSwOQkknILN3XkzRqpljBiUGoOW1ZqL4lPmLrnuTzITEXARlRVXVbDXdhWP4we cLqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731534; x=1771336334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=adjSQwHk3KULK9zaYzFCqBvXl4nV3J4QFwlScJUJ8xc=; b=HV7UdCevBpCXVOTdKYDXDflNbnAcs2L87Stf0OKahqv7mLKLsFP4PpGhV+vP6qL3kv 33r+MfqI6KJxDfM4iJ+JxbrDw4VFUZNOqwL7YzVB1WoxwSPNpUb3hek+YmUFOSoi/GRx S3qTs8ZHdukH9Hza3QM8L5Dr/nKYGTuj3zbKC7EMyJC73eSiXLUfTu7znCQE8B+YOHq4 2xFL2GGcOI4f20qLMChUK1/iu4MlThZIyUlK3AVs5SdT/X9P1G6Mp9dzqBjQOP/4Cdm6 KkAFGaHJSzvmvQ8zVbrL1WEJTIFTXM/5OApzidv+yDyerNzAoB16HduuzW5bvt870obo K5UA== X-Gm-Message-State: AOJu0YwZiIhfGan2thlD8ox9bobxrGkbt+h757yJDNrkoWeqQvuGEVU3 dnM8X9djrobQTtM4TAXmJtMlYR1OvYzSzDRyKWg3NotumhYwaJ6BzcjbaHf6+pPUAcT2eJ70J4E 0xsGa X-Gm-Gg: AZuq6aKkIjXQDojWAFHyROuzumIIeq3mCT4foucOr9weH1dQFKpJmxVRihcCRjglzqU Vx4PYC3ZSSFNdwC/cPVXKd6xzvUCcMZc7+U5bkIhriFNZZwDGf8kTPa4Nk1vhPy8GKmiegLq8OS ub8Fvx19KE5tr/HkUc6hOItYd2VHJvTgY9KdcNrM+XNgoP1I487PoEOK6HpL30Y/CKwd8j7DQ/K 4/o5lac6tpLBJciYtUvlT0Pm5Qq4ebjgc/sA0k9yVqdSK+HpdRTlM56Bquc/s05jbcls2g0Ovcu p4cnTdSrilyU5iwJiQv+gNbNGs9gus7KI6OiqNd/NojTnGAKPgDarCCRv4R4//RRJ2goWM9x8Dj i1j7zf8CIaUoRDmIZ0meFyW4h28k9Kc4Qh8xZdB8oM8zBtS4gGevy45h/PrVbd8PMYCy2E77tjH MevsKorZBJAyHpD5gtAcTqIWERACQoGq38ccAHKM3fFkT+/BavAv7xXZqfW/P9skSwplHGjcAVW tfh4uIx743z2Bxnl3lQNJfJ0h3NGSI= X-Received: by 2002:a05:600c:1e2a:b0:47e:e779:36e with SMTP id 5b1f17b1804b1-48320216170mr193520005e9.19.1770731534513; Tue, 10 Feb 2026 05:52:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/26] docs: arm: update virt machine model description Date: Tue, 10 Feb 2026 13:51:48 +0000 Message-ID: <20260210135206.229528-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731728132154100 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Update the documentation to match current QEMU. Remove the mention of pre-2.7 machine models as those aren't provided anymore. Signed-off-by: Mohamed Mediouni Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index e5570773ba..f8148b5dcf 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -41,9 +41,10 @@ The virt board supports: - User-creatable SMMUv3 devices (see below for example) - hotpluggable DIMMs - hotpluggable NVDIMMs -- An MSI controller (GICv2M or ITS). GICv2M is selected by default along - with GICv2. ITS is selected by default with GICv3 (>=3D virt-2.7). Note - that ITS is not modeled in TCG mode. +- An MSI controller (GICv2m or ITS). + - When using GICv3, ITS is selected by default when available on the pla= tform. + - If using GICv2, a GICv2m is provided by default instead. + - When ITS is not available on a GICv3 platform, a GICv2m is provided by= default. - 32 virtio-mmio transport devices - running guests using the KVM accelerator on aarch64 hardware - large amounts of RAM (at least 255GB, and more if using highmem) @@ -167,9 +168,22 @@ gic-version with TCG this is currently ``3`` if ``virtualization`` is ``off`` and ``4`` if ``virtualization`` is ``on``, but this may change in future) =20 +msi + Specify the MSI and MSI-X controller (GIC) to provide. + Valid values are: + + ``auto`` + Use the best available MSI-X controller option. ITS when supported, GI= Cv2m otherwise. + ``gicv2m`` + GICv2m. Typically used with a GICv2. Also available with a newer GIC. + ``its`` + GICv3 ITS. This is the default option when using a GICv3 or GICv4 with= a supported + accelerator. + ``off`` + Disable support for MSI/MSI-X interrupts. + its - Set ``on``/``off`` to enable/disable ITS instantiation. The default is `= `on`` - for machine types later than ``virt-2.7``. + Set ``on``/``off`` to control ITS instantiation. This is a deprecated op= tion, use ``msi`` instead. =20 iommu Set the IOMMU type to create for the guest. Valid values are: --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731598; cv=none; d=zohomail.com; s=zohoarc; b=jmUxTYUP1cDO/DL606ZVW2QLUpgYAXT/yEz77Mvyp7ja6rqV8Id55Cud2lESb+Yv4VERt47LWIB0O0n+YVEQ92Ln5+uwdGFu2KO6Ue1fLtjXNnZMq+7yeYnK90JSF0uCCqN4aiaYr9QAxCQTh0VheDG1oUP7IIHwHXzzUHwyD8k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731598; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=wHfh+0vLuB+ztlQ1m8l7NlaIrsfeFxV8zm0Rh6FLU2M=; b=KDMnID+CsFBXwNogg9dXeYdXwvxbcGy5ZPYLE2RpFCDKQqjYlfuqCfI5Rp4uGXGl1tgJoAPrJ8jdo7AW1rsA21LZXDfg6D7xUZsu5xZr+QHhf0JlwXX066MsFhJvYWvbHYygVGveKk7eq2F7CCB2BRuJUGDhZXgY4sk9Gp2fl7M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177073159897420.59546663817912; Tue, 10 Feb 2026 05:53:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAD-00022r-1Z; Tue, 10 Feb 2026 08:52:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA7-000207-3Y for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:23 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA5-0006Kf-4n for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:18 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4833115090dso8111935e9.3 for ; Tue, 10 Feb 2026 05:52:16 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731535; x=1771336335; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wHfh+0vLuB+ztlQ1m8l7NlaIrsfeFxV8zm0Rh6FLU2M=; b=DLL7ivZ09gxN/yYYEl9fQclU8k799Ck5rkABhvyL4E53yF62ca8ZBvynkGt3xCFKm2 HQvb0Xruf40qaflcPV+7cdGhjrL2tMbHeWrr4fledrYbqlVciVm9AIlr/ZB8dSgT+JbX wUklBfD/jbu07sL0732vlynV9DdBlp0xmMIJgHW2J8NjlaoG9AGizbvv4DELV7wU7TbV CgnGfw5FTxl9CRIXhjKQyBpZyucGf5wZA3yGRIWURdFacxGCp4WDvHHzszF6YzKJdHRk doFvRatZ/5Aod+kJt90QXCVYadTxjqzz1rZxdysouorzX+hpa9MMnzf1Y0l+sXZ0Jhv5 Gvbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731535; x=1771336335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=wHfh+0vLuB+ztlQ1m8l7NlaIrsfeFxV8zm0Rh6FLU2M=; b=ZXDujfVQXivIqXhpV+wU17UFdEhbqUKO+pCvOgN+zIvs1918iIzaUT4zHJTCUdR6Ou 8a8jAi1NRCVmTMAnE1OyzmyqFmRR4Q/EvT6ouAUQPKMv1PshUKulV5n/P5gPLOgXHMHq gvCgj2oi9geuTrKdm2kxz+SJnt91UCDkD2qyGRSqZGYb5WrOoTrSiFPmGCMq7/6Zybz8 FaVhX62swKllx54O4ceOjyKoaj/CA+zxd/2lWCx4fj94M6oOl6ApAQmjwl3l/jlADz8N SPWbfnZcQzGPNOsw3v84LBRoEvgtnArnNdk5+bhNTFbycIOpFXWDml7iCLBTB76Rs7zX 0D4A== X-Gm-Message-State: AOJu0YxNfn2++ky9BQTWKv1YM6EhnElx5sDAAXW2aYkqRZjG+Vz0UMXT suAOqn54iTrq3YOWsG2NkgNdvr1/r1n5r+StbLk93zW5aesJLj5zYs/M6FDoFWV56kBCiPwd8Pm 4/lFg X-Gm-Gg: AZuq6aIeQ2rv8Ex3WyMBOCtBLpU70QHPQE8sbaTXV0I0Zw0UBZuMhmxUXmDIBo29wr4 Y1OEghucO3hPqKfbzMeyx0HmvS9HAcQjsZ2aDsnQXkefzwMeDfLMb1SoJCN4dt09MwSochnnaL9 F2ac5Wtm0HqG7NUZckb2TQcmEBjuNs/kEqh/5j0AyuYbqlJGo4C0spMjgn4H7qeedELqYfXRvBN ZQmlCf8Zo9eND/3tO0qq3iwJ5kJPuNGEIYAw32SRynqHRDD9gP8eazWBUgp5bG/w/jXerZCGHSO I7t8YdWGS6ieWssiQs8Vk2ZgX7V6Aa21miiZlv0GjIAWLfY0zoGhjspa1hlz+y9enOwPslWNkD1 yQeVwZOiODoH/PAQdz/PpH4O3UTwvUOLZmTsGuiQfhLzIHfxhspFaz9oHMt+a6UP48K1nm3eN+2 +8aKyDsDlwjLsBVTELixJrm7/HIfO2ivYFdJy6u0pE1XBq+k5kH8MXyvYKzjPAbvUrZUc8XCdUI CushxoB4oHbGuNildF6bCAOjvXjQHs= X-Received: by 2002:a05:600c:3e19:b0:483:5310:dc43 with SMTP id 5b1f17b1804b1-4835310ddedmr22807635e9.32.1770731535264; Tue, 10 Feb 2026 05:52:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/26] whpx: Move around files before introducing AArch64 support Date: Tue, 10 Feb 2026 13:51:49 +0000 Message-ID: <20260210135206.229528-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731600196154100 From: Mohamed Mediouni Switch to a design where we can share whpx code between x86 and AArch64 whe= n it makes sense to do so. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- MAINTAINERS | 2 ++ accel/meson.build | 1 + accel/whpx/meson.build | 6 ++++++ {target/i386 =3D> accel}/whpx/whpx-accel-ops.c | 4 ++-- {target/i386/whpx =3D> include/system}/whpx-accel-ops.h | 4 ++-- {target/i386/whpx =3D> include/system}/whpx-internal.h | 6 ++++-- target/i386/whpx/meson.build | 1 - target/i386/whpx/whpx-all.c | 4 ++-- target/i386/whpx/whpx-apic.c | 2 +- 9 files changed, 20 insertions(+), 10 deletions(-) create mode 100644 accel/whpx/meson.build rename {target/i386 =3D> accel}/whpx/whpx-accel-ops.c (97%) rename {target/i386/whpx =3D> include/system}/whpx-accel-ops.h (92%) rename {target/i386/whpx =3D> include/system}/whpx-internal.h (97%) diff --git a/MAINTAINERS b/MAINTAINERS index 29f88d48f3..3a0fe1081a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -564,9 +564,11 @@ WHPX CPUs M: Pedro Barbuda M: Mohamed Mediouni S: Supported +F: accel/whpx/ F: target/i386/whpx/ F: accel/stubs/whpx-stub.c F: include/system/whpx.h +F: include/system/whpx-accel-ops.h =20 MSHV M: Magnus Kulke diff --git a/accel/meson.build b/accel/meson.build index 983dfd0bd5..289b7420ff 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -6,6 +6,7 @@ user_ss.add(files('accel-user.c')) subdir('tcg') if have_system subdir('hvf') + subdir('whpx') subdir('qtest') subdir('kvm') subdir('xen') diff --git a/accel/whpx/meson.build b/accel/whpx/meson.build new file mode 100644 index 0000000000..7b3d6f1c1c --- /dev/null +++ b/accel/whpx/meson.build @@ -0,0 +1,6 @@ +whpx_ss =3D ss.source_set() +whpx_ss.add(files( + 'whpx-accel-ops.c', +)) + +specific_ss.add_all(when: 'CONFIG_WHPX', if_true: whpx_ss) diff --git a/target/i386/whpx/whpx-accel-ops.c b/accel/whpx/whpx-accel-ops.c similarity index 97% rename from target/i386/whpx/whpx-accel-ops.c rename to accel/whpx/whpx-accel-ops.c index f75886128d..c84a25c273 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/accel/whpx/whpx-accel-ops.c @@ -16,8 +16,8 @@ #include "qemu/guest-random.h" =20 #include "system/whpx.h" -#include "whpx-internal.h" -#include "whpx-accel-ops.h" +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" =20 static void *whpx_cpu_thread_fn(void *arg) { diff --git a/target/i386/whpx/whpx-accel-ops.h b/include/system/whpx-accel-= ops.h similarity index 92% rename from target/i386/whpx/whpx-accel-ops.h rename to include/system/whpx-accel-ops.h index 54cfc25a14..ed9d4c49f4 100644 --- a/target/i386/whpx/whpx-accel-ops.h +++ b/include/system/whpx-accel-ops.h @@ -7,8 +7,8 @@ * See the COPYING file in the top-level directory. */ =20 -#ifndef TARGET_I386_WHPX_ACCEL_OPS_H -#define TARGET_I386_WHPX_ACCEL_OPS_H +#ifndef SYSTEM_WHPX_ACCEL_OPS_H +#define SYSTEM_WHPX_ACCEL_OPS_H =20 #include "system/cpus.h" =20 diff --git a/target/i386/whpx/whpx-internal.h b/include/system/whpx-interna= l.h similarity index 97% rename from target/i386/whpx/whpx-internal.h rename to include/system/whpx-internal.h index 2dcad1f565..041fa958b4 100644 --- a/target/i386/whpx/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -1,11 +1,13 @@ -#ifndef TARGET_I386_WHPX_INTERNAL_H -#define TARGET_I386_WHPX_INTERNAL_H +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_INTERNAL_H +#define SYSTEM_WHPX_INTERNAL_H =20 #include #include #include =20 #include "hw/i386/apic.h" +#include "exec/vaddr.h" =20 typedef enum WhpxBreakpointState { WHPX_BP_CLEARED =3D 0, diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build index 9c54aaad39..c3aaaff9fd 100644 --- a/target/i386/whpx/meson.build +++ b/target/i386/whpx/meson.build @@ -1,5 +1,4 @@ i386_system_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-apic.c', - 'whpx-accel-ops.c', )) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index db184e1b0d..cef31fc1a8 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -31,8 +31,8 @@ #include "accel/accel-cpu-target.h" #include =20 -#include "whpx-internal.h" -#include "whpx-accel-ops.h" +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" =20 #include #include diff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c index afcb25843b..b934fdcbe1 100644 --- a/target/i386/whpx/whpx-apic.c +++ b/target/i386/whpx/whpx-apic.c @@ -18,7 +18,7 @@ #include "hw/pci/msi.h" #include "system/hw_accel.h" #include "system/whpx.h" -#include "whpx-internal.h" +#include "system/whpx-internal.h" =20 struct whpx_lapic_state { struct { --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731706; cv=none; d=zohomail.com; s=zohoarc; b=gAGeEGWxZ5VcFNgF88plrnJSkbWmxyKftXVoj6bqWbR6G8C1CQo3HfH7wkPP57Lgy8NA/N6GHDpm4PokjjXpHYORymMctxSc5PPaI3KeDBrFPE2StHmhgWcsh1foI9qor22Mw06R3V5O3dEGgqknTq5chSwBprt12k0TDR4Fxwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731706; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=LHRt76DpiTUXu+oYqus89Ea8WBq2OqReifFSpohvo54=; b=OE7SxPT5iJGpuGWPqiLLPBSx7XeYznjk9wqXYSaYeYAce4jQuZZgLuwFQrq/sVaS4AzgtLIMHtv7LhKfe2QpQvEo69AKckJFAIecCcicj3jugyPb5eXx3oGVFMU8q+RLS3uN8oFNd6jSb+wqspRZs/lNq5p4gZR/GEZNGGlW5e8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731706303651.5330604362548; Tue, 10 Feb 2026 05:55:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAG-0002Aj-Ch; Tue, 10 Feb 2026 08:52:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAB-00021K-HS for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:23 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA6-0006L0-4q for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:21 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4806f3fc50bso47910585e9.0 for ; Tue, 10 Feb 2026 05:52:17 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731536; x=1771336336; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=LHRt76DpiTUXu+oYqus89Ea8WBq2OqReifFSpohvo54=; b=GnlS9FTS4/wEEHr7DvUAjLWgX7fYT1qrH4SNi91usONZJapmr/NGS57aPuCd/jYFu8 Otm7HnUo0Y32Z4iUJhLPOKjjkM9Znb/0mmUAmO1CFTJbZHn6610WEErGCmEYt1TRflrn r8dWujmSIHyMO6RcoHGZgSzDxRDTGQfQMy1nnZyB9zqlvgK+WrsoYxuzNLDaQDsLK40m joeHZwJlWSHgc3j6uraKC5cNNqjmEq+V6N+SSu+fzTkyOiaKK8LblWv5+25iOFJKSfq0 Yn8meMhtqaXGEveEr8ElXGTHnud9Jfp2WbZytg/2DXjnU56rT2dmIh+TDzEt3EbjnaQs APpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731536; x=1771336336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=LHRt76DpiTUXu+oYqus89Ea8WBq2OqReifFSpohvo54=; b=FvkdYk6HpoFUSWOeJuONlEfp7a+41gc5ANbL1aepqipmz44FwYoss7rpnfc0JBrloj zevwp9/v497mLOyU7IaO0YYsjeh+iCmS6e8hAYqi3liBQv+8S1mxGfv9A8ztK7HwYY4u Qti+Kb9riwni9Wvan47br9PFtnN76tLv7xkyNKbgtptLN61Nw3oM/UpEF4ZDmCWX3ii5 Bd47NwItbnseVS9F49NAYJoLKqWJwM2YxFGUz2C+Awcd47QNJ7EfoLgARklxgoxgKBxk yWDsNMTjH14D5ROfdD5tcf7YlmmGqKIsvaeoCpNQ9YCjjebpFx/N/QE8kxEaHf7DpNlm yW+g== X-Gm-Message-State: AOJu0YxEp0mSKcvMtazlkSvjynJ3DnP1FY+QiyD4jc45+TAXbaE1pCVS mPF+lWBAUuNMaepFOKebLMb4xGq4uqEIZ8l/htNypZEM75663mzWfTn9xYwmgU+93X36EwYUQu1 vV15N X-Gm-Gg: AZuq6aJTKoVYLoMOnYFioLtiE+TqmRPW9M/5Mh9dGkyJe+irOjD07u3n95FgrXRkXTj zcW+Fl7xSeg0fPgLigcfGkRb+yZnMUJSELMRTNWKtVD5q2lQq6A6pPxCrDiJ3j2NoPVH/Qbxzd5 +pneqYtP+z/TASjrVnigVlfUea3M3ioJBgy3Y+iAhSZddxS3w9kcJS1A50I/ODqan9SfiJVs+zS oCToglwJVqlvhkS+s1Kuu5/Eg7MyIpSFxtaBDDakWUtA3tF+gN2CtdHzzBNtuukezz3UDkPAL3u CCRJAUzg3QI/OWt3haouiDtQHzsjz5OMF5Kh3Is4U9Gqv2pS0lViVkZXRLsWA4FOhDIjrGw9dEJ w3k4pJi6wodRP5NXJ4aLP5U1pMPAa9fWvOxWs64NBDeB4irL6k7TDfL2IM1U37blnzZCeSuzDbO S8nUWLIDxwBSJyWuqY0L0hwxczqkhH/87Ir/rwS+sHLKR5m0JbDRbUMWbamd+4XCdCt9owjrA1I f4Jm+j15ZTp112NodH/a505bWVXhJM= X-Received: by 2002:a05:600c:19c7:b0:480:1e9e:f9d with SMTP id 5b1f17b1804b1-483201db0bcmr222865225e9.8.1770731536144; Tue, 10 Feb 2026 05:52:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/26] whpx: reshuffle common code Date: Tue, 10 Feb 2026 13:51:50 +0000 Message-ID: <20260210135206.229528-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731708236158500 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Some code can be shared between x86_64 and arm64 WHPX. Do so as much as rea= sonable. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- MAINTAINERS | 2 + accel/whpx/meson.build | 1 + accel/whpx/whpx-common.c | 558 +++++++++++++++++++++++++++++++++++ include/system/whpx-all.h | 20 ++ include/system/whpx-common.h | 21 ++ target/i386/whpx/whpx-all.c | 551 +--------------------------------- 6 files changed, 612 insertions(+), 541 deletions(-) create mode 100644 accel/whpx/whpx-common.c create mode 100644 include/system/whpx-all.h create mode 100644 include/system/whpx-common.h diff --git a/MAINTAINERS b/MAINTAINERS index 3a0fe1081a..54326b1a5a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -569,6 +569,8 @@ F: target/i386/whpx/ F: accel/stubs/whpx-stub.c F: include/system/whpx.h F: include/system/whpx-accel-ops.h +F: include/system/whpx-common.h +F: include/system/whpx-internal.h =20 MSHV M: Magnus Kulke diff --git a/accel/whpx/meson.build b/accel/whpx/meson.build index 7b3d6f1c1c..fad28dddcb 100644 --- a/accel/whpx/meson.build +++ b/accel/whpx/meson.build @@ -1,6 +1,7 @@ whpx_ss =3D ss.source_set() whpx_ss.add(files( 'whpx-accel-ops.c', + 'whpx-common.c' )) =20 specific_ss.add_all(when: 'CONFIG_WHPX', if_true: whpx_ss) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c new file mode 100644 index 0000000000..0a6068fdde --- /dev/null +++ b/accel/whpx/whpx-common.c @@ -0,0 +1,558 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Windows Hypervisor Platform accelerator (WHPX) + * + * Copyright Microsoft Corp. 2017 + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "system/address-spaces.h" +#include "system/ioport.h" +#include "gdbstub/helpers.h" +#include "qemu/accel.h" +#include "accel/accel-ops.h" +#include "system/whpx.h" +#include "system/cpus.h" +#include "system/runstate.h" +#include "qemu/main-loop.h" +#include "hw/core/boards.h" +#include "hw/intc/ioapic.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-types-common.h" +#include "qapi/qapi-visit-common.h" +#include "migration/blocker.h" +#include "accel/accel-cpu-target.h" +#include + +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" +#include "system/whpx-common.h" +#include "system/whpx-all.h" + +#include +#include + +bool whpx_allowed; +static bool whp_dispatch_initialized; +static HMODULE hWinHvPlatform; +static HMODULE hWinHvEmulation; + +struct whpx_state whpx_global; +struct WHPDispatch whp_dispatch; + +/* Tries to find a breakpoint at the specified address. */ +struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address) +{ + struct whpx_state *whpx =3D &whpx_global; + int i; + + if (whpx->breakpoints.breakpoints) { + for (i =3D 0; i < whpx->breakpoints.breakpoints->used; i++) { + if (address =3D=3D whpx->breakpoints.breakpoints->data[i].addr= ess) { + return &whpx->breakpoints.breakpoints->data[i]; + } + } + } + + return NULL; +} + +/* + * This function is called when the a VCPU is about to start and no other + * VCPUs have been started so far. Since the VCPU start order could be + * arbitrary, it doesn't have to be VCPU#0. + * + * It is used to commit the breakpoints into memory, and configure WHPX + * to intercept debug exceptions. + * + * Note that whpx_set_exception_exit_bitmap() cannot be called if one or + * more VCPUs are already running, so this is the best place to do it. + */ +int whpx_first_vcpu_starting(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + + g_assert(bql_locked()); + + if (!QTAILQ_EMPTY(&cpu->breakpoints) || + (whpx->breakpoints.breakpoints && + whpx->breakpoints.breakpoints->used)) { + CPUBreakpoint *bp; + int i =3D 0; + bool update_pending =3D false; + + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + if (i >=3D whpx->breakpoints.original_address_count || + bp->pc !=3D whpx->breakpoints.original_addresses[i]) { + update_pending =3D true; + } + + i++; + } + + if (i !=3D whpx->breakpoints.original_address_count) { + update_pending =3D true; + } + + if (update_pending) { + /* + * The CPU breakpoints have changed since the last call to + * whpx_translate_cpu_breakpoints(). WHPX breakpoints must + * now be recomputed. + */ + whpx_translate_cpu_breakpoints(&whpx->breakpoints, cpu, i); + } + /* Actually insert the breakpoints into the memory. */ + whpx_apply_breakpoints(whpx->breakpoints.breakpoints, cpu, true); + } + HRESULT hr; + uint64_t exception_mask; + if (whpx->step_pending || + (whpx->breakpoints.breakpoints && + whpx->breakpoints.breakpoints->used)) { + /* + * We are either attempting to single-step one or more CPUs, or + * have one or more breakpoints enabled. Both require intercepting + * the WHvX64ExceptionTypeBreakpointTrap exception. + */ + exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; + } else { + /* Let the guest handle all exceptions. */ + exception_mask =3D 0; + } + hr =3D whpx_set_exception_exit_bitmap(exception_mask); + if (!SUCCEEDED(hr)) { + error_report("WHPX: Failed to update exception exit mask," + "hr=3D%08lx.", hr); + return 1; + } + return 0; +} + +/* + * This function is called when the last VCPU has finished running. + * It is used to remove any previously set breakpoints from memory. + */ +int whpx_last_vcpu_stopping(CPUState *cpu) +{ + whpx_apply_breakpoints(whpx_global.breakpoints.breakpoints, cpu, false= ); + return 0; +} + +static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data a= rg) +{ + if (!cpu->vcpu_dirty) { + whpx_get_registers(cpu); + cpu->vcpu_dirty =3D true; + } +} + +static void do_whpx_cpu_synchronize_post_reset(CPUState *cpu, + run_on_cpu_data arg) +{ + whpx_set_registers(cpu, WHPX_SET_RESET_STATE); + cpu->vcpu_dirty =3D false; +} + +static void do_whpx_cpu_synchronize_post_init(CPUState *cpu, + run_on_cpu_data arg) +{ + whpx_set_registers(cpu, WHPX_SET_FULL_STATE); + cpu->vcpu_dirty =3D false; +} + +static void do_whpx_cpu_synchronize_pre_loadvm(CPUState *cpu, + run_on_cpu_data arg) +{ + cpu->vcpu_dirty =3D true; +} + +/* + * CPU support. + */ + +void whpx_cpu_synchronize_state(CPUState *cpu) +{ + if (!cpu->vcpu_dirty) { + run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL); + } +} + +void whpx_cpu_synchronize_post_reset(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); +} + +void whpx_cpu_synchronize_post_init(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_post_init, RUN_ON_CPU_NULL); +} + +void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu) +{ + run_on_cpu(cpu, do_whpx_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); +} + +static void whpx_pre_resume_vm(AccelState *as, bool step_pending) +{ + whpx_global.step_pending =3D step_pending; +} + +/* + * Vcpu support. + */ + +int whpx_vcpu_exec(CPUState *cpu) +{ + int ret; + int fatal; + + for (;;) { + if (cpu->exception_index >=3D EXCP_INTERRUPT) { + ret =3D cpu->exception_index; + cpu->exception_index =3D -1; + break; + } + + fatal =3D whpx_vcpu_run(cpu); + + if (fatal) { + error_report("WHPX: Failed to exec a virtual processor"); + abort(); + } + } + + return ret; +} + +void whpx_destroy_vcpu(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + + whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); + AccelCPUState *vcpu =3D cpu->accel; + whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); + g_free(cpu->accel); +} + + +void whpx_vcpu_kick(CPUState *cpu) +{ + struct whpx_state *whpx =3D &whpx_global; + whp_dispatch.WHvCancelRunVirtualProcessor( + whpx->partition, cpu->cpu_index, 0); +} + +/* + * Memory support. + */ + +static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, + void *host_va, int add, int rom, + const char *name) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + /* + if (add) { + printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", + (void*)start_pa, (void*)size, host_va, + (rom ? "ROM" : "RAM"), name); + } else { + printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", + (void*)start_pa, (void*)size, host_va, name); + } + */ + + if (add) { + hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, + host_va, + start_pa, + size, + (WHvMapGpaRangeFlagRead | + WHvMapGpaRangeFlagExecute | + (rom ? 0 : WHvMapGpaRangeFlagWri= te))); + } else { + hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, + start_pa, + size); + } + + if (FAILED(hr)) { + error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," + " Host:%p, hr=3D%08lx", + (add ? "MAP" : "UNMAP"), name, + (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); + } +} + +static void whpx_process_section(MemoryRegionSection *section, int add) +{ + MemoryRegion *mr =3D section->mr; + hwaddr start_pa =3D section->offset_within_address_space; + ram_addr_t size =3D int128_get64(section->size); + unsigned int delta; + uint64_t host_va; + + if (!memory_region_is_ram(mr)) { + return; + } + + delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); + delta &=3D ~qemu_real_host_page_mask(); + if (delta > size) { + return; + } + start_pa +=3D delta; + size -=3D delta; + size &=3D qemu_real_host_page_mask(); + if (!size || (start_pa & ~qemu_real_host_page_mask())) { + return; + } + + host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) + + section->offset_within_region + delta; + + whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, + memory_region_is_rom(mr), mr->name); +} + +static void whpx_region_add(MemoryListener *listener, + MemoryRegionSection *section) +{ + memory_region_ref(section->mr); + whpx_process_section(section, 1); +} + +static void whpx_region_del(MemoryListener *listener, + MemoryRegionSection *section) +{ + whpx_process_section(section, 0); + memory_region_unref(section->mr); +} + +static void whpx_transaction_begin(MemoryListener *listener) +{ +} + +static void whpx_transaction_commit(MemoryListener *listener) +{ +} + +static void whpx_log_sync(MemoryListener *listener, + MemoryRegionSection *section) +{ + MemoryRegion *mr =3D section->mr; + + if (!memory_region_is_ram(mr)) { + return; + } + + memory_region_set_dirty(mr, 0, int128_get64(section->size)); +} + +static MemoryListener whpx_memory_listener =3D { + .name =3D "whpx", + .begin =3D whpx_transaction_begin, + .commit =3D whpx_transaction_commit, + .region_add =3D whpx_region_add, + .region_del =3D whpx_region_del, + .log_sync =3D whpx_log_sync, + .priority =3D MEMORY_LISTENER_PRIORITY_ACCEL, +}; + +void whpx_memory_init(void) +{ + memory_listener_register(&whpx_memory_listener, &address_space_memory); +} + +/* + * Load the functions from the given library, using the given handle. If a + * handle is provided, it is used, otherwise the library is opened. The + * handle will be updated on return with the opened one. + */ +static bool load_whp_dispatch_fns(HMODULE *handle, + WHPFunctionList function_list) +{ + HMODULE hLib =3D *handle; + + #define WINHV_PLATFORM_DLL "WinHvPlatform.dll" + #define WINHV_EMULATION_DLL "WinHvEmulation.dll" + #define WHP_LOAD_FIELD_OPTIONAL(return_type, function_name, signature)= \ + whp_dispatch.function_name =3D \ + (function_name ## _t)GetProcAddress(hLib, #function_name); \ + + #define WHP_LOAD_FIELD(return_type, function_name, signature) \ + whp_dispatch.function_name =3D \ + (function_name ## _t)GetProcAddress(hLib, #function_name); \ + if (!whp_dispatch.function_name) { \ + error_report("Could not load function %s", #function_name); \ + goto error; \ + } \ + + #define WHP_LOAD_LIB(lib_name, handle_lib) \ + if (!handle_lib) { \ + handle_lib =3D LoadLibrary(lib_name); \ + if (!handle_lib) { \ + error_report("Could not load library %s.", lib_name); \ + goto error; \ + } \ + } \ + + switch (function_list) { + case WINHV_PLATFORM_FNS_DEFAULT: + WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) + LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) + break; + case WINHV_EMULATION_FNS_DEFAULT: + WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) + LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) + break; + case WINHV_PLATFORM_FNS_SUPPLEMENTAL: + WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) + LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_LOAD_FIELD_OPTIONAL) + break; + } + + *handle =3D hLib; + return true; + +error: + if (hLib) { + FreeLibrary(hLib); + } + + return false; +} + +static void whpx_set_kernel_irqchip(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + struct whpx_state *whpx =3D &whpx_global; + OnOffSplit mode; + + if (!visit_type_OnOffSplit(v, name, &mode, errp)) { + return; + } + + switch (mode) { + case ON_OFF_SPLIT_ON: + whpx->kernel_irqchip_allowed =3D true; + whpx->kernel_irqchip_required =3D true; + break; + + case ON_OFF_SPLIT_OFF: + whpx->kernel_irqchip_allowed =3D false; + whpx->kernel_irqchip_required =3D false; + break; + + case ON_OFF_SPLIT_SPLIT: + error_setg(errp, "WHPX: split irqchip currently not supported"); + error_append_hint(errp, + "Try without kernel-irqchip or with kernel-irqchip=3Don|off"); + break; + + default: + /* + * The value was checked in visit_type_OnOffSplit() above. If + * we get here, then something is wrong in QEMU. + */ + abort(); + } +} + +static void whpx_cpu_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D whpx_cpu_instance_init; +} + +static const TypeInfo whpx_cpu_accel_type =3D { + .name =3D ACCEL_CPU_NAME("whpx"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D whpx_cpu_accel_class_init, + .abstract =3D true, +}; + +/* + * Partition support + */ + +bool whpx_apic_in_platform(void) +{ + return whpx_global.apic_in_platform; +} + +static void whpx_accel_class_init(ObjectClass *oc, const void *data) +{ + AccelClass *ac =3D ACCEL_CLASS(oc); + ac->name =3D "WHPX"; + ac->init_machine =3D whpx_accel_init; + ac->pre_resume_vm =3D whpx_pre_resume_vm; + ac->allowed =3D &whpx_allowed; + + object_class_property_add(oc, "kernel-irqchip", "on|off|split", + NULL, whpx_set_kernel_irqchip, + NULL, NULL); + object_class_property_set_description(oc, "kernel-irqchip", + "Configure WHPX in-kernel irqchip"); +} + +static void whpx_accel_instance_init(Object *obj) +{ + struct whpx_state *whpx =3D &whpx_global; + + memset(whpx, 0, sizeof(struct whpx_state)); + /* Turn on kernel-irqchip, by default */ + whpx->kernel_irqchip_allowed =3D true; +} + +static const TypeInfo whpx_accel_type =3D { + .name =3D ACCEL_CLASS_NAME("whpx"), + .parent =3D TYPE_ACCEL, + .instance_init =3D whpx_accel_instance_init, + .class_init =3D whpx_accel_class_init, +}; + +static void whpx_type_init(void) +{ + type_register_static(&whpx_accel_type); + type_register_static(&whpx_cpu_accel_type); +} + +bool init_whp_dispatch(void) +{ + if (whp_dispatch_initialized) { + return true; + } + + if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { + goto error; + } + + if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { + goto error; + } + + assert(load_whp_dispatch_fns(&hWinHvPlatform, + WINHV_PLATFORM_FNS_SUPPLEMENTAL)); + whp_dispatch_initialized =3D true; + + return true; +error: + if (hWinHvPlatform) { + FreeLibrary(hWinHvPlatform); + } + if (hWinHvEmulation) { + FreeLibrary(hWinHvEmulation); + } + return false; +} + +type_init(whpx_type_init); diff --git a/include/system/whpx-all.h b/include/system/whpx-all.h new file mode 100644 index 0000000000..f13cdf7f66 --- /dev/null +++ b/include/system/whpx-all.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_ALL_H +#define SYSTEM_WHPX_ALL_H + +/* Called by whpx-common */ +int whpx_vcpu_run(CPUState *cpu); +void whpx_get_registers(CPUState *cpu); +void whpx_set_registers(CPUState *cpu, int level); +int whpx_accel_init(AccelState *as, MachineState *ms); +void whpx_cpu_instance_init(CPUState *cs); +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions); +void whpx_apply_breakpoints( +struct whpx_breakpoint_collection *breakpoints, + CPUState *cpu, + bool resuming); +void whpx_translate_cpu_breakpoints( + struct whpx_breakpoints *breakpoints, + CPUState *cpu, + int cpu_breakpoint_count); +#endif diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h new file mode 100644 index 0000000000..e549c7539c --- /dev/null +++ b/include/system/whpx-common.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef SYSTEM_WHPX_COMMON_H +#define SYSTEM_WHPX_COMMON_H + +struct AccelCPUState { + WHV_EMULATOR_HANDLE emulator; + bool window_registered; + bool interruptable; + bool ready_for_pic_interrupt; + uint64_t tpr; + uint64_t apic_base; + bool interruption_pending; + /* Must be the last field as it may have a tail */ + WHV_RUN_VP_EXIT_CONTEXT exit_ctx; +}; + +int whpx_first_vcpu_starting(CPUState *cpu); +int whpx_last_vcpu_stopping(CPUState *cpu); +void whpx_memory_init(void); +struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address); +#endif diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index cef31fc1a8..052cda42bf 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -33,6 +33,8 @@ =20 #include "system/whpx-internal.h" #include "system/whpx-accel-ops.h" +#include "system/whpx-all.h" +#include "system/whpx-common.h" =20 #include #include @@ -232,28 +234,9 @@ typedef enum WhpxStepMode { WHPX_STEP_EXCLUSIVE, } WhpxStepMode; =20 -struct AccelCPUState { - WHV_EMULATOR_HANDLE emulator; - bool window_registered; - bool interruptable; - bool ready_for_pic_interrupt; - uint64_t tpr; - uint64_t apic_base; - bool interruption_pending; - - /* Must be the last field as it may have a tail */ - WHV_RUN_VP_EXIT_CONTEXT exit_ctx; -}; - -bool whpx_allowed; -static bool whp_dispatch_initialized; -static HMODULE hWinHvPlatform, hWinHvEmulation; static uint32_t max_vcpu_index; static WHV_PROCESSOR_XSAVE_FEATURES whpx_xsave_cap; =20 -struct whpx_state whpx_global; -struct WHPDispatch whp_dispatch; - static bool whpx_has_xsave(void) { return whpx_xsave_cap.XsaveSupport; @@ -379,7 +362,7 @@ static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8) return cr8 << 4; } =20 -static void whpx_set_registers(CPUState *cpu, int level) +void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; @@ -594,7 +577,7 @@ static void whpx_get_xcrs(CPUState *cpu) cpu_env(cpu)->xcr0 =3D xcr0.Reg64; } =20 -static void whpx_get_registers(CPUState *cpu) +void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; @@ -934,7 +917,7 @@ static int whpx_handle_portio(CPUState *cpu, * The 'exceptions' argument accepts a bitmask, e.g: * (1 << WHvX64ExceptionTypeDebugTrapOrFault) | (...) */ -static HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) { struct whpx_state *whpx =3D &whpx_global; WHV_PARTITION_PROPERTY prop =3D { 0, }; @@ -1084,23 +1067,6 @@ static HRESULT whpx_vcpu_configure_single_stepping(C= PUState *cpu, return S_OK; } =20 -/* Tries to find a breakpoint at the specified address. */ -static struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t add= ress) -{ - struct whpx_state *whpx =3D &whpx_global; - int i; - - if (whpx->breakpoints.breakpoints) { - for (i =3D 0; i < whpx->breakpoints.breakpoints->used; i++) { - if (address =3D=3D whpx->breakpoints.breakpoints->data[i].addr= ess) { - return &whpx->breakpoints.breakpoints->data[i]; - } - } - } - - return NULL; -} - /* * Linux uses int3 (0xCC) during startup (see int3_selftest()) and for * debugging user-mode applications. Since the WHPX API does not offer @@ -1136,7 +1102,7 @@ static const uint8_t whpx_breakpoint_instruction =3D = 0xF1; * memory, but doesn't actually do it. The memory accessing is done in * whpx_apply_breakpoints(). */ -static void whpx_translate_cpu_breakpoints( +void whpx_translate_cpu_breakpoints( struct whpx_breakpoints *breakpoints, CPUState *cpu, int cpu_breakpoint_count) @@ -1230,7 +1196,7 @@ static void whpx_translate_cpu_breakpoints( * Passing resuming=3Dtrue will try to set all previously unset breakpoin= ts. * Passing resuming=3Dfalse will remove all inserted ones. */ -static void whpx_apply_breakpoints( +void whpx_apply_breakpoints( struct whpx_breakpoint_collection *breakpoints, CPUState *cpu, bool resuming) @@ -1306,93 +1272,6 @@ static void whpx_apply_breakpoints( } } =20 -/* - * This function is called when the a VCPU is about to start and no other - * VCPUs have been started so far. Since the VCPU start order could be - * arbitrary, it doesn't have to be VCPU#0. - * - * It is used to commit the breakpoints into memory, and configure WHPX - * to intercept debug exceptions. - * - * Note that whpx_set_exception_exit_bitmap() cannot be called if one or - * more VCPUs are already running, so this is the best place to do it. - */ -static int whpx_first_vcpu_starting(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - HRESULT hr; - - g_assert(bql_locked()); - - if (!QTAILQ_EMPTY(&cpu->breakpoints) || - (whpx->breakpoints.breakpoints && - whpx->breakpoints.breakpoints->used)) { - CPUBreakpoint *bp; - int i =3D 0; - bool update_pending =3D false; - - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (i >=3D whpx->breakpoints.original_address_count || - bp->pc !=3D whpx->breakpoints.original_addresses[i]) { - update_pending =3D true; - } - - i++; - } - - if (i !=3D whpx->breakpoints.original_address_count) { - update_pending =3D true; - } - - if (update_pending) { - /* - * The CPU breakpoints have changed since the last call to - * whpx_translate_cpu_breakpoints(). WHPX breakpoints must - * now be recomputed. - */ - whpx_translate_cpu_breakpoints(&whpx->breakpoints, cpu, i); - } - - /* Actually insert the breakpoints into the memory. */ - whpx_apply_breakpoints(whpx->breakpoints.breakpoints, cpu, true); - } - - uint64_t exception_mask; - if (whpx->step_pending || - (whpx->breakpoints.breakpoints && - whpx->breakpoints.breakpoints->used)) { - /* - * We are either attempting to single-step one or more CPUs, or - * have one or more breakpoints enabled. Both require intercepting - * the WHvX64ExceptionTypeBreakpointTrap exception. - */ - - exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; - } else { - /* Let the guest handle all exceptions. */ - exception_mask =3D 0; - } - - hr =3D whpx_set_exception_exit_bitmap(exception_mask); - if (!SUCCEEDED(hr)) { - error_report("WHPX: Failed to update exception exit mask," - "hr=3D%08lx.", hr); - return 1; - } - - return 0; -} - -/* - * This function is called when the last VCPU has finished running. - * It is used to remove any previously set breakpoints from memory. - */ -static int whpx_last_vcpu_stopping(CPUState *cpu) -{ - whpx_apply_breakpoints(whpx_global.breakpoints.breakpoints, cpu, false= ); - return 0; -} - /* Returns the address of the next instruction that is about to be execute= d. */ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exit_context_valid) { @@ -1634,7 +1513,7 @@ static void whpx_vcpu_process_async_events(CPUState *= cpu) } } =20 -static int whpx_vcpu_run(CPUState *cpu) +int whpx_vcpu_run(CPUState *cpu) { HRESULT hr; struct whpx_state *whpx =3D &whpx_global; @@ -2057,65 +1936,6 @@ static int whpx_vcpu_run(CPUState *cpu) return ret < 0; } =20 -static void do_whpx_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data a= rg) -{ - if (!cpu->vcpu_dirty) { - whpx_get_registers(cpu); - cpu->vcpu_dirty =3D true; - } -} - -static void do_whpx_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) -{ - whpx_set_registers(cpu, WHPX_SET_RESET_STATE); - cpu->vcpu_dirty =3D false; -} - -static void do_whpx_cpu_synchronize_post_init(CPUState *cpu, - run_on_cpu_data arg) -{ - whpx_set_registers(cpu, WHPX_SET_FULL_STATE); - cpu->vcpu_dirty =3D false; -} - -static void do_whpx_cpu_synchronize_pre_loadvm(CPUState *cpu, - run_on_cpu_data arg) -{ - cpu->vcpu_dirty =3D true; -} - -/* - * CPU support. - */ - -void whpx_cpu_synchronize_state(CPUState *cpu) -{ - if (!cpu->vcpu_dirty) { - run_on_cpu(cpu, do_whpx_cpu_synchronize_state, RUN_ON_CPU_NULL); - } -} - -void whpx_cpu_synchronize_post_reset(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -void whpx_cpu_synchronize_post_init(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -void whpx_cpu_synchronize_pre_loadvm(CPUState *cpu) -{ - run_on_cpu(cpu, do_whpx_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); -} - -static void whpx_pre_resume_vm(AccelState *as, bool step_pending) -{ - whpx_global.step_pending =3D step_pending; -} - /* * Vcpu support. */ @@ -2244,295 +2064,18 @@ error: return ret; } =20 -int whpx_vcpu_exec(CPUState *cpu) -{ - int ret; - int fatal; - - for (;;) { - if (cpu->exception_index >=3D EXCP_INTERRUPT) { - ret =3D cpu->exception_index; - cpu->exception_index =3D -1; - break; - } - - fatal =3D whpx_vcpu_run(cpu); - - if (fatal) { - error_report("WHPX: Failed to exec a virtual processor"); - abort(); - } - } - - return ret; -} - -void whpx_destroy_vcpu(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - AccelCPUState *vcpu =3D cpu->accel; - - whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); - whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); - g_free(cpu->accel); -} - -void whpx_vcpu_kick(CPUState *cpu) -{ - struct whpx_state *whpx =3D &whpx_global; - whp_dispatch.WHvCancelRunVirtualProcessor( - whpx->partition, cpu->cpu_index, 0); -} - -/* - * Memory support. - */ - -static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, - void *host_va, int add, int rom, - const char *name) -{ - struct whpx_state *whpx =3D &whpx_global; - HRESULT hr; - - /* - if (add) { - printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", - (void*)start_pa, (void*)size, host_va, - (rom ? "ROM" : "RAM"), name); - } else { - printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", - (void*)start_pa, (void*)size, host_va, name); - } - */ - - if (add) { - hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, - host_va, - start_pa, - size, - (WHvMapGpaRangeFlagRead | - WHvMapGpaRangeFlagExecute | - (rom ? 0 : WHvMapGpaRangeFlagWri= te))); - } else { - hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, - start_pa, - size); - } - - if (FAILED(hr)) { - error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," - " Host:%p, hr=3D%08lx", - (add ? "MAP" : "UNMAP"), name, - (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); - } -} - -static void whpx_process_section(MemoryRegionSection *section, int add) -{ - MemoryRegion *mr =3D section->mr; - hwaddr start_pa =3D section->offset_within_address_space; - ram_addr_t size =3D int128_get64(section->size); - unsigned int delta; - uint64_t host_va; - - if (!memory_region_is_ram(mr)) { - return; - } - - delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); - delta &=3D ~qemu_real_host_page_mask(); - if (delta > size) { - return; - } - start_pa +=3D delta; - size -=3D delta; - size &=3D qemu_real_host_page_mask(); - if (!size || (start_pa & ~qemu_real_host_page_mask())) { - return; - } - - host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) - + section->offset_within_region + delta; - - whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, - memory_region_is_rom(mr), mr->name); -} - -static void whpx_region_add(MemoryListener *listener, - MemoryRegionSection *section) -{ - memory_region_ref(section->mr); - whpx_process_section(section, 1); -} - -static void whpx_region_del(MemoryListener *listener, - MemoryRegionSection *section) -{ - whpx_process_section(section, 0); - memory_region_unref(section->mr); -} - -static void whpx_transaction_begin(MemoryListener *listener) -{ -} - -static void whpx_transaction_commit(MemoryListener *listener) -{ -} - -static void whpx_log_sync(MemoryListener *listener, - MemoryRegionSection *section) -{ - MemoryRegion *mr =3D section->mr; - - if (!memory_region_is_ram(mr)) { - return; - } - - memory_region_set_dirty(mr, 0, int128_get64(section->size)); -} - -static MemoryListener whpx_memory_listener =3D { - .name =3D "whpx", - .begin =3D whpx_transaction_begin, - .commit =3D whpx_transaction_commit, - .region_add =3D whpx_region_add, - .region_del =3D whpx_region_del, - .log_sync =3D whpx_log_sync, - .priority =3D MEMORY_LISTENER_PRIORITY_ACCEL, -}; - -static void whpx_memory_init(void) -{ - memory_listener_register(&whpx_memory_listener, &address_space_memory); -} - -/* - * Load the functions from the given library, using the given handle. If a - * handle is provided, it is used, otherwise the library is opened. The - * handle will be updated on return with the opened one. - */ -static bool load_whp_dispatch_fns(HMODULE *handle, - WHPFunctionList function_list) -{ - HMODULE hLib =3D *handle; - - #define WINHV_PLATFORM_DLL "WinHvPlatform.dll" - #define WINHV_EMULATION_DLL "WinHvEmulation.dll" - #define WHP_LOAD_FIELD_OPTIONAL(return_type, function_name, signature)= \ - whp_dispatch.function_name =3D \ - (function_name ## _t)GetProcAddress(hLib, #function_name); \ - - #define WHP_LOAD_FIELD(return_type, function_name, signature) \ - whp_dispatch.function_name =3D \ - (function_name ## _t)GetProcAddress(hLib, #function_name); \ - if (!whp_dispatch.function_name) { \ - error_report("Could not load function %s", #function_name); \ - goto error; \ - } \ - - #define WHP_LOAD_LIB(lib_name, handle_lib) \ - if (!handle_lib) { \ - handle_lib =3D LoadLibrary(lib_name); \ - if (!handle_lib) { \ - error_report("Could not load library %s.", lib_name); \ - goto error; \ - } \ - } \ - - switch (function_list) { - case WINHV_PLATFORM_FNS_DEFAULT: - WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) - LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) - break; - - case WINHV_EMULATION_FNS_DEFAULT: - WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) - LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) - break; - - case WINHV_PLATFORM_FNS_SUPPLEMENTAL: - WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) - LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_LOAD_FIELD_OPTIONAL) - break; - } - - *handle =3D hLib; - return true; - -error: - if (hLib) { - FreeLibrary(hLib); - } - - return false; -} - -static void whpx_set_kernel_irqchip(Object *obj, Visitor *v, - const char *name, void *opaque, - Error **errp) -{ - struct whpx_state *whpx =3D &whpx_global; - OnOffSplit mode; - - if (!visit_type_OnOffSplit(v, name, &mode, errp)) { - return; - } - - switch (mode) { - case ON_OFF_SPLIT_ON: - whpx->kernel_irqchip_allowed =3D true; - whpx->kernel_irqchip_required =3D true; - break; - - case ON_OFF_SPLIT_OFF: - whpx->kernel_irqchip_allowed =3D false; - whpx->kernel_irqchip_required =3D false; - break; - - case ON_OFF_SPLIT_SPLIT: - error_setg(errp, "WHPX: split irqchip currently not supported"); - error_append_hint(errp, - "Try without kernel-irqchip or with kernel-irqchip=3Don|off"); - break; - - default: - /* - * The value was checked in visit_type_OnOffSplit() above. If - * we get here, then something is wrong in QEMU. - */ - abort(); - } -} - -static void whpx_cpu_instance_init(CPUState *cs) +void whpx_cpu_instance_init(CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 host_cpu_instance_init(cpu); } =20 -static void whpx_cpu_accel_class_init(ObjectClass *oc, const void *data) -{ - AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); - - acc->cpu_instance_init =3D whpx_cpu_instance_init; -} - -static const TypeInfo whpx_cpu_accel_type =3D { - .name =3D ACCEL_CPU_NAME("whpx"), - - .parent =3D TYPE_ACCEL_CPU, - .class_init =3D whpx_cpu_accel_class_init, - .abstract =3D true, -}; - /* * Partition support */ =20 -static int whpx_accel_init(AccelState *as, MachineState *ms) +int whpx_accel_init(AccelState *as, MachineState *ms) { struct whpx_state *whpx; int ret; @@ -2715,77 +2258,3 @@ error: =20 return ret; } - -bool whpx_apic_in_platform(void) { - return whpx_global.apic_in_platform; -} - -static void whpx_accel_class_init(ObjectClass *oc, const void *data) -{ - AccelClass *ac =3D ACCEL_CLASS(oc); - ac->name =3D "WHPX"; - ac->init_machine =3D whpx_accel_init; - ac->pre_resume_vm =3D whpx_pre_resume_vm; - ac->allowed =3D &whpx_allowed; - - object_class_property_add(oc, "kernel-irqchip", "on|off|split", - NULL, whpx_set_kernel_irqchip, - NULL, NULL); - object_class_property_set_description(oc, "kernel-irqchip", - "Configure WHPX in-kernel irqchip"); -} - -static void whpx_accel_instance_init(Object *obj) -{ - struct whpx_state *whpx =3D &whpx_global; - - memset(whpx, 0, sizeof(struct whpx_state)); - /* Turn on kernel-irqchip, by default */ - whpx->kernel_irqchip_allowed =3D true; -} - -static const TypeInfo whpx_accel_type =3D { - .name =3D ACCEL_CLASS_NAME("whpx"), - .parent =3D TYPE_ACCEL, - .instance_init =3D whpx_accel_instance_init, - .class_init =3D whpx_accel_class_init, -}; - -static void whpx_type_init(void) -{ - type_register_static(&whpx_accel_type); - type_register_static(&whpx_cpu_accel_type); -} - -bool init_whp_dispatch(void) -{ - if (whp_dispatch_initialized) { - return true; - } - - if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { - goto error; - } - - if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { - goto error; - } - - assert(load_whp_dispatch_fns(&hWinHvPlatform, - WINHV_PLATFORM_FNS_SUPPLEMENTAL)); - whp_dispatch_initialized =3D true; - - return true; -error: - if (hWinHvPlatform) { - FreeLibrary(hWinHvPlatform); - } - - if (hWinHvEmulation) { - FreeLibrary(hWinHvEmulation); - } - - return false; -} - -type_init(whpx_type_init); --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731703; cv=none; d=zohomail.com; s=zohoarc; b=fyxhtgiX6bBAKUFdS2Wmi0Q9t8816iyKjQJq2dPG1yy9hvRDB9uY7Mvg2ZPWQEVzFOE6ItpWLWgtxZx1GzxmxYBiS1nSUV5vYQEApfdBqHAJX641aq40BpaeM7+bpdc2AehHY7K9zOqpaw1duymBdHkDaqcJCZdT85ZbIo9AlJE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731703; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IM/zaN3DN3FDZg2qGJSyS3KoNBrzk/mO9OYYTNEvs3Q=; b=S24+ycYEa1XZ9rzTCPtigTBDpXeUGffrMzWsmSidTRjZFMb+48vORNgnAtwAI+CTfPVHKEGth9Rf9c20k5uNJVdsDDZWCFnm11MXM02/wz85lLS7ZzNFIcq7VD1LsdWOj5T3Yv+2mO5fK0vJB1Lx/9Gm0XP9qqlrL9mbVjzTlr0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177073170360381.20388666261158; Tue, 10 Feb 2026 05:55:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAE-00028S-OI; Tue, 10 Feb 2026 08:52:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoA8-00020L-CW for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:23 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA6-0006LC-Fz for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:20 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-47edd6111b4so82574115e9.1 for ; Tue, 10 Feb 2026 05:52:18 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731537; x=1771336337; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IM/zaN3DN3FDZg2qGJSyS3KoNBrzk/mO9OYYTNEvs3Q=; b=tws5eV5d6jd17tvoUn/cKBFMcP68LSePWK+/+xUY8ES6rXnuCISSl3LS7Ga6MiTXnM 4KAy3TjZ9gMIFFzxrBtkpn7O1TwKIo3zXIQagyz4Pd8nnsaY4IQwOLaDhYOKdFyAHzV/ FusyZgASpsRYN4llxamMT6xxMjkhCNt9UV2U68HyAuQzC81ruwi8HiI0NipsXnsK/i1J 8IM5OeTch8WbVP39CdbJkvqtOTTZ3GEE1V3XS2Kh8iGFobFUlBaOiHVsH5E5Beno78eo d24Ui628/IaqP4vUVd3oNQU0hyHewZAe6PAE3DgemS1g3nL/0O8HGNq45V3qeYL331Mv Ltyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731537; x=1771336337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=IM/zaN3DN3FDZg2qGJSyS3KoNBrzk/mO9OYYTNEvs3Q=; b=tt5wThod1cW5HDh82m9rFftI9hS2POQaFg8j7mcNLYbGL2jwFMLxZQnmX48ssR7xMM cnJdLezz3/KPi+zmJMo5RNT181vvT0yot/8eJ2e/NDP43qUldZc65Lv6z8BVcbSYEqKy +2q53CLIWyRv11b+PptrTUUeGsLZa5vKGkYlPYJRjT55L4zXDoWMfGw86+AUb6WzILUS 2u7IOmCqGL1wEWR9I4DgMa8fXPX4eCxbsVUgNLDD0IRNOVr7N0XbeUCWQoLYDSZexXz8 N43TlUklqH6GRltoljptfm3tvjInTkD4DD3DQ6g2l3kLVCueguJl83aIy+cLuQiQn+jP D/5g== X-Gm-Message-State: AOJu0YyABzjQdz0UzKZiDOt1XUPWLvywVv/blWj4Q//waCMIKyYYhxIg kXx2ANRyq6AYbK8peos9fQ1Kh7nA3DwbLJLZQm61reubP6luh7TbChRQqYiDAEe2YC2EdWQpUMn 6WE2K X-Gm-Gg: AZuq6aIsppRN+V94gzwvU0Hi/dhocOuIvJK2Sf1huwF2jsJ6gOGMI0PRRXLVu3IpB8H vOp4CfpN0FqMPScOt2yxinMKPuoyOfiKCHnj71BDv8bmcu0F7l+zK+6HvucufqVYRwnJKNpw6BK dsU3OSHXEWojfyRM8FRhBQoB84BrWY9BAqaZ8BlMTfkcKXImJZuB1WOzxmT2ePWgNIQ/+/Aswdx 3+zOyyKQyHLSfBDm1frcW8k/0h7JpOk0NmYbr5bilua3oB3EoC23L+TPo2GU8r9aVyr53WC+X83 /U1IglLt17isDYxc1MsAqDhmSRUKXgU+KY0vlevujPpQ3qquAFbTrU/YWXU9uFAVtgPSa1btJr/ NRAKCIUWcjGKXhOkJNXzO2/F3KULSKWIkKcNC1NpkG2uB9jAzCvmIEKVIpmA/rJjlklaUJ1Eh7X fGM9aX+cm27GpO6lvN1XrhyuXkOcpNETLlYM+v/EuOaplkfF0l08LgjRIiw9rnO4ow9v1INev7p Z3TUsAEtUf8QjOK1R4Y0Ld/ZB2YT6w= X-Received: by 2002:a05:600c:3487:b0:47d:3690:7490 with SMTP id 5b1f17b1804b1-483507e16b1mr32351755e9.9.1770731536966; Tue, 10 Feb 2026 05:52:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/26] whpx: ifdef out winhvemulation on non-x86_64 Date: Tue, 10 Feb 2026 13:51:51 +0000 Message-ID: <20260210135206.229528-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731704129158500 From: Mohamed Mediouni winhvemulation is x86_64 only. In the future, we might want to get rid of winhvemulation usage entirely. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- accel/whpx/whpx-common.c | 14 ++++++++++++-- include/system/whpx-common.h | 2 ++ include/system/whpx-internal.h | 7 ++++++- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 0a6068fdde..c58344cb61 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -37,7 +37,9 @@ bool whpx_allowed; static bool whp_dispatch_initialized; static HMODULE hWinHvPlatform; +#ifdef HOST_X86_64 static HMODULE hWinHvEmulation; +#endif =20 struct whpx_state whpx_global; struct WHPDispatch whp_dispatch; @@ -232,8 +234,10 @@ void whpx_destroy_vcpu(CPUState *cpu) struct whpx_state *whpx =3D &whpx_global; =20 whp_dispatch.WHvDeleteVirtualProcessor(whpx->partition, cpu->cpu_index= ); +#ifdef HOST_X86_64 AccelCPUState *vcpu =3D cpu->accel; whp_dispatch.WHvEmulatorDestroyEmulator(vcpu->emulator); +#endif g_free(cpu->accel); } =20 @@ -408,8 +412,12 @@ static bool load_whp_dispatch_fns(HMODULE *handle, LIST_WINHVPLATFORM_FUNCTIONS(WHP_LOAD_FIELD) break; case WINHV_EMULATION_FNS_DEFAULT: +#ifdef HOST_X86_64 WHP_LOAD_LIB(WINHV_EMULATION_DLL, hLib) LIST_WINHVEMULATION_FUNCTIONS(WHP_LOAD_FIELD) +#else + g_assert_not_reached(); +#endif break; case WINHV_PLATFORM_FNS_SUPPLEMENTAL: WHP_LOAD_LIB(WINHV_PLATFORM_DLL, hLib) @@ -535,11 +543,11 @@ bool init_whp_dispatch(void) if (!load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_DEFAULT= )) { goto error; } - +#ifdef HOST_X86_64 if (!load_whp_dispatch_fns(&hWinHvEmulation, WINHV_EMULATION_FNS_DEFAU= LT)) { goto error; } - +#endif assert(load_whp_dispatch_fns(&hWinHvPlatform, WINHV_PLATFORM_FNS_SUPPLEMENTAL)); whp_dispatch_initialized =3D true; @@ -549,9 +557,11 @@ error: if (hWinHvPlatform) { FreeLibrary(hWinHvPlatform); } +#ifdef HOST_X86_64 if (hWinHvEmulation) { FreeLibrary(hWinHvEmulation); } +#endif return false; } =20 diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h index e549c7539c..8f171d1397 100644 --- a/include/system/whpx-common.h +++ b/include/system/whpx-common.h @@ -3,7 +3,9 @@ #define SYSTEM_WHPX_COMMON_H =20 struct AccelCPUState { +#ifdef HOST_X86_64 WHV_EMULATOR_HANDLE emulator; +#endif bool window_registered; bool interruptable; bool ready_for_pic_interrupt; diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 041fa958b4..609d0e1c08 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -4,8 +4,9 @@ =20 #include #include +#ifdef HOST_X86_64 #include - +#endif #include "hw/i386/apic.h" #include "exec/vaddr.h" =20 @@ -101,12 +102,16 @@ void whpx_apic_get(APICCommonState *s); =20 /* Define function typedef */ LIST_WINHVPLATFORM_FUNCTIONS(WHP_DEFINE_TYPE) +#ifdef HOST_X86_64 LIST_WINHVEMULATION_FUNCTIONS(WHP_DEFINE_TYPE) +#endif LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_DEFINE_TYPE) =20 struct WHPDispatch { LIST_WINHVPLATFORM_FUNCTIONS(WHP_DECLARE_MEMBER) +#ifdef HOST_X86_64 LIST_WINHVEMULATION_FUNCTIONS(WHP_DECLARE_MEMBER) +#endif LIST_WINHVPLATFORM_FUNCTIONS_SUPPLEMENTAL(WHP_DECLARE_MEMBER) }; =20 --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731578; cv=none; d=zohomail.com; s=zohoarc; b=UVbo/hrhLoa/iFnlNpI1lDPi8PPbXe+YcPrcBBb9/RzLAhr9JViY6avQNXMbWyW+A9p+H4btVQwZjQ/JE0F4zwehRrCuAUkiyGKhnFWnPe977gcttRriZaAAGFZtKQuJ1R9KFoS6ZWLUIRnSIRCGZvV9VKP5aX64Xy65uM2LLc4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731578; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=4Ci/Q1rJoWTvVFAzHOC9y2xpF4wfP74ZNNXf6tgbFQ0=; b=dRmGqSOvsO8KJ4VK+lzShU+1kcZXGh2ivaIcELDL3cj6iz6yG6hOwD1i3mPy72qJi6nNma3+fLebFtX4AVnbVP+aLzTSQioVgqISyLYK1fPZ9LyaB0OLsdCNjNyar1k3u2V6ozj36ZWUDsRHWkVwJlE23bk6xbR2RDV3OPEOhOg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17707315786601009.73439758816; Tue, 10 Feb 2026 05:52:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAC-00022n-Ug; Tue, 10 Feb 2026 08:52:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAB-00021P-IK for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:23 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoA7-0006LO-9D for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:20 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-48334ee0aeaso8901635e9.1 for ; Tue, 10 Feb 2026 05:52:18 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731538; x=1771336338; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4Ci/Q1rJoWTvVFAzHOC9y2xpF4wfP74ZNNXf6tgbFQ0=; b=vIT+Lcn/NbqHQCRQgX9nfk5QYimwPO8eS/dcHqzVPGVJ/nwD/rQ0WrhE4hHWENH61g Kf15cR0vK7W+VPPwc3a3N77FkVT+h1WI+R2gVX3QR5bidycLBjgeNpyJeLB+m8xBUNNb /A5ONy4S/wo14sSn6D1588QnyJxgNsULbrXQbzwSm6QdEmcJ4o4mG608xl1qNZd7ZYFa FQN+pEBGHWZdzVfWGiZhPrMb2r91K+bw5QeGDTQ/2ClHKY8h/TesYK/rIRO1tyzrKK7B qw8iySntgmZHbgdqOXGkXDkQDlLI/7ul9MQ4tnSdaeFaKqp3/jst4JiTpC9qYlTZ58Jh OBXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731538; x=1771336338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=4Ci/Q1rJoWTvVFAzHOC9y2xpF4wfP74ZNNXf6tgbFQ0=; b=TOadXPn5Apz880WIwrnXB3THRS+U7bpm/Q23K0+eEr+5X74dsoLWCnBciv218nofZC 4aTGnrR0o/mQINp3qSQK6gfqDj+tRBMLY0Kno6v0I0u5gRl9oJJA6P2HIMtkFReXCw2G DQaWE2sL7Qymcg4B8Yuojxlxd2Milhafc7vrYaj1wNVAxmoYyfclPmMHTVq866sbK9yh t0Y1M8wJ0q0EYivsCDgXE+h/remHLnMi6XjbAPIatBWYGC3OG85dNTSFDmOJ2lhnv/Vx hx4+51Nrzb+9xw815aOpvl+mHZ+mHESUhUZkppKXWJTS80CeeUYvfbNxlkC3zCuJkLLt 5uzw== X-Gm-Message-State: AOJu0Ywf03O63oEWT4D+oSJJ7KbrkmUp+NyShriIviT5bPXTMOuPswpB W417YceobmwBw8P55pHbOKJNIPaE9GF2LJ2r0EduYGr8O+g/i5t+KDi3dPceUVTXo3GUg0GygXZ Z5jXJ X-Gm-Gg: AZuq6aKmReYrmdwb4LD4Rh6DIU+N3VzGh22N308yaYq2ZYg+T4+McGlZIkou1fQ7jtU P7Zzei7yZaQ5EGv7xbC8NHoG6Dexmjqmba4sta9MP3if0bn8LQ1OBr+IB9HgJc3Rks7SeTYNq8I a+bk7xS1qd/94lwHGR1tKmKRsWfhVbEMPVWYxXHXXSIcXNoqzfcGwptuUU+rRU5IEm9x+V0ZYTj nZrsKdXqRjQPnx2NdU/QRGTJz4Mp3uWQLO8WJXKe/e4/CddArjy7JOhPCYUju8WveI+IBKGxLqe y0YkhcEqRNdYTVO6hw2e00jaD8hUhjK2+0ZST2WUhcmG2yFSerOF+sVWumnqOnqbeUoME7/dm1B PnBp19DN+sz3HSlonvpIpzta6JMczrx+aRH8C+rWdFad579q+c6Qudbxu5Fo86PhjOFwF39c68o B0Qpfmmu5GB4AjBNV4hecY7DrZOys2A5t7H4rKlTz0zWBfSxTEVyzSwq+yedyUjAr7EK4e6xgQ7 Y962dfDAAKQcqJnNOE4X0IHlOFs4/rZ4zFbRXIWUg== X-Received: by 2002:a05:600c:3b23:b0:47f:8c05:786b with SMTP id 5b1f17b1804b1-4832021eae9mr212406485e9.28.1770731537716; Tue, 10 Feb 2026 05:52:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/26] whpx: common: add WHPX_INTERCEPT_DEBUG_TRAPS define Date: Tue, 10 Feb 2026 13:51:52 +0000 Message-ID: <20260210135206.229528-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731579380158500 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni As of why: WHPX on arm64 doesn't have debug trap support as of today. Keep the exception bitmap interface for now - despite that being entirely u= navailable on arm64 too. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- accel/whpx/whpx-common.c | 2 +- include/system/whpx-common.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index c58344cb61..c0610815d9 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -119,7 +119,7 @@ int whpx_first_vcpu_starting(CPUState *cpu) * have one or more breakpoints enabled. Both require intercepting * the WHvX64ExceptionTypeBreakpointTrap exception. */ - exception_mask =3D 1UL << WHvX64ExceptionTypeDebugTrapOrFault; + exception_mask =3D 1UL << WHPX_INTERCEPT_DEBUG_TRAPS; } else { /* Let the guest handle all exceptions. */ exception_mask =3D 0; diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h index 8f171d1397..b86fe9db6e 100644 --- a/include/system/whpx-common.h +++ b/include/system/whpx-common.h @@ -20,4 +20,7 @@ int whpx_first_vcpu_starting(CPUState *cpu); int whpx_last_vcpu_stopping(CPUState *cpu); void whpx_memory_init(void); struct whpx_breakpoint *whpx_lookup_breakpoint_by_addr(uint64_t address); + +/* On x64: same as WHvX64ExceptionTypeDebugTrapOrFault */ +#define WHPX_INTERCEPT_DEBUG_TRAPS 1 #endif --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731676; cv=none; d=zohomail.com; s=zohoarc; b=PNbQ1hGeccPxQBbi2oqQy9W5/O0kahYQk3fs8xg5yT1pyZQTU3JTl0mF6HNlhLi+BhEvCMLWI5tyIAjgnSLytqmL7PNIMV0NpwB3wJoFSIX6eTFBUX6ox3msnYKdzhY9jNyLbj1HrMGvyF5reGAn0bOWbRLdo6WVMJOim5H3GuU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731676; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=5xPq2fNqcw/oH0dNiPR3/K9/+sAUVQTjTaQpF6aGozQ=; b=RqQlui+fCQ4BkwGhIOvfGoM21RHsjpecoQ5hKqUztMPkymE8qvxOnfxpggyuP31WnP62Ak4NhMclvoKPJjHiUUaT09W74RopxKr6J3pwLwCe1mM8+wa1CCXRvzFrACyhJGIbrYKGf6KfV1mWi4zEee78zfsfODeEInqWMWlfX1Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731676924158.96920336081484; Tue, 10 Feb 2026 05:54:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAG-0002BG-UQ; Tue, 10 Feb 2026 08:52:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAD-00026d-S9 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:25 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAB-0006LZ-5f for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:25 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-48336a6e932so16499115e9.3 for ; Tue, 10 Feb 2026 05:52:19 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731539; x=1771336339; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5xPq2fNqcw/oH0dNiPR3/K9/+sAUVQTjTaQpF6aGozQ=; b=m7nLKRFItcahzz3AkSBg6nlbmGeI+NHTWkJ0gpJbCydA8pZOl/CEMfqAG6k9WJgySO fYxQcQpCpqcrMvfY0uPkfx5o8YrXZQMI8xJ/eZuGaaXFh92xnP94nD44KY1Y92DWu6NW XnjMp2i0nzRWQW+CgnMATGLJ0Wp8jGtIu9HcY1gYiwqVdZyb3b9GM8BD2Lxv5FqS3wdg bywwH06A09ybx72EUfQIuue4hYkzdDC/9R1tuOYHY0SNyoEHF9TvQtQCfydwFaNMSYwt 8zOT4ds6Nm+VWlxd+IVcz0/6Ff+3pee1BcJW0jTnh1Oiq6bDgtoDCT3A3vtLhUwPTkpn 348Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731539; x=1771336339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=5xPq2fNqcw/oH0dNiPR3/K9/+sAUVQTjTaQpF6aGozQ=; b=TNYp5z4HIiMccbjiCV2luSSbwQY4AqtAwXl9+oc8bktZcGSWpu8QMxTnHnySx4tD1A i3AJSX0lBzfk+6Ks2MMhmJNSXp/SfSwE2uNqT5I8U6I512LO0giK6akJM9i4wgjAnNp2 B0PVFdii0yHdyWsmcpNVx9NG6NFYRr4OukCmQktg1tdNtK58tvbhdmuvXEYk0sBQcGQA h/WjAidMS6giikO4d1S2klLcW7tXE53LQCt9IZ2fYnioahKzT7m2ExplAYmmq99TtXKT L0Q5pdZfNidr2rrSxxsj+n+L2Bkkj05JG7L1tQkJh0FBGDevcEqfNZQw3VDiWbFIRmQu l7UA== X-Gm-Message-State: AOJu0YxmmTKdSUipPRB9bu+NMi0Q2Uw7o2T05DJWTfN4ninptEQLKJAg pybMhl0bA7oRcSI4hQ1ZgBhrKFFoU4m5DliT0gypgFB82FP25u/VRLGKgYfnp7PL5+DRujzuwd6 toNJd X-Gm-Gg: AZuq6aKxAX/zdU5qC0VhR4jYG35fAWK0ph+oAFko9DF+Wt1LPfjWXoUDFzPjJcKmczx eRW/jQQq5mGn6zjoRVuqWltj04kNCZIGBdISNYOUWKhZnTp/De2sWWmDHE+njusPvBsVd6vyrZV Eofh8u1ncGKTfXhn0iD4xXOcsCipKb8X90778suUDwzKb75/bhNM5/TfKzLNFPEkel0F5/Gnegn bk3zytWXwFfpFqWcVtR3EgZ/+tEMgxPLdCOsM/Gyp7kOVVjQyKNqnXrpqGa/Dpbt0hSW0xvcm3K gR4FsX4maVDwAEcoVmbTvJReWb7lixJuQPJwEb9Bqw8XcATv+coq1CkqwLBvCziWx2L2ww0J9ze 8E23nDyALpy+RUTuwIq9/U2jcNWVzjEahAUD2bdlfOXcX4WpdL4X8oiMIsHxJSlPSbmUpeS6ZPN hxJ8imwQkKtXaKWLfvYfyJDej49sh7MgIRT/XlFoUWToghfm0cNp1Q18Muep2aoWnvMcVliwoyS q4+oUrvHC5UVfwKGbqiTSXjoLdGGE89QXhc3eNNjQ== X-Received: by 2002:a05:600c:34c5:b0:480:1b65:b744 with SMTP id 5b1f17b1804b1-4832021e972mr211015325e9.28.1770731538591; Tue, 10 Feb 2026 05:52:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/26] hw, target, accel: whpx: change apic_in_platform to kernel_irqchip Date: Tue, 10 Feb 2026 13:51:53 +0000 Message-ID: <20260210135206.229528-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731677460154100 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Change terminology to match the KVM one, as APIC is x86-specific. And move out whpx_irqchip_in_kernel() to make it usable from common code even when not compiling with WHPX support. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + accel/stubs/whpx-stub.c | 1 + accel/whpx/whpx-accel-ops.c | 2 +- accel/whpx/whpx-common.c | 10 +- hw/arm/virt.c | 9 ++ hw/i386/x86-cpu.c | 4 +- hw/intc/arm_gicv3_common.c | 3 + hw/intc/arm_gicv3_whpx.c | 237 +++++++++++++++++++++++++++++ hw/intc/meson.build | 1 + include/hw/intc/arm_gicv3_common.h | 3 + include/system/whpx-internal.h | 1 - include/system/whpx.h | 5 +- target/i386/cpu-apic.c | 2 +- target/i386/whpx/whpx-all.c | 14 +- 14 files changed, 270 insertions(+), 23 deletions(-) create mode 100644 hw/intc/arm_gicv3_whpx.c diff --git a/MAINTAINERS b/MAINTAINERS index 54326b1a5a..c6af6e10bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,7 @@ M: Mohamed Mediouni S: Supported F: accel/whpx/ F: target/i386/whpx/ +F: hw/intc/arm_gicv3_whpx.c F: accel/stubs/whpx-stub.c F: include/system/whpx.h F: include/system/whpx-accel-ops.h diff --git a/accel/stubs/whpx-stub.c b/accel/stubs/whpx-stub.c index c564c89fd0..4529dc4f78 100644 --- a/accel/stubs/whpx-stub.c +++ b/accel/stubs/whpx-stub.c @@ -10,3 +10,4 @@ #include "system/whpx.h" =20 bool whpx_allowed; +bool whpx_irqchip_in_kernel; diff --git a/accel/whpx/whpx-accel-ops.c b/accel/whpx/whpx-accel-ops.c index c84a25c273..50fadea0fd 100644 --- a/accel/whpx/whpx-accel-ops.c +++ b/accel/whpx/whpx-accel-ops.c @@ -78,7 +78,7 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) =20 static bool whpx_vcpu_thread_is_idle(CPUState *cpu) { - return !whpx_apic_in_platform(); + return !whpx_irqchip_in_kernel(); } =20 static void whpx_accel_ops_class_init(ObjectClass *oc, const void *data) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index c0610815d9..05f9e520b7 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -35,6 +35,7 @@ #include =20 bool whpx_allowed; +bool whpx_irqchip_in_kernel; static bool whp_dispatch_initialized; static HMODULE hWinHvPlatform; #ifdef HOST_X86_64 @@ -488,15 +489,6 @@ static const TypeInfo whpx_cpu_accel_type =3D { .abstract =3D true, }; =20 -/* - * Partition support - */ - -bool whpx_apic_in_platform(void) -{ - return whpx_global.apic_in_platform; -} - static void whpx_accel_class_init(ObjectClass *oc, const void *data) { AccelClass *ac =3D ACCEL_CLASS(oc); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index aa5e992712..b7eb0cec5e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -49,6 +49,7 @@ #include "system/tcg.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/whpx.h" #include "system/qtest.h" #include "system/system.h" #include "hw/core/loader.h" @@ -2114,6 +2115,8 @@ static void finalize_gic_version(VirtMachineState *vm= s) /* KVM w/o kernel irqchip can only deal with GICv2 */ gics_supported |=3D VIRT_GIC_VERSION_2_MASK; accel_name =3D "KVM with kernel-irqchip=3Doff"; + } else if (whpx_enabled()) { + gics_supported |=3D VIRT_GIC_VERSION_3_MASK; } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) { gics_supported |=3D VIRT_GIC_VERSION_2_MASK; if (module_object_class_by_name("arm-gicv3")) { @@ -2154,6 +2157,8 @@ static void finalize_msi_controller(VirtMachineState = *vms) if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_AUTO) { if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; + } else if (whpx_enabled()) { + vms->msi_controller =3D VIRT_MSI_CTRL_GICV2M; } else { vms->msi_controller =3D VIRT_MSI_CTRL_ITS; } @@ -2169,6 +2174,10 @@ static void finalize_msi_controller(VirtMachineState= *vms) error_report("GICv2 + ITS is an invalid configuration."); exit(1); } + if (whpx_enabled()) { + error_report("ITS not supported on WHPX."); + exit(1); + } } =20 assert(vms->msi_controller !=3D VIRT_MSI_CTRL_AUTO); diff --git a/hw/i386/x86-cpu.c b/hw/i386/x86-cpu.c index 276f2b0cdf..95e08e3c2a 100644 --- a/hw/i386/x86-cpu.c +++ b/hw/i386/x86-cpu.c @@ -45,7 +45,7 @@ static void pic_irq_request(void *opaque, int irq, int le= vel) =20 trace_x86_pic_interrupt(irq, level); if (cpu_is_apic_enabled(cpu->apic_state) && !kvm_irqchip_in_kernel() && - !whpx_apic_in_platform()) { + !whpx_irqchip_in_kernel()) { CPU_FOREACH(cs) { cpu =3D X86_CPU(cs); if (apic_accept_pic_intr(cpu->apic_state)) { @@ -71,7 +71,7 @@ int cpu_get_pic_interrupt(CPUX86State *env) X86CPU *cpu =3D env_archcpu(env); int intno; =20 - if (!kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) { + if (!kvm_irqchip_in_kernel() && !whpx_irqchip_in_kernel()) { intno =3D apic_get_interrupt(cpu->apic_state); if (intno >=3D 0) { return intno; diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 0a2e5a3e2f..9054143ea7 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -32,6 +32,7 @@ #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" #include "system/kvm.h" +#include "system/whpx.h" =20 =20 static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs) @@ -663,6 +664,8 @@ const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { return "kvm-arm-gicv3"; + } else if (whpx_enabled()) { + return TYPE_WHPX_GICV3; } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/hw/intc/arm_gicv3_whpx.c b/hw/intc/arm_gicv3_whpx.c new file mode 100644 index 0000000000..849a005242 --- /dev/null +++ b/hw/intc/arm_gicv3_whpx.c @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ARM Generic Interrupt Controller using HVF platform support + * + * Copyright (c) 2025 Mohamed Mediouni + * Based on vGICv3 KVM code by Pavel Fedin + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/intc/arm_gicv3_common.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "system/runstate.h" +#include "system/whpx.h" +#include "system/whpx-internal.h" +#include "gicv3_internal.h" +#include "vgic_common.h" +#include "migration/blocker.h" +#include "qom/object.h" +#include "target/arm/cpregs.h" + +#include "hw/arm/bsa.h" +#include +#include +#include + +struct WHPXARMGICv3Class { + ARMGICv3CommonClass parent_class; + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +OBJECT_DECLARE_TYPE(GICv3State, WHPXARMGICv3Class, WHPX_GICV3) + +/* TODO: Implement GIC state save-restore */ +static void whpx_gicv3_check(GICv3State *s) +{ +} + +static void whpx_gicv3_put(GICv3State *s) +{ + whpx_gicv3_check(s); +} + +static void whpx_gicv3_get(GICv3State *s) +{ +} + +static void whpx_gicv3_set_irq(void *opaque, int irq, int level) +{ + struct whpx_state *whpx =3D &whpx_global; + GICv3State *s =3D opaque; + WHV_INTERRUPT_CONTROL interrupt_control =3D { + .InterruptControl.InterruptType =3D WHvArm64InterruptTypeFixed, + .RequestedVector =3D GIC_INTERNAL + irq, + .InterruptControl.Asserted =3D level + }; + + if (irq > s->num_irq) { + return; + } + + + whp_dispatch.WHvRequestInterrupt(whpx->partition, &interrupt_control, + sizeof(interrupt_control)); +} + +static void whpx_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + GICv3CPUState *c; + + c =3D env->gicv3state; + + c->icc_pmr_el1 =3D 0; + /* + * Architecturally the reset value of the ICC_BPR registers + * is UNKNOWN. We set them all to 0 here; when the kernel + * uses these values to program the ICH_VMCR_EL2 fields that + * determine the guest-visible ICC_BPR register values, the + * hardware's "writing a value less than the minimum sets + * the field to the minimum value" behaviour will result in + * them effectively resetting to the correct minimum value + * for the host GIC. + */ + c->icc_bpr[GICV3_G0] =3D 0; + c->icc_bpr[GICV3_G1] =3D 0; + c->icc_bpr[GICV3_G1NS] =3D 0; + + c->icc_sre_el1 =3D 0x7; + memset(c->icc_apr, 0, sizeof(c->icc_apr)); + memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen)); +} + +static void whpx_gicv3_reset_hold(Object *obj, ResetType type) +{ + GICv3State *s =3D ARM_GICV3_COMMON(obj); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_GET_CLASS(s); + + if (kgc->parent_phases.hold) { + kgc->parent_phases.hold(obj, type); + } + + whpx_gicv3_put(s); +} + + +/* + * CPU interface registers of GIC needs to be reset on CPU reset. + * For the calling arm_gicv3_icc_reset() on CPU reset, we register + * below ARMCPRegInfo. As we reset the whole cpu interface under single + * register reset, we define only one register of CPU interface instead + * of defining all the registers. + */ +static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { + { .name =3D "ICC_CTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 12, .opc2 =3D 4, + /* + * If ARM_CP_NOP is used, resetfn is not called, + * So ARM_CP_NO_RAW is appropriate type. + */ + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, + .readfn =3D arm_cp_read_zero, + .writefn =3D arm_cp_write_ignore, + /* + * We hang the whole cpu interface reset routine off here + * rather than parcelling it out into one little function + * per register + */ + .resetfn =3D whpx_gicv3_icc_reset, + }, +}; + +static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_gicv3_realize(DeviceState *dev, Error **errp) +{ + ERRP_GUARD(); + GICv3State *s =3D WHPX_GICV3(dev); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_GET_CLASS(s); + int i; + + kgc->parent_realize(dev, errp); + if (*errp) { + return; + } + + if (s->revision !=3D 3) { + error_setg(errp, "unsupported GIC revision %d for platform GIC", + s->revision); + return; + } + + if (s->security_extn) { + error_setg(errp, "the platform vGICv3 does not implement the " + "security extensions"); + return; + } + + if (s->nmi_support) { + error_setg(errp, "NMI is not supported with the platform GIC"); + return; + } + + if (s->nb_redist_regions > 1) { + error_setg(errp, "Multiple VGICv3 redistributor regions are not " + "supported by WHPX"); + error_append_hint(errp, "A maximum of %d VCPUs can be used", + s->redist_region_count[0]); + return; + } + + gicv3_init_irqs_and_mmio(s, whpx_gicv3_set_irq, NULL); + + for (i =3D 0; i < s->num_cpu; i++) { + CPUState *cpu_state =3D qemu_get_cpu(i); + ARMCPU *cpu =3D ARM_CPU(cpu_state); + WHV_REGISTER_VALUE val =3D {.Reg64 =3D 0x080A0000 + (GICV3_REDIST_= SIZE * i)}; + whpx_set_reg(cpu_state, WHvArm64RegisterGicrBaseGpa, val); + define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + } + + if (s->maint_irq) { + error_setg(errp, "Nested virtualisation not currently supported by= WHPX."); + return; + } + + error_setg(&s->migration_blocker, + "Live migration disabled because GIC state save/restore not suppor= ted on WHPX"); + if (migrate_add_blocker(&s->migration_blocker, errp) < 0) { + error_report_err(*errp); + } +} + +static void whpx_gicv3_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + ARMGICv3CommonClass *agcc =3D ARM_GICV3_COMMON_CLASS(klass); + WHPXARMGICv3Class *kgc =3D WHPX_GICV3_CLASS(klass); + + agcc->pre_save =3D whpx_gicv3_get; + agcc->post_load =3D whpx_gicv3_put; + + device_class_set_parent_realize(dc, whpx_gicv3_realize, + &kgc->parent_realize); + resettable_class_set_parent_phases(rc, NULL, whpx_gicv3_reset_hold, NU= LL, + &kgc->parent_phases); +} + +static const TypeInfo whpx_arm_gicv3_info =3D { + .name =3D TYPE_WHPX_GICV3, + .parent =3D TYPE_ARM_GICV3_COMMON, + .instance_size =3D sizeof(GICv3State), + .class_init =3D whpx_gicv3_class_init, + .class_size =3D sizeof(WHPXARMGICv3Class), +}; + +static void whpx_gicv3_register_types(void) +{ + type_register_static(&whpx_arm_gicv3_info); +} + +type_init(whpx_gicv3_register_types) diff --git a/hw/intc/meson.build b/hw/intc/meson.build index faae20b93d..96742df090 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -41,6 +41,7 @@ specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic= .c', 'apic_common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_= common.c')) arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpui= f.c')) specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'= )) +specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('a= rm_gicv3_whpx.c')) specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: f= iles('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c')) arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c')) specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c')) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 3d24ad22d2..c55cf18120 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -313,6 +313,9 @@ typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass, ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON) =20 +/* Types for GICv3 kernel-irqchip */ +#define TYPE_WHPX_GICV3 "whpx-arm-gicv3" + struct ARMGICv3CommonClass { /*< private >*/ SysBusDeviceClass parent_class; diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 609d0e1c08..8ded54a39b 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -45,7 +45,6 @@ struct whpx_state { =20 bool kernel_irqchip_allowed; bool kernel_irqchip_required; - bool apic_in_platform; }; =20 extern struct whpx_state whpx_global; diff --git a/include/system/whpx.h b/include/system/whpx.h index 00f6a3e523..4217a27e91 100644 --- a/include/system/whpx.h +++ b/include/system/whpx.h @@ -25,11 +25,12 @@ =20 #ifdef CONFIG_WHPX_IS_POSSIBLE extern bool whpx_allowed; +extern bool whpx_irqchip_in_kernel; #define whpx_enabled() (whpx_allowed) -bool whpx_apic_in_platform(void); +#define whpx_irqchip_in_kernel() (whpx_irqchip_in_kernel) #else /* !CONFIG_WHPX_IS_POSSIBLE */ #define whpx_enabled() 0 -#define whpx_apic_in_platform() (0) +#define whpx_irqchip_in_kernel() (0) #endif /* !CONFIG_WHPX_IS_POSSIBLE */ =20 #endif /* QEMU_WHPX_H */ diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c index f7ad7b5139..eaa10ad2a3 100644 --- a/target/i386/cpu-apic.c +++ b/target/i386/cpu-apic.c @@ -33,7 +33,7 @@ APICCommonClass *apic_get_class(Error **errp) apic_type =3D "kvm-apic"; } else if (xen_enabled()) { apic_type =3D "xen-apic"; - } else if (whpx_apic_in_platform()) { + } else if (whpx_irqchip_in_kernel()) { apic_type =3D "whpx-apic"; } =20 diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 052cda42bf..8210250dc3 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -607,7 +607,7 @@ void whpx_get_registers(CPUState *cpu) hr); } =20 - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { /* * Fetch the TPR value from the emulated APIC. It may get overwrit= ten * below with the value from CR8 returned by @@ -749,7 +749,7 @@ void whpx_get_registers(CPUState *cpu) =20 assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names)); =20 - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { whpx_apic_get(x86_cpu->apic_state); } =20 @@ -1379,7 +1379,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) } =20 /* Get pending hard interruption or replay one that was overwritten */ - if (!whpx_apic_in_platform()) { + if (!whpx_irqchip_in_kernel()) { if (!vcpu->interruption_pending && vcpu->interruptable && (env->eflags & IF_MASK)) { assert(!new_int.InterruptionPending); @@ -1553,7 +1553,7 @@ int whpx_vcpu_run(CPUState *cpu) =20 if (exclusive_step_mode =3D=3D WHPX_STEP_NONE) { whpx_vcpu_process_async_events(cpu); - if (cpu->halted && !whpx_apic_in_platform()) { + if (cpu->halted && !whpx_irqchip_in_kernel()) { cpu->exception_index =3D EXCP_HLT; qatomic_set(&cpu->exit_request, false); return 0; @@ -1642,7 +1642,7 @@ int whpx_vcpu_run(CPUState *cpu) break; =20 case WHvRunVpExitReasonX64ApicEoi: - assert(whpx_apic_in_platform()); + assert(whpx_irqchip_in_kernel()); ioapic_eoi_broadcast(vcpu->exit_ctx.ApicEoi.InterruptVector); break; =20 @@ -2187,7 +2187,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } } else { - whpx->apic_in_platform =3D true; + whpx_irqchip_in_kernel =3D true; } } =20 @@ -2196,7 +2196,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms) prop.ExtendedVmExits.X64MsrExit =3D 1; prop.ExtendedVmExits.X64CpuidExit =3D 1; prop.ExtendedVmExits.ExceptionExit =3D 1; - if (whpx_apic_in_platform()) { + if (whpx_irqchip_in_kernel()) { prop.ExtendedVmExits.X64ApicInitSipiExitTrap =3D 1; } =20 --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731742; cv=none; d=zohomail.com; s=zohoarc; b=BaVrxbvf+eGhkOTIdlplkxDYrQ9E1kkaLmIzwXoUCZEqCr6gKX2P3+heAlah6SVFkY+ys3Ja33MtS+j7blMj8xVRdL3fMlwdRps2mshP+2G35RzWeewcMD70LcMi4ENc95ia51zzFxVwRn6Ql4+rVyeX+kD09u3SkZ4dgs+XG+E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731742; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=+XOcY+AOu+OcMbkxBTIZN3ikLAl892hSxYanbSLcRcg=; b=NgwrHbV5QopU+cXPGe32s2HBt//LDzer1jbRoCWULVu6b3CJDRkyWZEwGFpFKEtSC6Sjf66EuowNh0DyMfn83TMbtxhwcXfeZEkVURX/q7zN/Ysv+xKycsVLWlKWzWayRD5M0rvV9V1dhuYmd7uOJZ3DoCDBKtmZPpE3bxMK0MM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731742690980.6481068843392; Tue, 10 Feb 2026 05:55:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAH-0002Bs-QC; Tue, 10 Feb 2026 08:52:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAG-0002Ah-73 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:28 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAB-0006Ll-A7 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:27 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4801eb2c0a5so53543395e9.3 for ; Tue, 10 Feb 2026 05:52:21 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731540; x=1771336340; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+XOcY+AOu+OcMbkxBTIZN3ikLAl892hSxYanbSLcRcg=; b=fdcfF5RelNQ+39FGG0QB1Qb97q/hk7IduHRTOsneUqq4PxPB29xFNIuIGbtCNnvk5T oopT6zMOup3rhKfs1jwaEzEDVVrtzF75pZsfNZ3pg8HYViEUzpNpynrLS0R6gyzJLgut DoLFBliNmhvg6swf6GbxDtu8JWSxiscvIya6CFQZn4FpkjEbdoorXo7y2FjV1twNWGal iW75UvhKFNKWjlqpt8SUHY1zvi4QR+9RKuP7z/C+FoukEiVMLvjD/lbTvMEcS/jXx8jX UXDhnZhwTPGsbRrzTadSVtZby2mZjC3ERtZH1kO+52CgC4e9Z6wS5Rn1PqfNFGzuHInh xCXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731540; x=1771336340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=+XOcY+AOu+OcMbkxBTIZN3ikLAl892hSxYanbSLcRcg=; b=FS8TBlT7fC+7Rc/05uo3NOXeMtUsmG4By+OyVpSM8d4K8vM4R4U2sYkgLjiEcItOdV +vXrbD2wMOBQn3LOqEnlLCUA/zQ4EKBRkeIBx8OJUljuonMs+Foyttyh7pNxQI6eHorW tM2k9OVJhOaVqOfmQdCnsxwKDddUPTFRSugjjRpERTW7HvYaWK9pmKwQjmVgGna3r5N8 xhJN5pFrS4kuViiDYENUf+Jrq/L0nTU2jX29OH5PaTSbr0GTkE2SCSXIV3Kg8HS/2tWi oGDmxh4hXKcqojjkfoIWPlWgf7qtplFQzvxiZu791moL+I9+AsNr9w0MJTiOlJsJyVJ4 k2aQ== X-Gm-Message-State: AOJu0YwArxM+VZZbR4PTEWc0WTv6A8kfu6RcY7IsgHf7HO5ABkogVWOD O7lP2BY2Ti8o/2p2P2+5EWypT9Ema4D6w0XzthrTNYnYaVLuFDlb8C/KMl2iRxnWotwjowadocs TdQuy X-Gm-Gg: AZuq6aKqwEs++E/MHTDOnuHwjk5rcAjn4wZJS+JQ/7eTZ2yPZzeD0WBFDKBJjcWZVnH WhxjwTIuUT0tmNBzxA0/BNn9YiGylpMshbf871NIP/piklUqMxzMMUSUTnnc54TLGBc+JUgDk45 WUP3XSGyvnZCEibb2P2y7iTy9ZMOaT3F0zH2TVLX6cIj0UgLbbv0nKyAQHDyApxWf7Zcyr6Cqr1 ab5+rLyd2uDVJu1EUCx9njy3o8puEec9YpaZq9E0IL/L4sCiTgAcoMPcf21AbPhScMb/S2xdnY7 VTr/viz7AKsgvFaOZEf4GcXIiOp1o13I3WZYEXYoyDzT8MX9py9WqBr8ZWFJewlybpP8TTw+dxh 0j02B2d0PFQnyd3JP3KLH4BcHRQrJ3WJBa6mDTUs/CfdKbe6qXtGzAXLr4iMtehW4Bkkn78s5g6 /Diwujyc348Bxr3iww7r5lVZHtX/kxPNG6OxghILqV3FvhXadpq/17CMmA4gDHS+guLfhSJJj5J kv8p/e1RatPJjeEblZ4PISOByb41VQ= X-Received: by 2002:a05:600c:3b1e:b0:483:3380:ca0c with SMTP id 5b1f17b1804b1-4835083456cmr33318915e9.35.1770731539716; Tue, 10 Feb 2026 05:52:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/26] whpx: add arm64 support Date: Tue, 10 Feb 2026 13:51:54 +0000 Message-ID: <20260210135206.229528-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731744363158500 From: Mohamed Mediouni Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + accel/whpx/whpx-common.c | 1 + target/arm/meson.build | 1 + target/arm/whpx/meson.build | 3 + target/arm/whpx/whpx-all.c | 810 ++++++++++++++++++++++++++++++++++++ 5 files changed, 816 insertions(+) create mode 100644 target/arm/whpx/meson.build create mode 100644 target/arm/whpx/whpx-all.c diff --git a/MAINTAINERS b/MAINTAINERS index c6af6e10bb..5cdfea7e11 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -566,6 +566,7 @@ M: Mohamed Mediouni S: Supported F: accel/whpx/ F: target/i386/whpx/ +F: target/arm/whpx/ F: hw/intc/arm_gicv3_whpx.c F: accel/stubs/whpx-stub.c F: include/system/whpx.h diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 05f9e520b7..827f50f3e0 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -12,6 +12,7 @@ #include "gdbstub/helpers.h" #include "qemu/accel.h" #include "accel/accel-ops.h" +#include "system/memory.h" #include "system/whpx.h" #include "system/cpus.h" #include "system/runstate.h" diff --git a/target/arm/meson.build b/target/arm/meson.build index 1a1bcde260..fe396c4318 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -59,6 +59,7 @@ arm_common_system_ss.add(files( )) =20 subdir('hvf') +subdir('whpx') =20 if 'CONFIG_TCG' in config_all_accel subdir('tcg') diff --git a/target/arm/whpx/meson.build b/target/arm/whpx/meson.build new file mode 100644 index 0000000000..1de2ef0283 --- /dev/null +++ b/target/arm/whpx/meson.build @@ -0,0 +1,3 @@ +arm_system_ss.add(when: 'CONFIG_WHPX', if_true: files( + 'whpx-all.c', +)) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c new file mode 100644 index 0000000000..192d7ec7a8 --- /dev/null +++ b/target/arm/whpx/whpx-all.c @@ -0,0 +1,810 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU Windows Hypervisor Platform accelerator (WHPX) + * + * Copyright (c) 2025 Mohamed Mediouni + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "system/address-spaces.h" +#include "system/ioport.h" +#include "gdbstub/helpers.h" +#include "qemu/accel.h" +#include "accel/accel-ops.h" +#include "system/whpx.h" +#include "system/cpus.h" +#include "system/runstate.h" +#include "qemu/main-loop.h" +#include "hw/core/boards.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "qapi/qapi-types-common.h" +#include "qapi/qapi-visit-common.h" +#include "migration/blocker.h" +#include "accel/accel-cpu-target.h" +#include + +#include "syndrome.h" +#include "cpu.h" +#include "target/arm/cpregs.h" +#include "internals.h" + +#include "system/whpx-internal.h" +#include "system/whpx-accel-ops.h" +#include "system/whpx-all.h" +#include "system/whpx-common.h" +#include "hw/arm/bsa.h" +#include "arm-powerctl.h" + +#include +#include + +typedef struct WHPXRegMatch { + WHV_REGISTER_NAME reg; + uint64_t offset; +} WHPXRegMatch; + +static const WHPXRegMatch whpx_reg_match[] =3D { + { WHvArm64RegisterX0, offsetof(CPUARMState, xregs[0]) }, + { WHvArm64RegisterX1, offsetof(CPUARMState, xregs[1]) }, + { WHvArm64RegisterX2, offsetof(CPUARMState, xregs[2]) }, + { WHvArm64RegisterX3, offsetof(CPUARMState, xregs[3]) }, + { WHvArm64RegisterX4, offsetof(CPUARMState, xregs[4]) }, + { WHvArm64RegisterX5, offsetof(CPUARMState, xregs[5]) }, + { WHvArm64RegisterX6, offsetof(CPUARMState, xregs[6]) }, + { WHvArm64RegisterX7, offsetof(CPUARMState, xregs[7]) }, + { WHvArm64RegisterX8, offsetof(CPUARMState, xregs[8]) }, + { WHvArm64RegisterX9, offsetof(CPUARMState, xregs[9]) }, + { WHvArm64RegisterX10, offsetof(CPUARMState, xregs[10]) }, + { WHvArm64RegisterX11, offsetof(CPUARMState, xregs[11]) }, + { WHvArm64RegisterX12, offsetof(CPUARMState, xregs[12]) }, + { WHvArm64RegisterX13, offsetof(CPUARMState, xregs[13]) }, + { WHvArm64RegisterX14, offsetof(CPUARMState, xregs[14]) }, + { WHvArm64RegisterX15, offsetof(CPUARMState, xregs[15]) }, + { WHvArm64RegisterX16, offsetof(CPUARMState, xregs[16]) }, + { WHvArm64RegisterX17, offsetof(CPUARMState, xregs[17]) }, + { WHvArm64RegisterX18, offsetof(CPUARMState, xregs[18]) }, + { WHvArm64RegisterX19, offsetof(CPUARMState, xregs[19]) }, + { WHvArm64RegisterX20, offsetof(CPUARMState, xregs[20]) }, + { WHvArm64RegisterX21, offsetof(CPUARMState, xregs[21]) }, + { WHvArm64RegisterX22, offsetof(CPUARMState, xregs[22]) }, + { WHvArm64RegisterX23, offsetof(CPUARMState, xregs[23]) }, + { WHvArm64RegisterX24, offsetof(CPUARMState, xregs[24]) }, + { WHvArm64RegisterX25, offsetof(CPUARMState, xregs[25]) }, + { WHvArm64RegisterX26, offsetof(CPUARMState, xregs[26]) }, + { WHvArm64RegisterX27, offsetof(CPUARMState, xregs[27]) }, + { WHvArm64RegisterX28, offsetof(CPUARMState, xregs[28]) }, + { WHvArm64RegisterFp, offsetof(CPUARMState, xregs[29]) }, + { WHvArm64RegisterLr, offsetof(CPUARMState, xregs[30]) }, + { WHvArm64RegisterPc, offsetof(CPUARMState, pc) }, +}; + +static const WHPXRegMatch whpx_fpreg_match[] =3D { + { WHvArm64RegisterQ0, offsetof(CPUARMState, vfp.zregs[0]) }, + { WHvArm64RegisterQ1, offsetof(CPUARMState, vfp.zregs[1]) }, + { WHvArm64RegisterQ2, offsetof(CPUARMState, vfp.zregs[2]) }, + { WHvArm64RegisterQ3, offsetof(CPUARMState, vfp.zregs[3]) }, + { WHvArm64RegisterQ4, offsetof(CPUARMState, vfp.zregs[4]) }, + { WHvArm64RegisterQ5, offsetof(CPUARMState, vfp.zregs[5]) }, + { WHvArm64RegisterQ6, offsetof(CPUARMState, vfp.zregs[6]) }, + { WHvArm64RegisterQ7, offsetof(CPUARMState, vfp.zregs[7]) }, + { WHvArm64RegisterQ8, offsetof(CPUARMState, vfp.zregs[8]) }, + { WHvArm64RegisterQ9, offsetof(CPUARMState, vfp.zregs[9]) }, + { WHvArm64RegisterQ10, offsetof(CPUARMState, vfp.zregs[10]) }, + { WHvArm64RegisterQ11, offsetof(CPUARMState, vfp.zregs[11]) }, + { WHvArm64RegisterQ12, offsetof(CPUARMState, vfp.zregs[12]) }, + { WHvArm64RegisterQ13, offsetof(CPUARMState, vfp.zregs[13]) }, + { WHvArm64RegisterQ14, offsetof(CPUARMState, vfp.zregs[14]) }, + { WHvArm64RegisterQ15, offsetof(CPUARMState, vfp.zregs[15]) }, + { WHvArm64RegisterQ16, offsetof(CPUARMState, vfp.zregs[16]) }, + { WHvArm64RegisterQ17, offsetof(CPUARMState, vfp.zregs[17]) }, + { WHvArm64RegisterQ18, offsetof(CPUARMState, vfp.zregs[18]) }, + { WHvArm64RegisterQ19, offsetof(CPUARMState, vfp.zregs[19]) }, + { WHvArm64RegisterQ20, offsetof(CPUARMState, vfp.zregs[20]) }, + { WHvArm64RegisterQ21, offsetof(CPUARMState, vfp.zregs[21]) }, + { WHvArm64RegisterQ22, offsetof(CPUARMState, vfp.zregs[22]) }, + { WHvArm64RegisterQ23, offsetof(CPUARMState, vfp.zregs[23]) }, + { WHvArm64RegisterQ24, offsetof(CPUARMState, vfp.zregs[24]) }, + { WHvArm64RegisterQ25, offsetof(CPUARMState, vfp.zregs[25]) }, + { WHvArm64RegisterQ26, offsetof(CPUARMState, vfp.zregs[26]) }, + { WHvArm64RegisterQ27, offsetof(CPUARMState, vfp.zregs[27]) }, + { WHvArm64RegisterQ28, offsetof(CPUARMState, vfp.zregs[28]) }, + { WHvArm64RegisterQ29, offsetof(CPUARMState, vfp.zregs[29]) }, + { WHvArm64RegisterQ30, offsetof(CPUARMState, vfp.zregs[30]) }, + { WHvArm64RegisterQ31, offsetof(CPUARMState, vfp.zregs[31]) }, +}; + +struct whpx_sreg_match { + WHV_REGISTER_NAME reg; + uint32_t key; + bool global; + uint32_t cp_idx; +}; + +static struct whpx_sreg_match whpx_sreg_match[] =3D { + { WHvArm64RegisterDbgbvr0El1, ENCODE_AA64_CP_REG(0, 0, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr0El1, ENCODE_AA64_CP_REG(0, 0, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr0El1, ENCODE_AA64_CP_REG(0, 0, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr0El1, ENCODE_AA64_CP_REG(0, 0, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr0El1, ENCODE_AA64_CP_REG(0, 1, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr0El1, ENCODE_AA64_CP_REG(0, 1, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr0El1, ENCODE_AA64_CP_REG(0, 1, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr0El1, ENCODE_AA64_CP_REG(0, 1, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr2El1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr2El1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr2El1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr2El1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr3El1, ENCODE_AA64_CP_REG(0, 3, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr3El1, ENCODE_AA64_CP_REG(0, 3, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr3El1, ENCODE_AA64_CP_REG(0, 3, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr3El1, ENCODE_AA64_CP_REG(0, 3, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr4El1, ENCODE_AA64_CP_REG(0, 4, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr4El1, ENCODE_AA64_CP_REG(0, 4, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr4El1, ENCODE_AA64_CP_REG(0, 4, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr4El1, ENCODE_AA64_CP_REG(0, 4, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr5El1, ENCODE_AA64_CP_REG(0, 5, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr5El1, ENCODE_AA64_CP_REG(0, 5, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr5El1, ENCODE_AA64_CP_REG(0, 5, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr5El1, ENCODE_AA64_CP_REG(0, 5, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr6El1, ENCODE_AA64_CP_REG(0, 6, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr6El1, ENCODE_AA64_CP_REG(0, 6, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr6El1, ENCODE_AA64_CP_REG(0, 6, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr6El1, ENCODE_AA64_CP_REG(0, 6, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr7El1, ENCODE_AA64_CP_REG(0, 7, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr7El1, ENCODE_AA64_CP_REG(0, 7, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr7El1, ENCODE_AA64_CP_REG(0, 7, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr7El1, ENCODE_AA64_CP_REG(0, 7, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr8El1, ENCODE_AA64_CP_REG(0, 8, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr8El1, ENCODE_AA64_CP_REG(0, 8, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr8El1, ENCODE_AA64_CP_REG(0, 8, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr8El1, ENCODE_AA64_CP_REG(0, 8, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr9El1, ENCODE_AA64_CP_REG(0, 9, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr9El1, ENCODE_AA64_CP_REG(0, 9, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr9El1, ENCODE_AA64_CP_REG(0, 9, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr9El1, ENCODE_AA64_CP_REG(0, 9, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr10El1, ENCODE_AA64_CP_REG(0, 10, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr10El1, ENCODE_AA64_CP_REG(0, 10, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr10El1, ENCODE_AA64_CP_REG(0, 10, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr10El1, ENCODE_AA64_CP_REG(0, 10, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr11El1, ENCODE_AA64_CP_REG(0, 11, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr11El1, ENCODE_AA64_CP_REG(0, 11, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr11El1, ENCODE_AA64_CP_REG(0, 11, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr11El1, ENCODE_AA64_CP_REG(0, 11, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr12El1, ENCODE_AA64_CP_REG(0, 12, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr12El1, ENCODE_AA64_CP_REG(0, 12, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr12El1, ENCODE_AA64_CP_REG(0, 12, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr12El1, ENCODE_AA64_CP_REG(0, 12, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr13El1, ENCODE_AA64_CP_REG(0, 13, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr13El1, ENCODE_AA64_CP_REG(0, 13, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr13El1, ENCODE_AA64_CP_REG(0, 13, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr13El1, ENCODE_AA64_CP_REG(0, 13, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr14El1, ENCODE_AA64_CP_REG(0, 14, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr14El1, ENCODE_AA64_CP_REG(0, 14, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr14El1, ENCODE_AA64_CP_REG(0, 14, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr14El1, ENCODE_AA64_CP_REG(0, 14, 2, 0, 7) }, + + { WHvArm64RegisterDbgbvr15El1, ENCODE_AA64_CP_REG(0, 15, 2, 0, 4) }, + { WHvArm64RegisterDbgbcr15El1, ENCODE_AA64_CP_REG(0, 15, 2, 0, 5) }, + { WHvArm64RegisterDbgwvr15El1, ENCODE_AA64_CP_REG(0, 15, 2, 0, 6) }, + { WHvArm64RegisterDbgwcr15El1, ENCODE_AA64_CP_REG(0, 15, 2, 0, 7) }, +#ifdef SYNC_NO_RAW_REGS + /* + * The registers below are manually synced on init because they are + * marked as NO_RAW. We still list them to make number space sync easi= er. + */ + { WHvArm64RegisterMidrEl1, ENCODE_AA64_CP_REG(0, 0, 3, 0, 0) }, + { WHvArm64RegisterMpidrEl1, ENCODE_AA64_CP_REG(0, 0, 3, 0, 5) }, + { WHvArm64RegisterIdPfr0El1, ENCODE_AA64_CP_REG(0, 4, 3, 0, 0) }, +#endif + { WHvArm64RegisterIdAa64Pfr1El1, ENCODE_AA64_CP_REG(0, 4, 3, 0, 1), tr= ue }, + { WHvArm64RegisterIdAa64Dfr0El1, ENCODE_AA64_CP_REG(0, 5, 3, 0, 0), tr= ue }, + { WHvArm64RegisterIdAa64Dfr1El1, ENCODE_AA64_CP_REG(0, 5, 3, 0, 1), tr= ue }, + { WHvArm64RegisterIdAa64Isar0El1, ENCODE_AA64_CP_REG(0, 6, 3, 0, 0), t= rue }, + { WHvArm64RegisterIdAa64Isar1El1, ENCODE_AA64_CP_REG(0, 6, 3, 0, 1), t= rue }, +#ifdef SYNC_NO_MMFR0 + /* We keep the hardware MMFR0 around. HW limits are there anyway */ + { WHvArm64RegisterIdAa64Mmfr0El1, ENCODE_AA64_CP_REG(0, 7, 3, 0, 0) }, +#endif + { WHvArm64RegisterIdAa64Mmfr1El1, ENCODE_AA64_CP_REG(0, 7, 3, 0, 1), t= rue }, + { WHvArm64RegisterIdAa64Mmfr2El1, ENCODE_AA64_CP_REG(0, 7, 3, 0, 2), t= rue }, + { WHvArm64RegisterIdAa64Mmfr3El1, ENCODE_AA64_CP_REG(0, 7, 3, 0, 3), t= rue }, + + { WHvArm64RegisterMdscrEl1, ENCODE_AA64_CP_REG(0, 2, 2, 0, 2) }, + { WHvArm64RegisterSctlrEl1, ENCODE_AA64_CP_REG(1, 0, 3, 0, 0) }, + { WHvArm64RegisterCpacrEl1, ENCODE_AA64_CP_REG(1, 0, 3, 0, 2) }, + { WHvArm64RegisterTtbr0El1, ENCODE_AA64_CP_REG(2, 0, 3, 0, 0) }, + { WHvArm64RegisterTtbr1El1, ENCODE_AA64_CP_REG(2, 0, 3, 0, 1) }, + { WHvArm64RegisterTcrEl1, ENCODE_AA64_CP_REG(2, 0, 3, 0, 2) }, + + { WHvArm64RegisterApiAKeyLoEl1, ENCODE_AA64_CP_REG(2, 1, 3, 0, 0) }, + { WHvArm64RegisterApiAKeyHiEl1, ENCODE_AA64_CP_REG(2, 1, 3, 0, 1) }, + { WHvArm64RegisterApiBKeyLoEl1, ENCODE_AA64_CP_REG(2, 1, 3, 0, 2) }, + { WHvArm64RegisterApiBKeyHiEl1, ENCODE_AA64_CP_REG(2, 1, 3, 0, 3) }, + { WHvArm64RegisterApdAKeyLoEl1, ENCODE_AA64_CP_REG(2, 2, 3, 0, 0) }, + { WHvArm64RegisterApdAKeyHiEl1, ENCODE_AA64_CP_REG(2, 2, 3, 0, 1) }, + { WHvArm64RegisterApdBKeyLoEl1, ENCODE_AA64_CP_REG(2, 2, 3, 0, 2) }, + { WHvArm64RegisterApdBKeyHiEl1, ENCODE_AA64_CP_REG(2, 2, 3, 0, 3) }, + { WHvArm64RegisterApgAKeyLoEl1, ENCODE_AA64_CP_REG(2, 3, 3, 0, 0) }, + { WHvArm64RegisterApgAKeyHiEl1, ENCODE_AA64_CP_REG(2, 3, 3, 0, 1) }, + + { WHvArm64RegisterSpsrEl1, ENCODE_AA64_CP_REG(4, 0, 3, 0, 0) }, + { WHvArm64RegisterElrEl1, ENCODE_AA64_CP_REG(4, 0, 3, 0, 1) }, + { WHvArm64RegisterSpEl1, ENCODE_AA64_CP_REG(4, 1, 3, 0, 0) }, + { WHvArm64RegisterEsrEl1, ENCODE_AA64_CP_REG(5, 2, 3, 0, 0) }, + { WHvArm64RegisterFarEl1, ENCODE_AA64_CP_REG(6, 0, 3, 0, 0) }, + { WHvArm64RegisterParEl1, ENCODE_AA64_CP_REG(7, 4, 3, 0, 0) }, + { WHvArm64RegisterMairEl1, ENCODE_AA64_CP_REG(10, 2, 3, 0, 0) }, + { WHvArm64RegisterVbarEl1, ENCODE_AA64_CP_REG(12, 0, 3, 0, 0) }, + { WHvArm64RegisterContextidrEl1, ENCODE_AA64_CP_REG(13, 0, 3, 0, 1) }, + { WHvArm64RegisterTpidrEl1, ENCODE_AA64_CP_REG(13, 0, 3, 0, 4) }, + { WHvArm64RegisterCntkctlEl1, ENCODE_AA64_CP_REG(14, 1, 3, 0, 0) }, + { WHvArm64RegisterCsselrEl1, ENCODE_AA64_CP_REG(0, 0, 3, 2, 0) }, + { WHvArm64RegisterTpidrEl0, ENCODE_AA64_CP_REG(13, 0, 3, 3, 2) }, + { WHvArm64RegisterTpidrroEl0, ENCODE_AA64_CP_REG(13, 0, 3, 3, 3) }, + { WHvArm64RegisterCntvCtlEl0, ENCODE_AA64_CP_REG(14, 3, 3, 3, 1) }, + { WHvArm64RegisterCntvCvalEl0, ENCODE_AA64_CP_REG(14, 3, 3, 3, 2) }, + { WHvArm64RegisterSpEl1, ENCODE_AA64_CP_REG(4, 1, 3, 4, 0) }, +}; + +static void flush_cpu_state(CPUState *cpu) +{ + if (cpu->vcpu_dirty) { + whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE); + cpu->vcpu_dirty =3D false; + } +} + +HRESULT whpx_set_exception_exit_bitmap(UINT64 exceptions) +{ + if (exceptions !=3D 0) { + return E_NOTIMPL; + } + return ERROR_SUCCESS; +} +void whpx_apply_breakpoints( + struct whpx_breakpoint_collection *breakpoints, + CPUState *cpu, + bool resuming) +{ + /* Breakpoints aren=E2=80=99t supported on this platform */ +} +void whpx_translate_cpu_breakpoints( + struct whpx_breakpoints *breakpoints, + CPUState *cpu, + int cpu_breakpoint_count) +{ + /* Breakpoints aren=E2=80=99t supported on this platform */ +} + +static void whpx_get_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE* val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + flush_cpu_state(cpu); + + hr =3D whp_dispatch.WHvGetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to get register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_set_reg(CPUState *cpu, WHV_REGISTER_NAME reg, WHV_REGISTE= R_VALUE val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, c= pu->cpu_index, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_get_global_reg(WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE = *val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + + hr =3D whp_dispatch.WHvGetVirtualProcessorRegisters(whpx->partition, W= HV_ANY_VP, + ®, 1, val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to get register %08x, hr=3D%08lx", reg,= hr); + } +} + +static void whpx_set_global_reg(WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE = val) +{ + struct whpx_state *whpx =3D &whpx_global; + HRESULT hr; + hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters(whpx->partition, W= HV_ANY_VP, + ®, 1, &val); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set register %08x, hr=3D%08lx", reg,= hr); + } +} + +static uint64_t whpx_get_gp_reg(CPUState *cpu, int rt) +{ + assert(rt <=3D 31); + if (rt =3D=3D 31) { + return 0; + } + WHV_REGISTER_NAME reg =3D WHvArm64RegisterX0 + rt; + WHV_REGISTER_VALUE val; + whpx_get_reg(cpu, reg, &val); + + return val.Reg64; +} + +static void whpx_set_gp_reg(CPUState *cpu, int rt, uint64_t val) +{ + assert(rt < 31); + WHV_REGISTER_NAME reg =3D WHvArm64RegisterX0 + rt; + WHV_REGISTER_VALUE reg_val =3D {.Reg64 =3D val}; + + whpx_set_reg(cpu, reg, reg_val); +} + +static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) +{ + uint64_t syndrome =3D ctx->Syndrome; + + bool isv =3D syndrome & ARM_EL_ISV; + bool iswrite =3D (syndrome >> 6) & 1; + bool sse =3D (syndrome >> 21) & 1; + uint32_t sas =3D (syndrome >> 22) & 3; + uint32_t len =3D 1 << sas; + uint32_t srt =3D (syndrome >> 16) & 0x1f; + uint32_t cm =3D (syndrome >> 8) & 0x1; + uint64_t val =3D 0; + + assert(!cm); + assert(isv); + + if (iswrite) { + val =3D whpx_get_gp_reg(cpu, srt); + address_space_write(&address_space_memory, + ctx->Gpa, + MEMTXATTRS_UNSPECIFIED, &val, len); + } else { + address_space_read(&address_space_memory, + ctx->Gpa, + MEMTXATTRS_UNSPECIFIED, &val, len); + if (sse) { + val =3D sextract64(val, 0, len * 8); + } + whpx_set_gp_reg(cpu, srt, val); + } + + return 0; +} + +static void whpx_psci_cpu_off(ARMCPU *arm_cpu) +{ + int32_t ret =3D arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); + assert(ret =3D=3D QEMU_ARM_POWERCTL_RET_SUCCESS); +} + +int whpx_vcpu_run(CPUState *cpu) +{ + HRESULT hr; + struct whpx_state *whpx =3D &whpx_global; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + AccelCPUState *vcpu =3D cpu->accel; + int ret; + + + g_assert(bql_locked()); + + if (whpx->running_cpus++ =3D=3D 0) { + ret =3D whpx_first_vcpu_starting(cpu); + if (ret !=3D 0) { + return ret; + } + } + + bql_unlock(); + + + cpu_exec_start(cpu); + do { + bool advance_pc =3D false; + if (cpu->vcpu_dirty) { + whpx_set_registers(cpu, WHPX_SET_RUNTIME_STATE); + cpu->vcpu_dirty =3D false; + } + + if (qatomic_read(&cpu->exit_request)) { + whpx_vcpu_kick(cpu); + } + + hr =3D whp_dispatch.WHvRunVirtualProcessor( + whpx->partition, cpu->cpu_index, + &vcpu->exit_ctx, sizeof(vcpu->exit_ctx)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to exec a virtual processor," + " hr=3D%08lx", hr); + ret =3D -1; + break; + } + + switch (vcpu->exit_ctx.ExitReason) { + case WHvRunVpExitReasonGpaIntercept: + case WHvRunVpExitReasonUnmappedGpa: + advance_pc =3D true; + + if (vcpu->exit_ctx.MemoryAccess.Syndrome & BIT(8)) { + error_report("WHPX: cached access to unmapped memory" + "Pc =3D 0x%llx Gva =3D 0x%llx Gpa =3D 0x%llx", + vcpu->exit_ctx.MemoryAccess.Header.Pc, + vcpu->exit_ctx.MemoryAccess.Gpa, + vcpu->exit_ctx.MemoryAccess.Gva); + break; + } + + ret =3D whpx_handle_mmio(cpu, &vcpu->exit_ctx.MemoryAccess); + break; + case WHvRunVpExitReasonCanceled: + cpu->exception_index =3D EXCP_INTERRUPT; + ret =3D 1; + break; + case WHvRunVpExitReasonArm64Reset: + switch (vcpu->exit_ctx.Arm64Reset.ResetType) { + case WHvArm64ResetTypePowerOff: + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN= ); + break; + case WHvArm64ResetTypeReboot: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + break; + default: + g_assert_not_reached(); + } + bql_lock(); + if (arm_cpu->power_state !=3D PSCI_OFF) { + whpx_psci_cpu_off(arm_cpu); + } + bql_unlock(); + break; + case WHvRunVpExitReasonNone: + case WHvRunVpExitReasonUnrecoverableException: + case WHvRunVpExitReasonInvalidVpRegisterValue: + case WHvRunVpExitReasonUnsupportedFeature: + default: + error_report("WHPX: Unexpected VP exit code 0x%08x", + vcpu->exit_ctx.ExitReason); + whpx_get_registers(cpu); + bql_lock(); + qemu_system_guest_panicked(cpu_get_crash_info(cpu)); + bql_unlock(); + break; + } + if (advance_pc) { + WHV_REGISTER_VALUE pc; + + flush_cpu_state(cpu); + pc.Reg64 =3D vcpu->exit_ctx.MemoryAccess.Header.Pc + 4; + whpx_set_reg(cpu, WHvArm64RegisterPc, pc); + } + } while (!ret); + + cpu_exec_end(cpu); + + bql_lock(); + current_cpu =3D cpu; + + if (--whpx->running_cpus =3D=3D 0) { + whpx_last_vcpu_stopping(cpu); + } + + qatomic_set(&cpu->exit_request, false); + + return ret < 0; +} + +static void clean_whv_register_value(WHV_REGISTER_VALUE *val) +{ + memset(val, 0, sizeof(WHV_REGISTER_VALUE)); +} + +void whpx_get_registers(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + WHV_REGISTER_VALUE val; + int i; + + for (i =3D 0; i < ARRAY_SIZE(whpx_reg_match); i++) { + whpx_get_reg(cpu, whpx_reg_match[i].reg, &val); + *(uint64_t *)((char *)env + whpx_reg_match[i].offset) =3D val.Reg6= 4; + } + + for (i =3D 0; i < ARRAY_SIZE(whpx_fpreg_match); i++) { + whpx_get_reg(cpu, whpx_reg_match[i].reg, &val); + memcpy((char *)env + whpx_fpreg_match[i].offset, &val, sizeof(val.= Reg128)); + } + + whpx_get_reg(cpu, WHvArm64RegisterPc, &val); + env->pc =3D val.Reg64; + + whpx_get_reg(cpu, WHvArm64RegisterFpcr, &val); + vfp_set_fpcr(env, val.Reg32); + + whpx_get_reg(cpu, WHvArm64RegisterFpsr, &val); + vfp_set_fpsr(env, val.Reg32); + + whpx_get_reg(cpu, WHvArm64RegisterPstate, &val); + pstate_write(env, val.Reg32); + + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + + if (whpx_sreg_match[i].global) { + /* WHP disallows us from accessing global regs as a vCPU */ + whpx_get_global_reg(whpx_sreg_match[i].reg, &val); + } else { + whpx_get_reg(cpu, whpx_sreg_match[i].reg, &val); + } + arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx] =3D val.Reg64; + } + + assert(write_list_to_cpustate(arm_cpu)); + aarch64_restore_sp(env, arm_current_el(env)); +} + +void whpx_set_registers(CPUState *cpu, int level) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + WHV_REGISTER_VALUE val; + clean_whv_register_value(&val); + int i; + + assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + + for (i =3D 0; i < ARRAY_SIZE(whpx_reg_match); i++) { + val.Reg64 =3D *(uint64_t *)((char *)env + whpx_reg_match[i].offset= ); + whpx_set_reg(cpu, whpx_reg_match[i].reg, val); + } + + for (i =3D 0; i < ARRAY_SIZE(whpx_fpreg_match); i++) { + memcpy(&val.Reg128, (char *)env + whpx_fpreg_match[i].offset, size= of(val.Reg128)); + whpx_set_reg(cpu, whpx_reg_match[i].reg, val); + } + + clean_whv_register_value(&val); + val.Reg64 =3D env->pc; + whpx_set_reg(cpu, WHvArm64RegisterPc, val); + + clean_whv_register_value(&val); + val.Reg32 =3D vfp_get_fpcr(env); + whpx_set_reg(cpu, WHvArm64RegisterFpcr, val); + val.Reg32 =3D vfp_get_fpsr(env); + whpx_set_reg(cpu, WHvArm64RegisterFpsr, val); + val.Reg32 =3D pstate_read(env); + whpx_set_reg(cpu, WHvArm64RegisterPstate, val); + + aarch64_save_sp(env, arm_current_el(env)); + + assert(write_cpustate_to_list(arm_cpu, false)); + + /* Currently set global regs every time. */ + for (i =3D 0; i < ARRAY_SIZE(whpx_sreg_match); i++) { + if (whpx_sreg_match[i].cp_idx =3D=3D -1) { + continue; + } + + val.Reg64 =3D arm_cpu->cpreg_values[whpx_sreg_match[i].cp_idx]; + if (whpx_sreg_match[i].global) { + /* WHP disallows us from accessing global regs as a vCPU */ + whpx_set_global_reg(whpx_sreg_match[i].reg, val); + } else { + whpx_set_reg(cpu, whpx_sreg_match[i].reg, val); + } + } +} + +static uint32_t max_vcpu_index; + +static void whpx_cpu_update_state(void *opaque, bool running, RunState sta= te) +{ +} + +int whpx_init_vcpu(CPUState *cpu) +{ + HRESULT hr; + struct whpx_state *whpx =3D &whpx_global; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + + uint32_t sregs_match_len =3D ARRAY_SIZE(whpx_sreg_match); + uint32_t sregs_cnt =3D 0; + WHV_REGISTER_VALUE val; + int i; + + hr =3D whp_dispatch.WHvCreateVirtualProcessor( + whpx->partition, cpu->cpu_index, 0); + if (FAILED(hr)) { + error_report("WHPX: Failed to create a virtual processor," + " hr=3D%08lx", hr); + return -EINVAL; + } + + /* Assumption that CNTFRQ_EL0 is the same between the VMM and the part= ition. */ + asm volatile("mrs %0, cntfrq_el0" : "=3Dr"(arm_cpu->gt_cntfrq_hz)); + + cpu->vcpu_dirty =3D true; + cpu->accel =3D g_new0(AccelCPUState, 1); + max_vcpu_index =3D MAX(max_vcpu_index, cpu->cpu_index); + qemu_add_vm_change_state_handler(whpx_cpu_update_state, env); + + env->aarch64 =3D true; + + /* Allocate enough space for our sysreg sync */ + arm_cpu->cpreg_indexes =3D g_renew(uint64_t, arm_cpu->cpreg_indexes, + sregs_match_len); + arm_cpu->cpreg_values =3D g_renew(uint64_t, arm_cpu->cpreg_values, + sregs_match_len); + arm_cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, + arm_cpu->cpreg_vmstate_indexe= s, + sregs_match_len); + arm_cpu->cpreg_vmstate_values =3D g_renew(uint64_t, + arm_cpu->cpreg_vmstate_values, + sregs_match_len); + + memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); + + /* Populate cp list for all known sysregs */ + for (i =3D 0; i < sregs_match_len; i++) { + const ARMCPRegInfo *ri; + uint32_t key =3D whpx_sreg_match[i].key; + + ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs, key); + if (ri) { + assert(!(ri->type & ARM_CP_NO_RAW)); + whpx_sreg_match[i].cp_idx =3D sregs_cnt; + arm_cpu->cpreg_indexes[sregs_cnt++] =3D cpreg_to_kvm_id(key); + } else { + whpx_sreg_match[i].cp_idx =3D -1; + } + } + arm_cpu->cpreg_array_len =3D sregs_cnt; + arm_cpu->cpreg_vmstate_array_len =3D sregs_cnt; + + assert(write_cpustate_to_list(arm_cpu, false)); + + /* Set CP_NO_RAW system registers on init */ + val.Reg64 =3D arm_cpu->midr; + whpx_set_reg(cpu, WHvArm64RegisterMidrEl1, + val); + + clean_whv_register_value(&val); + + val.Reg64 =3D deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */); + whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, val); + + return 0; +} + +void whpx_cpu_instance_init(CPUState *cs) +{ +} + +int whpx_accel_init(AccelState *as, MachineState *ms) +{ + struct whpx_state *whpx; + int ret; + HRESULT hr; + WHV_CAPABILITY whpx_cap; + UINT32 whpx_cap_size; + WHV_PARTITION_PROPERTY prop; + WHV_CAPABILITY_FEATURES features; + + whpx =3D &whpx_global; + /* on arm64 Windows Hypervisor Platform, vGICv3 always used */ + whpx_irqchip_in_kernel =3D true; + + if (!init_whp_dispatch()) { + ret =3D -ENOSYS; + goto error; + } + + whpx->mem_quota =3D ms->ram_size; + + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodeHypervisorPresent, &whpx_cap, + sizeof(whpx_cap), &whpx_cap_size); + if (FAILED(hr) || !whpx_cap.HypervisorPresent) { + error_report("WHPX: No accelerator found, hr=3D%08lx", hr); + ret =3D -ENOSPC; + goto error; + } + + memset(&features, 0, sizeof(features)); + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodeFeatures, &features, sizeof(features), NULL); + if (FAILED(hr)) { + error_report("WHPX: Failed to query capabilities, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + if (!features.Arm64Support) { + error_report("WHPX: host OS exposing pre-release WHPX implementati= on. " + "Please update your operating system to at least build 26100.3= 915"); + ret =3D -EINVAL; + goto error; + } + + hr =3D whp_dispatch.WHvCreatePartition(&whpx->partition); + if (FAILED(hr)) { + error_report("WHPX: Failed to create partition, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + memset(&prop, 0, sizeof(prop)); + prop.ProcessorCount =3D ms->smp.cpus; + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeProcessorCount, + &prop, + sizeof(prop)); + + if (FAILED(hr)) { + error_report("WHPX: Failed to set partition processor count to %u," + " hr=3D%08lx", prop.ProcessorCount, hr); + ret =3D -EINVAL; + goto error; + } + + if (!whpx->kernel_irqchip_allowed) { + error_report("WHPX: on Arm, only kernel-irqchip=3Don is currently = supported"); + ret =3D -EINVAL; + goto error; + } + + memset(&prop, 0, sizeof(prop)); + + hr =3D whp_dispatch.WHvSetupPartition(whpx->partition); + if (FAILED(hr)) { + error_report("WHPX: Failed to setup partition, hr=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + + whpx_memory_init(); + + return 0; + +error: + if (whpx->partition !=3D NULL) { + whp_dispatch.WHvDeletePartition(whpx->partition); + whpx->partition =3D NULL; + } + + return ret; +} --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731590; cv=none; d=zohomail.com; s=zohoarc; b=OCS6Myh7ld1ecGTObhJ6tcQRd0CZwF0FC6svnHLO6tHWXw9RpT1MhpfF1U/R6HmLI0GnN4X2UOqCB8vUkM3BXIxqCp51l2Qtx1HH22yIYabB5G21FAc+aTeU1RCQ3eB1IMG+CpQXV7cGpiNj84iOhSHMDMrqMvSCf8xKdfjFLcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731590; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=73Gszeg/ABaJHBRXvm523fWNFo3Mo1lJgEc7Wi/TY9M=; b=QhZFdaAfbeVHhIaUD9CesAqNEK2b+kKjDKo3QGII5YYLJlmZAN3q+Biez5PCQ8anoGmTEwx+/z9X6VeB8bDqvtnZmR9NQotQseeYldZlomtBr2fsnpp6k2iXfCweoiHqUa5iNcozUoJs+4nFvMDXl+K+PRWACUX3tk+lfEUmWFI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731590548607.0156929272995; Tue, 10 Feb 2026 05:53:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAD-00026O-Ot; Tue, 10 Feb 2026 08:52:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAC-00022p-Ts for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:24 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAB-0006Lp-9S for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:24 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4801c2fae63so46995605e9.2 for ; Tue, 10 Feb 2026 05:52:21 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731541; x=1771336341; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=73Gszeg/ABaJHBRXvm523fWNFo3Mo1lJgEc7Wi/TY9M=; b=H7ZFiOXlf6v7R5KUS3avqXKuCAzCcw6qNOqoBvAGF3d6JHNw0EuIRh6zyHk2AlssPr zNPCyFFEbNAKfzwczRE2EDd82O+StZ4PvH2hsEv6AiTkRyi43cfDlWERwz7VDXGCxw5a kldNqapabjNMO3BD/0Hmw11akIo9boGfxSJuvSEF/UqbPl6k4v/uno+onNbvJl5efwY9 MaRTCv1kK8MT+5ysdW9KAtZZgP+q/mvouAiE3MqSFR+EYN3URT4ZMZOV9pb0urc/tf11 MLYJ1XEESRhiH4WgiD2xP/mvAAxyRn/ns/rBbEjWzwN3416GDGZVpNxlr1BZCqgOJzej jpmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731541; x=1771336341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=73Gszeg/ABaJHBRXvm523fWNFo3Mo1lJgEc7Wi/TY9M=; b=BEEdWbr741bjVePZScFCeXeY7EXqKb9iQhicI4ZjflzSmVDEfZ885+KwNZbYF9t8be eWkUZBT0Rn4hL4KJodIvbFxo1lwhKPuqXWdY3UPOLqb7VcqCtulf9SWVJlYGyqpqXh+u KnyZ6fj5ZnsmM7IwhOiphgCJY5oM3RQb6TucjeTbjCG8sd6GY/rZs5oeVNhXvX2BjkhF g2h7hVgvLKGCB3HBPAf7w8v93baHeEphe8+vB2i5ACJP19oUvtrtkPNP4NH0whNFqBns G5fcsBr0glyBlFJ/oam0qhH+x1m35qqWX7X1PzLpmmnFVTNI4UGt7wgErO+wgUT7+EIy bXVA== X-Gm-Message-State: AOJu0YyCdHpGLJ6nPXXdk4G16siaFhg0nA/V31ROxZ26CuwS4q7KyPz5 6bOwa2jD27f/zDmhk1ybDlTAr9NTipGskMY4IH1DaTwuGr8Dtm6e1FFaDjryPiMGXg0YTxHSuQN BJQeK X-Gm-Gg: AZuq6aLf6QMjdzZR1TO0b9919p7U3wCXsqLNClSKxs2qVl2oOX56/jKjqJZDskrEpat d7WKZZLGntaPfkB3xnN/q2mZaGy9lCqNyZaZqPxWd/qS4CIsbkV+ZinvinW55k+UJ1iTVhWR4Iu PNOvwj1xkG0Y3oGsPZBi3sNd0iLmE4T91nebunjLGQ9t9gbUbcFjtR3iGipTk99eH3+u5sBMP+t 0pPnFQyV6p5jn+KwoSCASd9aiJsNigPR2rsAIiO9aVgDK4SLCw4Pr31q7+BnMHKLRY4+6spkkYG JEWsAhseA/xEt7BQls0wU73lfVXcPKorO3IzPLl8vlwwdB+HUtlH6/0Bb518EzE41a0+zQPfcuZ TiOJbcMm6xQG3pH41dwBLhQdiphOHu1Nl4rBwqF/Qji08tdTZ44w4SagNoXLC7Sv08ULuP+pKHF QFBb9QW4iiu8YlySdFBHERkl7/QbAfLNLFyAng805SZM11XYfTGnopPPu4s8ncszH2lxbKAvSL/ b5MpJvuqm8BdLPsmWbnt+nYQxBn+l4= X-Received: by 2002:a05:600c:8b12:b0:480:4be7:4f53 with SMTP id 5b1f17b1804b1-4835083392dmr35903785e9.31.1770731540462; Tue, 10 Feb 2026 05:52:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/26] whpx: change memory management logic Date: Tue, 10 Feb 2026 13:51:55 +0000 Message-ID: <20260210135206.229528-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731591430158500 From: Mohamed Mediouni This allows edk2 to work on Arm, although u-boot is still not functional. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- accel/whpx/whpx-common.c | 99 +++++++++++++++------------------------- 1 file changed, 37 insertions(+), 62 deletions(-) diff --git a/accel/whpx/whpx-common.c b/accel/whpx/whpx-common.c index 827f50f3e0..f018a8f5c7 100644 --- a/accel/whpx/whpx-common.c +++ b/accel/whpx/whpx-common.c @@ -255,89 +255,64 @@ void whpx_vcpu_kick(CPUState *cpu) * Memory support. */ =20 -static void whpx_update_mapping(hwaddr start_pa, ram_addr_t size, - void *host_va, int add, int rom, - const char *name) +static void whpx_set_phys_mem(MemoryRegionSection *section, bool add) { struct whpx_state *whpx =3D &whpx_global; + MemoryRegion *area =3D section->mr; + bool writable =3D !area->readonly && !area->rom_device; + WHV_MAP_GPA_RANGE_FLAGS flags; + uint64_t page_size =3D qemu_real_host_page_size(); + uint64_t gva =3D section->offset_within_address_space; + uint64_t size =3D int128_get64(section->size); HRESULT hr; + void *mem; =20 - /* - if (add) { - printf("WHPX: ADD PA:%p Size:%p, Host:%p, %s, '%s'\n", - (void*)start_pa, (void*)size, host_va, - (rom ? "ROM" : "RAM"), name); - } else { - printf("WHPX: DEL PA:%p Size:%p, Host:%p, '%s'\n", - (void*)start_pa, (void*)size, host_va, name); + if (!memory_region_is_ram(area)) { + if (writable) { + return; + } else if (!memory_region_is_romd(area)) { + add =3D false; + } } - */ =20 - if (add) { - hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, - host_va, - start_pa, - size, - (WHvMapGpaRangeFlagRead | - WHvMapGpaRangeFlagExecute | - (rom ? 0 : WHvMapGpaRangeFlagWri= te))); - } else { + if (!QEMU_IS_ALIGNED(size, page_size) || + !QEMU_IS_ALIGNED(gva, page_size)) { + /* Not page aligned, so we can not map as RAM */ + add =3D false; + } + + if (!add) { hr =3D whp_dispatch.WHvUnmapGpaRange(whpx->partition, - start_pa, - size); + gva, size); + if (FAILED(hr)) { + error_report("WHPX: failed to unmap GPA range"); + abort(); + } + return; } =20 + flags =3D WHvMapGpaRangeFlagRead | WHvMapGpaRangeFlagExecute + | (writable ? WHvMapGpaRangeFlagWrite : 0); + mem =3D memory_region_get_ram_ptr(area) + section->offset_within_regio= n; + + hr =3D whp_dispatch.WHvMapGpaRange(whpx->partition, + mem, gva, size, flags); if (FAILED(hr)) { - error_report("WHPX: Failed to %s GPA range '%s' PA:%p, Size:%p byt= es," - " Host:%p, hr=3D%08lx", - (add ? "MAP" : "UNMAP"), name, - (void *)(uintptr_t)start_pa, (void *)size, host_va, h= r); + error_report("WHPX: failed to map GPA range"); + abort(); } } =20 -static void whpx_process_section(MemoryRegionSection *section, int add) -{ - MemoryRegion *mr =3D section->mr; - hwaddr start_pa =3D section->offset_within_address_space; - ram_addr_t size =3D int128_get64(section->size); - unsigned int delta; - uint64_t host_va; - - if (!memory_region_is_ram(mr)) { - return; - } - - delta =3D qemu_real_host_page_size() - (start_pa & ~qemu_real_host_pag= e_mask()); - delta &=3D ~qemu_real_host_page_mask(); - if (delta > size) { - return; - } - start_pa +=3D delta; - size -=3D delta; - size &=3D qemu_real_host_page_mask(); - if (!size || (start_pa & ~qemu_real_host_page_mask())) { - return; - } - - host_va =3D (uintptr_t)memory_region_get_ram_ptr(mr) - + section->offset_within_region + delta; - - whpx_update_mapping(start_pa, size, (void *)(uintptr_t)host_va, add, - memory_region_is_rom(mr), mr->name); -} - static void whpx_region_add(MemoryListener *listener, MemoryRegionSection *section) { - memory_region_ref(section->mr); - whpx_process_section(section, 1); + whpx_set_phys_mem(section, true); } =20 static void whpx_region_del(MemoryListener *listener, MemoryRegionSection *section) { - whpx_process_section(section, 0); - memory_region_unref(section->mr); + whpx_set_phys_mem(section, false); } =20 static void whpx_transaction_begin(MemoryListener *listener) --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731748; cv=none; d=zohomail.com; s=zohoarc; b=C4v7r0rpaknxyfC8geZCLF7QZ59vpSlYy41mIFZbhjreetRWfNw8Mr5qh7JPbuH+sqWD1yt372lHddboYVVf1UMl/gpOJ48HwceYbwlgYAOzdTmW2Rfm4fFc9SOkwge4Ofi45xtQNnCvd5HqsAQEgcY3xm3/aZ7kMaLf4U4sZqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731748; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=/ItqmxvT2sW8xeL1y52qhG/fYOf0Xbu2AAYt6A/1I0E=; b=V50Mq1MxJkWSDrZj+1T7zxPz14zf/2EqTuXf9B6YaCHsdVBoaVbY/y87IVpxVY1a7QMkWdOZ89qJDfw3yWL8Bsqt4yKVItKiKmfflB0dNBVV4ARY3btOktv86BzWoq5pv8KVEv4keTPHDeGNzv4emSzMox2ddzT/4PB6cbqyhxI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731748847310.6503286578312; Tue, 10 Feb 2026 05:55:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAK-0002Dl-Hi; Tue, 10 Feb 2026 08:52:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAE-00026y-2i for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:26 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAB-0006Lt-A3 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:25 -0500 Received: by mail-wm1-x341.google.com with SMTP id 5b1f17b1804b1-47edd9024b1so52439925e9.3 for ; Tue, 10 Feb 2026 05:52:22 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731541; x=1771336341; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/ItqmxvT2sW8xeL1y52qhG/fYOf0Xbu2AAYt6A/1I0E=; b=xfBUfw6yHIoWTYzb42jdKaEVgkzllMF5sUdzDaD5fogKcRsjwUOZruDCqxCBEgQbRB 1HGvpURe7uBi5ORkpZd+jfspO8UgvX840BN82qKtgVmmj/TqTjQp+jUX0TrP9/wuNzjI 1SWFfjNSnQdKclVkdE7muozX8Ho6IdnN4qVQohXAAlPxdqVnmEMpSvEv4ybGaazNYUr6 E3lhav47JI7pcziTy03CiPUWEPnIF3Nqoqurd4M9U+j4zY3IAieKzDEl2KzKUNtcOAOv kcfwu+PJ8tjQe+Yghg5MJdcXtII+ov1fyYaBOnCGXYI7XagKXDBni5jkE8b92EJ0jZAC 56Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731541; x=1771336341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=/ItqmxvT2sW8xeL1y52qhG/fYOf0Xbu2AAYt6A/1I0E=; b=Y1cKuORmqzwq72B+vri5UneG8v3Lo67B6yzIZr+MsxjJkbm3H1VmU7YDa4nBxT0Vid 1pHk0QnuPWPoB4X2xjk2d1ByLsmv1DnbCXWPl0SMvmwezk5IU9jQSnKWmA0ry5L+JxCn 2+nVH1CLvI9q2y7XvsS4mXb+UKzUPRH5jmzSQqo2Ya/nN5EHr+5lgglsbnDn30r1o4U+ 4qGM64WWiR3o8sTDSuHYmSo+LxVEptsIU6+ZFqIlaTdDIF1/Ctw+ZN3Py/0DmmPxC+YR gMqM6t9NA3Am4Upfnj2aWA/gWOJY1kJUnHdVfpw/bW8HfzGTXAKSMGbHWQSn3Azf+Vgg ZOvw== X-Gm-Message-State: AOJu0Yzsgtp4qs4BKSnkcSyr6yVFgW9lT9flzO/O+o4UuMgvFlZkRPwM tNpRQlqbsuuviW+E5BBOUmX3UgNG+Nk+dn1ciO5vJJUxaSHfzAasH+HOnA1vsdwuAAeybYip5h9 I/Xgan8k= X-Gm-Gg: AZuq6aIHlxP63xA11rHEhaqyqNZk1eghG0pKmbX++ept8ywKOztalAWNq7G9zonxWnc c0FVaIo6vGWLbT/8G2jGVi2dkWORVmHsIBiUDH+wHRDn2N1Yf1jK9qhta7S0CAA/YJPV3bH5qIu 5NpgqyzrA30Z466KOvDe2RzR9ux3K7KLgmZ/fhBs+iWFcSXIiNfGRAGpw3JFMvlzubRflzuOPLY M0aiiBtuNmFbfGevAeAzDLQ60nFK+9YcfKgkqBa0LU3pcgLTDjL2jirCxdjDLAMTblkTiwXqRbJ qqN+ndfV5a5zjvruzjYSYmCxlmeJLpvloVlmN0SR32oH89qpOpFJBMG8JvRwwPytN78Hoc2Ly7T +MTaoosTmLfKpz9GxJl7z6fx6kMcL8wOHrwyJOSBjPXG1WwYeEWRTzNUbg7X4xoI/kBmCLnVjOJ Ymm4184D5/k7ICW33rA5aPQAB2f/TUTRFCde49d3Lw3Fh7eNqEw3BZYFsRJuy6gv8TYNnvo1+Wg ghdqklhU8kvzy/U4JtzBufC0yQNFk4= X-Received: by 2002:a05:600c:5253:b0:480:6941:d38b with SMTP id 5b1f17b1804b1-4832021cdcamr201941325e9.30.1770731541238; Tue, 10 Feb 2026 05:52:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/26] target/arm: cpu: mark WHPX as supporting PSCI 1.3 Date: Tue, 10 Feb 2026 13:51:56 +0000 Message-ID: <20260210135206.229528-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731750430154100 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Hyper-V supports PSCI 1.3, and that implementation is exposed through WHPX. Signed-off-by: Mohamed Mediouni Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c535b292d9..077f1f9a74 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -23,6 +23,7 @@ #include "qemu/timer.h" #include "qemu/log.h" #include "exec/page-vary.h" +#include "system/whpx.h" #include "target/arm/idau.h" #include "qemu/module.h" #include "qapi/error.h" @@ -1143,6 +1144,8 @@ static void arm_cpu_initfn(Object *obj) if (tcg_enabled() || hvf_enabled()) { /* TCG and HVF implement PSCI 1.1 */ cpu->psci_version =3D QEMU_PSCI_VERSION_1_1; + } else if (whpx_enabled()) { + cpu->psci_version =3D QEMU_PSCI_VERSION_1_3; } } =20 --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731717; cv=none; d=zohomail.com; s=zohoarc; b=jyOQgcQy2tErUTg2LXDLzUjPwlISPYZvVqF5A4zj2lbpbtfK1T7ph4wVf2YEikjkqXoNPlk8EechRigpUOPBpjQBBIFy+j+fXzP0jBN6tgWoNy9YEc1nzLuckNM5gl74TL4bbIXWlquazRjnr4Lez7+cUzTxw4A7K1llJxQ0qwI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731717; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=wdfCt/hYND0Wf2q+qK3U6LW7wpQkulM9WJ6MRgTXjCM=; b=EqkwZ4EbK37o/Zq9sQ1ZMM6IciB2A7WpvkIANnHGQJffxY5rp8pFQ+PM5jak0wdg/YC4+38ieXbPdY0eeYkLCUjERsmJTcokjfWxoxsOUOPsWf0fIrDZ6byIRURPmxsver5jgSm+lDz3ycvxtjRlF+hmbE/2pt+bNKnJOQlcZYM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731717546420.78827857996237; Tue, 10 Feb 2026 05:55:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAH-0002BJ-2w; Tue, 10 Feb 2026 08:52:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAE-00028g-O8 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:26 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAB-0006M0-LI for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:26 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-480142406b3so43928015e9.1 for ; Tue, 10 Feb 2026 05:52:23 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731542; x=1771336342; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wdfCt/hYND0Wf2q+qK3U6LW7wpQkulM9WJ6MRgTXjCM=; b=IeldHlK0Bl+95Tg8R0uGVWTWEr9hEmF47bIvO+3i6PBnWQIg/AuG2Vh7wL6SOpwFzh U70GsckX8f+TKWRcu9lqmA8vetT2Q/CiE2IiJEu9N3Ir/7EP/murEVckumoN6ixxfNM5 6wMMha5ZUVvnBAu3dh0fKaqHG8P6g113pBPc3szkRZcF3/4W1WlA/SbFiMqvVUYQ6fHY mUqBONc146WGMGCkpeX9MXmNqImjquonJcIGfdoRbeBADfZ9PFUxaDf+OYQByNKLNixT EUnX6wThEG+VigITEbdeCDV8pWKPOJNATJdhOccgoK3IvV/ESEd2TSzOTJiyqVxbVqf2 B6PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731542; x=1771336342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=wdfCt/hYND0Wf2q+qK3U6LW7wpQkulM9WJ6MRgTXjCM=; b=vzSFedYPCOJwT1tj3PSlMhBh9Hny24fs/opwQQq/xLnkQoqhQfyqbCes38oHOXpK+s KC5a3BfpWoF5czxRQrYZ33n1gabv3ZVdwYYLOSM0ef/9PmMQFaKblZ8aVKpClhbKXh1s eIKy10VL1LzB1bVX+113VwA/mhzZ8nnuz/OExnbp4XDViuGmFZwDXYM9irZHc9CBqX17 RFQAYpAw/oMiHkPh/4scOTsWVbA2vwD5CKibb6bmVatm453KB7bU+uVf3kZTRBURWOql WiYMS449bYf3t8VeQl5nJ5mGTTENDOH5csAc9mWmS9QIXudxtRv2pgIjVC0rhnMbbl82 O4Qg== X-Gm-Message-State: AOJu0Yw2MqXt+1gun527YOwMA9dzY50gSp8tgpilDit2IoBVxMxzAG1N mNy6OrChPnIM+FekRQZYLtSrkXf3pAZ/lwH/ogRBIYOw6Hdi3nB+rePwqmu05kBuptQYTYYqfA5 +6PT0 X-Gm-Gg: AZuq6aIcQQ8SuR/DHvGhzlHob426eP57UPdTwqClt9S/l2vWxbduAKI3MjhUweYpW5o +tqv+uyxt2W6YMB7WA+pqGqvEDyCjXO03XnB033ui6rIBuiHmwt+VOb5gUFGoHcZG81XX1NXaM3 KORDKt+zpdEtt4JUud5Dnrb6BFHP3rGiXQ7mtFinkkJb8w1oQWiMyBHsbFv+Npu8jwSXAjElgb/ SePFj3eniNkphNALM7NOeTkn09BQlq2tiOCUuQ/F9fs0du6/PUKH6ZWDgT4hCS+uwXgECixqWcq aRSq6to+vDvvJuiF7vrAHy+gBo8y/llzzPj+YppGgkPTw8qZgnNMcPNyH3o00zO/jeSYJNaOBM7 uIHNebbRQt8JBArut5UXVXQIxJsXIC9F+z+YYS86WimByISlvKdmrEeq0OGc2t7k5hUoEA33bdT 5C2lLuPwrwjvle4GkBVMHUyLny6BGJgT7yoCOhEs9j+uKADpW888dzS6uOmOgvPXnlSOupFFMNh 7mwRPmEupm/kK3nv+piqLwYnbTSlSg= X-Received: by 2002:a05:600c:190f:b0:480:52fd:d2e4 with SMTP id 5b1f17b1804b1-4835056df77mr29591855e9.0.1770731542010; Tue, 10 Feb 2026 05:52:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/26] whpx: arm64: clamp down IPA size Date: Tue, 10 Feb 2026 13:51:57 +0000 Message-ID: <20260210135206.229528-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731727617154101 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Code taken from HVF and adapted for WHPX use. Note that WHPX doesn't have a default vs maximum IPA distinction. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Signed-off-by: Peter Maydell --- hw/arm/virt.c | 32 ++++++++++++++++++++++++++ include/hw/core/boards.h | 1 + target/arm/whpx/meson.build | 2 ++ target/arm/whpx/whpx-all.c | 45 +++++++++++++++++++++++++++++++++++++ target/arm/whpx/whpx-stub.c | 15 +++++++++++++ target/arm/whpx_arm.h | 16 +++++++++++++ 6 files changed, 111 insertions(+) create mode 100644 target/arm/whpx/whpx-stub.c create mode 100644 target/arm/whpx_arm.h diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b7eb0cec5e..77832b566e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -72,6 +72,7 @@ #include "hw/core/irq.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "whpx_arm.h" #include "hw/firmware/smbios.h" #include "qapi/visitor.h" #include "qapi/qapi-visit-common.h" @@ -3360,6 +3361,36 @@ static int virt_kvm_type(MachineState *ms, const cha= r *type_str) return fixed_ipa ? 0 : requested_pa_size; } =20 +static int virt_whpx_get_physical_address_range(MachineState *ms) +{ + VirtMachineState *vms =3D VIRT_MACHINE(ms); + + int max_ipa_size =3D whpx_arm_get_ipa_bit_size(); + + /* We freeze the memory map to compute the highest gpa */ + virt_set_memmap(vms, max_ipa_size); + + int requested_ipa_size =3D 64 - clz64(vms->highest_gpa); + + /* + * If we're <=3D the default IPA size just use the default. + * If we're above the default but below the maximum, round up to + * the maximum. whpx_arm_get_max_ipa_bit_size() conveniently only + * returns values that are valid ARM PARange values. + */ + if (requested_ipa_size <=3D max_ipa_size) { + requested_ipa_size =3D max_ipa_size; + } else { + error_report("-m and ,maxmem option values " + "require an IPA range (%d bits) larger than " + "the one supported by the host (%d bits)", + requested_ipa_size, max_ipa_size); + return -1; + } + + return requested_ipa_size; +} + static int virt_hvf_get_physical_address_range(MachineState *ms) { VirtMachineState *vms =3D VIRT_MACHINE(ms); @@ -3459,6 +3490,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; mc->hvf_get_physical_address_range =3D virt_hvf_get_physical_address_r= ange; + mc->whpx_get_physical_address_range =3D virt_whpx_get_physical_address= _range; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; hc->pre_plug =3D virt_machine_device_pre_plug_cb; diff --git a/include/hw/core/boards.h b/include/hw/core/boards.h index 07f8938752..0b2aefb126 100644 --- a/include/hw/core/boards.h +++ b/include/hw/core/boards.h @@ -278,6 +278,7 @@ struct MachineClass { void (*wakeup)(MachineState *state); int (*kvm_type)(MachineState *machine, const char *arg); int (*hvf_get_physical_address_range)(MachineState *machine); + int (*whpx_get_physical_address_range)(MachineState *machine); =20 BlockInterfaceType block_default_type; int units_per_default_bus; diff --git a/target/arm/whpx/meson.build b/target/arm/whpx/meson.build index 1de2ef0283..3df632c9d3 100644 --- a/target/arm/whpx/meson.build +++ b/target/arm/whpx/meson.build @@ -1,3 +1,5 @@ arm_system_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', )) + +arm_common_system_ss.add(when: 'CONFIG_WHPX', if_false: files('whpx-stub.c= ')) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 192d7ec7a8..850f6ec81f 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -35,6 +35,7 @@ #include "system/whpx-accel-ops.h" #include "system/whpx-all.h" #include "system/whpx-common.h" +#include "whpx_arm.h" #include "hw/arm/bsa.h" #include "arm-powerctl.h" =20 @@ -633,6 +634,40 @@ static void whpx_cpu_update_state(void *opaque, bool r= unning, RunState state) { } =20 +uint32_t whpx_arm_get_ipa_bit_size(void) +{ + WHV_CAPABILITY whpx_cap; + UINT32 whpx_cap_size; + HRESULT hr; + hr =3D whp_dispatch.WHvGetCapability( + WHvCapabilityCodePhysicalAddressWidth, &whpx_cap, + sizeof(whpx_cap), &whpx_cap_size); + if (FAILED(hr)) { + error_report("WHPX: failed to get supported " + "physical address width, hr=3D%08lx", hr); + } + + /* + * We clamp any IPA size we want to back the VM with to a valid PARange + * value so the guest doesn't try and map memory outside of the valid = range. + * This logic just clamps the passed in IPA bit size to the first valid + * PARange value <=3D to it. + */ + return round_down_to_parange_bit_size(whpx_cap.PhysicalAddressWidth); +} + +static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) +{ + uint32_t ipa_size =3D whpx_arm_get_ipa_bit_size(); + uint64_t id_aa64mmfr0; + + /* Clamp down the PARange to the IPA size the kernel supports. */ + uint8_t index =3D round_down_to_parange_index(ipa_size); + id_aa64mmfr0 =3D GET_IDREG(isar, ID_AA64MMFR0); + id_aa64mmfr0 =3D (id_aa64mmfr0 & ~R_ID_AA64MMFR0_PARANGE_MASK) | index; + SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); +} + int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; @@ -706,6 +741,7 @@ int whpx_init_vcpu(CPUState *cpu) val.Reg64 =3D deposit64(arm_cpu->mp_affinity, 31, 1, 1 /* RES1 */); whpx_set_reg(cpu, WHvArm64RegisterMpidrEl1, val); =20 + clamp_id_aa64mmfr0_parange_to_ipa_size(&arm_cpu->isar); return 0; } =20 @@ -722,6 +758,8 @@ int whpx_accel_init(AccelState *as, MachineState *ms) UINT32 whpx_cap_size; WHV_PARTITION_PROPERTY prop; WHV_CAPABILITY_FEATURES features; + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + int pa_range =3D 0; =20 whpx =3D &whpx_global; /* on arm64 Windows Hypervisor Platform, vGICv3 always used */ @@ -732,6 +770,13 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 + if (mc->whpx_get_physical_address_range) { + pa_range =3D mc->whpx_get_physical_address_range(ms); + if (pa_range < 0) { + return -EINVAL; + } + } + whpx->mem_quota =3D ms->ram_size; =20 hr =3D whp_dispatch.WHvGetCapability( diff --git a/target/arm/whpx/whpx-stub.c b/target/arm/whpx/whpx-stub.c new file mode 100644 index 0000000000..32e434a5f6 --- /dev/null +++ b/target/arm/whpx/whpx-stub.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * WHPX stubs for ARM + * + * Copyright (c) 2025 Mohamed Mediouni + * + */ + +#include "qemu/osdep.h" +#include "whpx_arm.h" + +uint32_t whpx_arm_get_ipa_bit_size(void) +{ + g_assert_not_reached(); +} diff --git a/target/arm/whpx_arm.h b/target/arm/whpx_arm.h new file mode 100644 index 0000000000..de7406b66f --- /dev/null +++ b/target/arm/whpx_arm.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * WHPX support -- ARM specifics + * + * Copyright (c) 2025 Mohamed Mediouni + * + */ + +#ifndef QEMU_WHPX_ARM_H +#define QEMU_WHPX_ARM_H + +#include "target/arm/cpu-qom.h" + +uint32_t whpx_arm_get_ipa_bit_size(void); + +#endif --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731629; cv=none; d=zohomail.com; s=zohoarc; b=nr9HQcybitedZkjoCAOkja4W7dxNoYFDnflohuXF2VyQsyhNAAx5Nv2y4KTjKIWUjAyhM/IDFwVyDKTuS6SCePHmGdTOzQf1D6m0ThUOrFHXOMd2Gqy96YlixXWqjAeT3QhqBRobob+vAnGWWRLH5GnU8Eer4FNbOkZWLtTSu00= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731629; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ZzT5BD5nzWQigc6t+4Cb7vywT9PeeHYQne2OSAJAPZo=; b=P1AVBUhk970zCcD6wdLBr7N+jIru2uHViQ0J4tHowfEyW0qX3oG+Au/ss8pz0vqo7zWnYobbGREXabyOycQDi8BjghZW1dKLUQxL3KDof/nGjXY5cVTq/Y5MBDcTDon5WlQNS82i5sR0y2hzApIwXnD6JMvE5emDwD/ftMDpFmU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731629717239.856227105764; Tue, 10 Feb 2026 05:53:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAJ-0002Da-UG; Tue, 10 Feb 2026 08:52:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAF-00029S-00 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:27 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAC-0006MH-FV for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:26 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-48327b8350dso35013015e9.1 for ; Tue, 10 Feb 2026 05:52:24 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731543; x=1771336343; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZzT5BD5nzWQigc6t+4Cb7vywT9PeeHYQne2OSAJAPZo=; b=hklws+M7rLRW90l8I+LYEBiX3EvX10LzpFLJDXRjYRL7lOk/p7t7u7yyTnrzx6/Jmp PvOyKlHuisibr2xMTroKJ6Cq1+HOU5umsMtLnMQkX9yWK9MfSNUNz3bjqkuccWyk5f93 xt5Fk2cKkGVFR4ujm+ZC6axPPmZXZpeqcPn61e4z6+YPqsyZI4HpFMonsj/n91HT9j+g 1ty0m5AG2wJ2c2XlAiviuMLT6sPXVkNuLv9PWbBUBZmucayvgKj2rEnO6cKprElTc7vi O+2VIFGNv7EqAmewDlGJjAkJg3Uc+inhuvdsO8dCm3/Y1C43+E3osWlSEMWXEtfsfEeZ itHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731543; x=1771336343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ZzT5BD5nzWQigc6t+4Cb7vywT9PeeHYQne2OSAJAPZo=; b=p96UcK0HNQYTPDBkSynVkhNLt97Q0yJHTaLoHEBB3mxNjG0t026Zuhu92kTT3faUzv s3fWluzhJIYWYRt5huQa7l9ebn8xh6UlU9WjMmcXLyXPaynn5LgIaOki20hhYd7tGKuL W0sSf/0q2/DZxV36FGpz3fze4nJ559ag0k8eDOQFVLwDfPYMART3SRUNcAIy2rwkVG59 Pe9FglNjF9yMZg3iUugVpVtXd+QSJhvK6Q/st4za4u4qyllycn2h5g4gBNhbhUewzCrU 3MVb99931myNU0a0pmmM9//OB24+WmPLgp1hr+mOQqiWtVDVOrNotXQK1DHSXmm/gAz5 0l8w== X-Gm-Message-State: AOJu0Yw7aTBVAkt4U41T/kRsWi4QHOK+i4QzD8sY0kqoYVWn0lVUkrOa UXgLvXn064tB5JlyaazTveFJkiWGRKk7FbUyjcq+gahqxCW1sLti4LjEzGOVji9xDivNWslGSX5 6MmfZ X-Gm-Gg: AZuq6aJeBEyD39R3XGfdW3jMVBJdETE4TbjBMltz4IRDps4P3yp3T8/2I88Ryg9zXe0 WrPB6bBF4XVbkpsCsNwsoMMmqy3pPU3TsTqYcx9iWvfPwCZkTp2CohFNBIU8Am4cU1JcUj0GSeJ /z1elXWVcNkAKYH35ubOfS2V+G3I8UhHLNt+qAnJfupLNMala+95+Aq/q3bro3WydWT8woWDwXJ F7ENsWmdtqv3ZztZ3Fomm9KJ8RzyYdoOIRMh+0uNxN9PdqmS9kDqtyIr++Jci4mSN2vApsoGRcu nZkoSphYLVBxGY6pIT79dvNeHOtP3Rn34QH/JpzS+jtXlsFJw33WgEp2XY8yoSQ0YemjrEMAyeC 15YmN2n+eWWM0n7AAk6sXDvGJ+FmSaXd/C36ikLHU6CTiOaA1d+QtbYZonM3Fvz3nXRSKB2WnFF rYP9pnYBvI/+cQT2dtzNr7yU92RTjXmMx9K6v/FjVB8IqL+uLunsNh5Q/RRsyhe1IJt+VFUsCQ4 Wq1NAu4Xm41uaRuYciWY+AzBej5st4= X-Received: by 2002:a05:600c:154b:b0:47a:81b7:9a20 with SMTP id 5b1f17b1804b1-483201e17b5mr182157255e9.9.1770731542930; Tue, 10 Feb 2026 05:52:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/26] hw/arm, accel/hvf, whpx: unify get_physical_address_range between WHPX and HVF Date: Tue, 10 Feb 2026 13:51:58 +0000 Message-ID: <20260210135206.229528-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731631762158500 From: Mohamed Mediouni Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- accel/hvf/hvf-all.c | 7 +++++-- hw/arm/virt.c | 43 +++++--------------------------------- include/hw/core/boards.h | 4 ++-- include/system/hvf_int.h | 4 ++++ target/arm/hvf-stub.c | 20 ------------------ target/arm/hvf/hvf.c | 6 +++--- target/arm/hvf_arm.h | 3 --- target/arm/meson.build | 1 - target/arm/whpx/whpx-all.c | 5 +++-- target/i386/hvf/hvf.c | 11 ++++++++++ 10 files changed, 33 insertions(+), 71 deletions(-) delete mode 100644 target/arm/hvf-stub.c diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c index 0fbe27dfa2..033c677b6f 100644 --- a/accel/hvf/hvf-all.c +++ b/accel/hvf/hvf-all.c @@ -18,6 +18,7 @@ #include "system/hvf_int.h" #include "hw/core/cpu.h" #include "hw/core/boards.h" +#include "target/arm/hvf_arm.h" #include "trace.h" =20 bool hvf_allowed; @@ -186,8 +187,10 @@ static int hvf_accel_init(AccelState *as, MachineState= *ms) int pa_range =3D 36; MachineClass *mc =3D MACHINE_GET_CLASS(ms); =20 - if (mc->hvf_get_physical_address_range) { - pa_range =3D mc->hvf_get_physical_address_range(ms); + + if (mc->get_physical_address_range) { + pa_range =3D mc->get_physical_address_range(ms, + hvf_arch_get_default_ipa_bit_size(), hvf_arch_get_max_ipa_bit_= size()); if (pa_range < 0) { return -EINVAL; } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 77832b566e..5c31695d37 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3361,12 +3361,11 @@ static int virt_kvm_type(MachineState *ms, const ch= ar *type_str) return fixed_ipa ? 0 : requested_pa_size; } =20 -static int virt_whpx_get_physical_address_range(MachineState *ms) +static int virt_get_physical_address_range(MachineState *ms, + int default_ipa_size, int max_ipa_size) { VirtMachineState *vms =3D VIRT_MACHINE(ms); =20 - int max_ipa_size =3D whpx_arm_get_ipa_bit_size(); - /* We freeze the memory map to compute the highest gpa */ virt_set_memmap(vms, max_ipa_size); =20 @@ -3375,39 +3374,8 @@ static int virt_whpx_get_physical_address_range(Mach= ineState *ms) /* * If we're <=3D the default IPA size just use the default. * If we're above the default but below the maximum, round up to - * the maximum. whpx_arm_get_max_ipa_bit_size() conveniently only - * returns values that are valid ARM PARange values. - */ - if (requested_ipa_size <=3D max_ipa_size) { - requested_ipa_size =3D max_ipa_size; - } else { - error_report("-m and ,maxmem option values " - "require an IPA range (%d bits) larger than " - "the one supported by the host (%d bits)", - requested_ipa_size, max_ipa_size); - return -1; - } - - return requested_ipa_size; -} - -static int virt_hvf_get_physical_address_range(MachineState *ms) -{ - VirtMachineState *vms =3D VIRT_MACHINE(ms); - - int default_ipa_size =3D hvf_arm_get_default_ipa_bit_size(); - int max_ipa_size =3D hvf_arm_get_max_ipa_bit_size(); - - /* We freeze the memory map to compute the highest gpa */ - virt_set_memmap(vms, max_ipa_size); - - int requested_ipa_size =3D 64 - clz64(vms->highest_gpa); - - /* - * If we're <=3D the default IPA size just use the default. - * If we're above the default but below the maximum, round up to - * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only - * returns values that are valid ARM PARange values. + * the maximum. hvf/whpx_arch_get_max_ipa_bit_size() conveniently only + * return values that are valid ARM PARange values. */ if (requested_ipa_size <=3D default_ipa_size) { requested_ipa_size =3D default_ipa_size; @@ -3489,8 +3457,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) mc->get_valid_cpu_types =3D virt_get_valid_cpu_types; mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; - mc->hvf_get_physical_address_range =3D virt_hvf_get_physical_address_r= ange; - mc->whpx_get_physical_address_range =3D virt_whpx_get_physical_address= _range; + mc->get_physical_address_range =3D virt_get_physical_address_range; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; hc->pre_plug =3D virt_machine_device_pre_plug_cb; diff --git a/include/hw/core/boards.h b/include/hw/core/boards.h index 0b2aefb126..26e0879e1a 100644 --- a/include/hw/core/boards.h +++ b/include/hw/core/boards.h @@ -277,8 +277,8 @@ struct MachineClass { void (*reset)(MachineState *state, ResetType type); void (*wakeup)(MachineState *state); int (*kvm_type)(MachineState *machine, const char *arg); - int (*hvf_get_physical_address_range)(MachineState *machine); - int (*whpx_get_physical_address_range)(MachineState *machine); + int (*get_physical_address_range)(MachineState *machine, + int default_ipa_size, int max_ipa_size); =20 BlockInterfaceType block_default_type; int units_per_default_bus; diff --git a/include/system/hvf_int.h b/include/system/hvf_int.h index 96790b4938..2621164cb2 100644 --- a/include/system/hvf_int.h +++ b/include/system/hvf_int.h @@ -57,6 +57,8 @@ void assert_hvf_ok_impl(hv_return_t ret, const char *file= , unsigned int line, const char *hvf_return_string(hv_return_t ret); int hvf_arch_init(void); hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range); +uint32_t hvf_arch_get_default_ipa_bit_size(void); +uint32_t hvf_arch_get_max_ipa_bit_size(void); void hvf_kick_vcpu_thread(CPUState *cpu); =20 /* Must be called by the owning thread */ @@ -107,5 +109,7 @@ int hvf_update_guest_debug(CPUState *cpu); bool hvf_arch_supports_guest_debug(void); =20 bool hvf_arch_cpu_realize(CPUState *cpu, Error **errp); +uint32_t hvf_arch_get_default_ipa_bit_size(void); +uint32_t hvf_arch_get_max_ipa_bit_size(void); =20 #endif diff --git a/target/arm/hvf-stub.c b/target/arm/hvf-stub.c deleted file mode 100644 index ff137267a0..0000000000 --- a/target/arm/hvf-stub.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * QEMU Hypervisor.framework (HVF) stubs for ARM - * - * Copyright (c) Linaro - * - * SPDX-License-Identifier: GPL-2.0-or-later - */ - -#include "qemu/osdep.h" -#include "hvf_arm.h" - -uint32_t hvf_arm_get_default_ipa_bit_size(void) -{ - g_assert_not_reached(); -} - -uint32_t hvf_arm_get_max_ipa_bit_size(void) -{ - g_assert_not_reached(); -} diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 9ce720793d..1b19d9713e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -825,7 +825,7 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) { uint32_t ipa_size =3D chosen_ipa_bit_size ? - chosen_ipa_bit_size : hvf_arm_get_max_ipa_bit_size(); + chosen_ipa_bit_size : hvf_arch_get_max_ipa_bit_size(); uint64_t id_aa64mmfr0; =20 /* Clamp down the PARange to the IPA size the kernel supports. */ @@ -921,7 +921,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) return r =3D=3D HV_SUCCESS; } =20 -uint32_t hvf_arm_get_default_ipa_bit_size(void) +uint32_t hvf_arch_get_default_ipa_bit_size(void) { uint32_t default_ipa_size; hv_return_t ret =3D hv_vm_config_get_default_ipa_size(&default_ipa_siz= e); @@ -930,7 +930,7 @@ uint32_t hvf_arm_get_default_ipa_bit_size(void) return default_ipa_size; } =20 -uint32_t hvf_arm_get_max_ipa_bit_size(void) +uint32_t hvf_arch_get_max_ipa_bit_size(void) { uint32_t max_ipa_size; hv_return_t ret =3D hv_vm_config_get_max_ipa_size(&max_ipa_size); diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea82f2691d..5d19d82e5d 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -22,7 +22,4 @@ void hvf_arm_init_debug(void); =20 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 -uint32_t hvf_arm_get_default_ipa_bit_size(void); -uint32_t hvf_arm_get_max_ipa_bit_size(void); - #endif diff --git a/target/arm/meson.build b/target/arm/meson.build index fe396c4318..6e0e504a40 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -41,7 +41,6 @@ arm_common_system_ss.add(files('cpu.c')) arm_common_system_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c')) arm_common_system_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) -arm_common_system_ss.add(when: 'CONFIG_HVF', if_false: files('hvf-stub.c')) arm_common_system_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: files('common-semi-target.c')) arm_common_system_ss.add(files( diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 850f6ec81f..6067918b27 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -770,8 +770,9 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 - if (mc->whpx_get_physical_address_range) { - pa_range =3D mc->whpx_get_physical_address_range(ms); + if (mc->get_physical_address_range) { + pa_range =3D mc->get_physical_address_range(ms, + whpx_arm_get_ipa_bit_size(), whpx_arm_get_ipa_bit_size()); if (pa_range < 0) { return -EINVAL; } diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 7cfaee389e..ce54020f00 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -228,6 +228,17 @@ int hvf_arch_init(void) return 0; } =20 +/* 48-bit on all Intel Macs. Function currently unused. */ +uint32_t hvf_arch_get_default_ipa_bit_size(void) +{ + g_assert_not_reached(); +} + +uint32_t hvf_arch_get_max_ipa_bit_size(void) +{ + g_assert_not_reached(); +} + hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range) { return hv_vm_create(HV_VM_DEFAULT); --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731700; cv=none; d=zohomail.com; s=zohoarc; b=MnIdfRb13HV88xNy5T5k7X/uph6rRniQdV04EtUW7m2jXuJu6lhu2jPMUuMn5lM2eqRT26HXW+2NzMVkoU9Mmk+TqwVi23Sx8k8lBp1WzqDrHjq+CPamUpNeDpi38bGR6EtW9xOZ60/x+wEt4Of3ao4Lg9gJiM7xivPYoo/ILlk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731700; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=nVy2RmUvOgKqnSfaMqTS5rYyZ2kmyUTErzns4X+yjy4=; b=kw/y05r4RzDkXw5mCDgd8RCokSxh6fXN5Vf9+yCsqK/XYUJKisLYpLynnSiNES+PMrVsIFB65MGNvfTVPa7m+oO2W+6pqtHgiNYusmhFvKafITiDZ7Q7UmQG9+58Ysox7oM3PkKVA6HxCnw3DpYC/P8JYPSUxpC1KfHzmWmzdKE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731700492308.761539370219; Tue, 10 Feb 2026 05:55:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAI-0002CF-HU; Tue, 10 Feb 2026 08:52:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAG-0002As-GM for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:28 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAD-0006MN-R9 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:28 -0500 Received: by mail-wm1-x343.google.com with SMTP id 5b1f17b1804b1-480706554beso43998855e9.1 for ; Tue, 10 Feb 2026 05:52:25 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731544; x=1771336344; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nVy2RmUvOgKqnSfaMqTS5rYyZ2kmyUTErzns4X+yjy4=; b=VeMHsaF9D2ldat8qK2CVdnQwdOUzUpdeJFAngSFYQlyAMwLlmmC68ego4lCO+VEHOj 5dE8VhDLRdBhOxx2AbS4kj4GDvFe0x57NeQB1S07K/vU4+65q+WxBc87YfXnDUP/Ng0+ eaLkHERxAsskp+PrZVyHJGko2/z4PjXUcN5+UbS3/qYyh8VoJZKrdV+uG9tV90azB5IS C7RZhpF/yNFDRqRA37ozp8Sh3D1ESYe54Hj4O+XsVe/cF1dBVTKqz+gsNe2zCMCPlEsF j/3N+Es/SbwrgtYzMi1uK/Mpzb6jlVxy8lPjYCUoO5N2EWP0SJoZJgSOtb0vpXQ6r21o dZJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731544; x=1771336344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=nVy2RmUvOgKqnSfaMqTS5rYyZ2kmyUTErzns4X+yjy4=; b=ugWrZvRK5tW/rExeO3aekRxFDyJAIUDANdSeFrxLJfpMCUD42G1bOQqubIXyBQe8So 8PLS8zq+880Lwi/62h1+ugqy39py+W1jcuLO3QUShPOMpQcYNoQ7i11pdguG9k8OMMGH Rp1C3bEjgakzm8AS7dgySZ+fluJX7qf5YpEdcbefbbbinwDsHP8QvGK4pSF/aiP2rPgu r4MlaxWPbpQANv6HbtGDk25hiWws8IA7+FP+5i2su7FKlCjaE4qK3Jo8/rJ0l5smE/Oe uFFPVhzjbBkcEd+eZ3tiOfmLC1D9LNPQGCDjMIMmnVa6WapA0enXQ2j2ZvbILmCRmsQT qISQ== X-Gm-Message-State: AOJu0Ywy2B5Ebv+LLdrk5AXwgNabKCd4UCilBwY+LSkx8hF739FgUE8L fKKa8zyn12+gumJ3MJhqcXLJIc2ZwY8XAyHzQ/mrng8ylkEz4rHgNAwEV8mAuMhzyGUz8wDJLnG vzgdI X-Gm-Gg: AZuq6aIj0lrl7Cbo0753RtOg9c9gv9ayifcix/HOpCwu01MlPg5nE/Rr6Tse00Yeakq 7Zt8r/BniQd3LcpU9Qhb8k3Xp7+rPb+EY4bDVVXN/9I+p/UBHF+kcuFeUK3k6x9NX0WxzNOXwrc iF/tb7nhcFP8p2f4He0Bte7+ZUA2lMackklyZd4ysIxrgo8JM6zX0JBde8DRuSgsI7NTxzxo7RC y7ewNmOMyZGbpqPgSl8ZHYyy9+lx2nmY8k0E1kusNLuVYK/0wA0rd4w+BmSR5vSiJ9NpWTI3pOs AWoZrRheXVlItNWH6xGfzca7ybdtlY+ro8FLznOKRH0PL61+6MGYGjq6MqDjR/nvrV9ODPpsVuj ad02r2du/LFknJgcVXsnn5K79hqxnFePG8CcS2SiXriIecB54RsPFr602Yn8K/USZFSuLj4dwyv KOf476MM8+mE6APnD4Mp9PSxR1AKrhe1UVXXVBGnDGHL/GKtgBwrmf5b+6Y3q072uyt4ubbbYeo 2Rb+Z+sZo7dbZPXB8146iyyA7swLUI= X-Received: by 2002:a05:600c:4fc1:b0:483:aa2:6bce with SMTP id 5b1f17b1804b1-483202253ecmr203519005e9.30.1770731543910; Tue, 10 Feb 2026 05:52:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/26] whpx: arm64: implement -cpu host Date: Tue, 10 Feb 2026 13:51:59 +0000 Message-ID: <20260210135206.229528-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731702201158500 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Logic to fetch MIDR_EL1 for cpu 0 adapted from: https://github.com/FEX-Emu/FEX/blob/e6de17e72ef03aa88ba14fa0ec13163061608c7= 4/Source/Windows/Common/CPUFeatures.cpp#L62 Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 17 +++--- target/arm/whpx/whpx-all.c | 104 +++++++++++++++++++++++++++++++++++++ target/arm/whpx_arm.h | 1 + 3 files changed, 116 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4dfc03973e..5d7c6b7fbb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -26,10 +26,13 @@ #include "qemu/units.h" #include "system/kvm.h" #include "system/hvf.h" +#include "system/whpx.h" +#include "system/hw_accel.h" #include "system/qtest.h" #include "system/tcg.h" #include "kvm_arm.h" #include "hvf_arm.h" +#include "whpx_arm.h" #include "qapi/visitor.h" #include "hw/core/qdev-properties.h" #include "internals.h" @@ -521,7 +524,7 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); isar2 =3D FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); =20 - if (kvm_enabled() || hvf_enabled()) { + if (hwaccel_enabled()) { /* * Exit early if PAuth is enabled and fall through to disable it. * The algorithm selection properties are not present. @@ -598,10 +601,10 @@ void aarch64_add_pauth_properties(Object *obj) =20 /* Default to PAUTH on, with the architected algorithm on TCG. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - if (kvm_enabled() || hvf_enabled()) { + if (hwaccel_enabled()) { /* * Mirror PAuth support from the probed sysregs back into the - * property for KVM or hvf. Is it just a bit backward? Yes it is! + * property for HW accel. Is it just a bit backward? Yes it is! * Note that prop_pauth is true whether the host CPU supports the * architected QARMA5 algorithm or the IMPDEF one. We don't * provide the separate pauth-impdef property for KVM or hvf, @@ -769,6 +772,8 @@ static void aarch64_host_initfn(Object *obj) } #elif defined(CONFIG_HVF) hvf_arm_set_cpu_features_from_host(cpu); +#elif defined(CONFIG_WHPX) + whpx_arm_set_cpu_features_from_host(cpu); #else g_assert_not_reached(); #endif @@ -779,8 +784,8 @@ static void aarch64_host_initfn(Object *obj) =20 static void aarch64_max_initfn(Object *obj) { - if (kvm_enabled() || hvf_enabled()) { - /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ + if (hwaccel_enabled()) { + /* When hardware acceleration enabled, '-cpu max' is identical to = '-cpu host' */ aarch64_host_initfn(obj); return; } @@ -799,7 +804,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX) { .name =3D "host", .initfn =3D aarch64_host_initfn }, #endif }; diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 6067918b27..c88c67a9e2 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -41,6 +41,17 @@ =20 #include #include +#include + +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint64_t midr; + uint32_t reset_sctlr; + const char *dtb_compatible; +} ARMHostCPUFeatures; + +static ARMHostCPUFeatures arm_host_cpu_features; =20 typedef struct WHPXRegMatch { WHV_REGISTER_NAME reg; @@ -668,6 +679,99 @@ static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARM= ISARegisters *isar) SET_IDREG(isar, ID_AA64MMFR0, id_aa64mmfr0); } =20 +static uint64_t whpx_read_midr(void) +{ + HKEY key; + uint64_t midr_el1; + DWORD size =3D sizeof(midr_el1); + const char *path =3D "Hardware\\Description\\System\\CentralProcessor\= \0\\"; + assert(!RegOpenKeyExA(HKEY_LOCAL_MACHINE, path, 0, KEY_READ, &key)); + assert(!RegGetValueA(key, NULL, "CP 4000", RRF_RT_REG_QWORD, NULL, &mi= dr_el1, &size)); + RegCloseKey(key); + return midr_el1; +} + +static bool whpx_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + const struct isar_regs { + WHV_REGISTER_NAME reg; + uint64_t *val; + } regs[] =3D { + { WHvArm64RegisterIdAa64Pfr0El1, &ahcf->isar.idregs[ID_AA64PFR0_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Pfr1El1, &ahcf->isar.idregs[ID_AA64PFR1_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Dfr0El1, &ahcf->isar.idregs[ID_AA64DFR0_EL= 1_IDX] }, + { WHvArm64RegisterIdAa64Dfr1El1 , &ahcf->isar.idregs[ID_AA64DFR1_E= L1_IDX] }, + { WHvArm64RegisterIdAa64Isar0El1, &ahcf->isar.idregs[ID_AA64ISAR0_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar1El1, &ahcf->isar.idregs[ID_AA64ISAR1_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Isar2El1, &ahcf->isar.idregs[ID_AA64ISAR2_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr0El1, &ahcf->isar.idregs[ID_AA64MMFR0_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr1El1, &ahcf->isar.idregs[ID_AA64MMFR1_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr2El1, &ahcf->isar.idregs[ID_AA64MMFR2_= EL1_IDX] }, + { WHvArm64RegisterIdAa64Mmfr3El1, &ahcf->isar.idregs[ID_AA64MMFR2_= EL1_IDX] } + }; + + int i; + WHV_REGISTER_VALUE val; + + ahcf->dtb_compatible =3D "arm,armv8"; + ahcf->features =3D (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_NEON) | + (1ULL << ARM_FEATURE_AARCH64) | + (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER); + + for (i =3D 0; i < ARRAY_SIZE(regs); i++) { + clean_whv_register_value(&val); + whpx_get_global_reg(regs[i].reg, &val); + *regs[i].val =3D val.Reg64; + } + + /* + * MIDR_EL1 is not a global register on WHPX + * As such, read the CPU0 from the registry to get a consistent value. + * Otherwise, on heterogenous systems, you'll get variance between CPU= s. + */ + ahcf->midr =3D whpx_read_midr(); + + clamp_id_aa64mmfr0_parange_to_ipa_size(&ahcf->isar); + + /* + * Disable SVE, which is not supported by QEMU whpx yet. + * Work needed for SVE support: + * - SVE state save/restore + * - any potentially needed VL management + * Also disable SME at the same time. (not currently supported by Hype= r-V) + */ + SET_IDREG(&ahcf->isar, ID_AA64PFR0, + GET_IDREG(&ahcf->isar, ID_AA64PFR0) & ~R_ID_AA64PFR0_SVE_MAS= K); + + SET_IDREG(&ahcf->isar, ID_AA64PFR1, + GET_IDREG(&ahcf->isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MAS= K); + + return true; +} + +void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + if (!arm_host_cpu_features.dtb_compatible) { + if (!whpx_enabled() || + !whpx_arm_get_host_cpu_features(&arm_host_cpu_features)) { + /* + * We can't report this error yet, so flag that we need to + * in arm_cpu_realizefn(). + */ + cpu->host_cpu_probe_failed =3D true; + return; + } + } + + cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; + cpu->env.features =3D arm_host_cpu_features.features; + cpu->midr =3D arm_host_cpu_features.midr; + cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; +} + int whpx_init_vcpu(CPUState *cpu) { HRESULT hr; diff --git a/target/arm/whpx_arm.h b/target/arm/whpx_arm.h index de7406b66f..df65fd753c 100644 --- a/target/arm/whpx_arm.h +++ b/target/arm/whpx_arm.h @@ -12,5 +12,6 @@ #include "target/arm/cpu-qom.h" =20 uint32_t whpx_arm_get_ipa_bit_size(void); +void whpx_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 #endif --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731612; cv=none; d=zohomail.com; s=zohoarc; b=NnQyBMho2QmFnSLrYZd6d4wn4P/Tp6XO4jQH529szoOLQhXUXOFbYFLmeebKXeefcx2ppF+MkQ9Shq8eqRGnvetgMQRIRvdCoXgZnLGZS+tfJ8NzlUpuoC/z8CuuVr3GC4rcCEyDej7ZN0Du+mUiMCIkdm52EqFfqGT7KJ9TU5A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731612; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=7wzAaDjiOhrmRRcJpDVFtm7pFxU4gAMetH8yOhIS7bo=; b=YPCX9tsCPM/3A4IfLJrHNe70KIdLjiPMx/WifmsPZ1lvH76tkhD1ssjUUxAIOuyKeptRYXI/Tba5AQRa08mgxdxxXReDM7qndqu6CxaUSpRMuMcHnDFxQTOwi7LYezZ+7RxGCSAaCbh2/RmmFdQbkVnuj0MJ6Nf8XtePMlVLI5o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731612382205.18012688237957; Tue, 10 Feb 2026 05:53:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAJ-0002Cx-1H; Tue, 10 Feb 2026 08:52:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAG-0002B1-JR for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:28 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAF-0006Mq-39 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:28 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-480142406b3so43928435e9.1 for ; Tue, 10 Feb 2026 05:52:26 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731546; x=1771336346; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7wzAaDjiOhrmRRcJpDVFtm7pFxU4gAMetH8yOhIS7bo=; b=k1Es7PRZubPlIBsfZ9Pkw7uSvS8Gn/JfWZClXPCGI3tQqjK3WRjYMKf22vjfSovGqG inO8H2JstdiN97c7Vb5D2ih28zvaDA7tqMOdA6bzevxmg2IKPhlG7Q+Mpm6H8gvmdrFu QGjdzA2BLOLz7rU+Q7UXDNu8YTg7k4ne/b5nfZmpd/ECs9AcGbSPxkdp+iV6g8O1M8ja thnHlrRdEtTYcQ+rAUmu33WOwgcuHOuSil0EzgVCxjkudJWpT0W1XonEUNXBeGZWIkQb 41nmWyWEm5FEpTZUtHW9TPulitLeXZsWnAmyzAh6WD1u1oF+u1crZ+8tcOsaGHXXt6Aj MjoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731546; x=1771336346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=7wzAaDjiOhrmRRcJpDVFtm7pFxU4gAMetH8yOhIS7bo=; b=wBaJmc/TmNB/3sp/pBy+7AMynwYWW+N8z8BiVh880iVUbGSrdpblw8Hy/Z1gEZ2GM8 uxPzN2FMefukkgpJap/OzMfIYkODRw/BwiGtbSvthwg/vT/IxjfR6P6VO77Ym6zRMOci PM8dXdVlMkrPPkB5SjHD60I2oWlhLzhJX5LmqQyC8Cg1A+tUvshuD6qGHfvA71vEyopG WT+Vjo9bc8Ui/F5gbgca/u0OfOyLvbN2g9/lFrD51sYZcV3IqjqXOZPPXadZ4yNYlwAr E4a0FOvCliYaeF6f1btjJSaqxoc72xQbMvT0MaWYdbE7zrp8pLgKUIkG3sSsXLxYRW6u dNNA== X-Gm-Message-State: AOJu0YyWc3+YDkhfaYhWpyDe9KTKvzCN0m/vPsNkabRl8Z1bB1o/2pDv rxQ3cEE9fXFkxkfkHL4zvR4M6TNNW7NbTOJZiSHfcMvAy5JroE53lEvw5NXMomPdx1PfYmVorcY yHyGJ X-Gm-Gg: AZuq6aLfus8bxThWjTMWaEdyn4m+uCQ+a7uliom6h4z5HtC7FhVgKOOWVDln11Cxl3O tVbZOlCKqGnDAPulZbMZgS51ZS3+uRxq33q0MgqIyGcfD8xPFagX19tUJAJyR9ap6sCrBb0DQj/ t/cQc4Whg8TgfEcxkFA2aTdkXGSB2u7zIyYyAtZ7UCVJcVDQrsvc7rtsXP9hIWB9M49DfNXzD9J VuPLTyBJhunH8vQ3+vjLqCl0lcDgjyZALLe+TAI1tWHPKJrGtiLtV405ewLq8qmIqiOYTTWc0PR jYHgwUZMpOTB8nucKy0wfQITHl4/rehtpvb8UPm4uFxHDcUONcNKvxbxQ8tFfOmgYIBXAAZxqpe o+xFcKodPubPrTdicRzZrQR707P988ONt3Dvb4u5p0bdMouldK+sL6DXaoj6Px6Tgvrr45kaW73 zoQWhuHwosdYa1ODaJpfVtYHKYjfLDb8xT64f4fRFkaRDVOvkDsdDFOKgI+UgXbYZUfzlx8cUi2 +ci25zzq9QnqHZctbbxzqZUM0t/qZs= X-Received: by 2002:a05:600c:450f:b0:477:7af8:c88b with SMTP id 5b1f17b1804b1-483507e16a6mr31159365e9.11.1770731545579; Tue, 10 Feb 2026 05:52:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/26] target/arm: whpx: instantiate GIC early Date: Tue, 10 Feb 2026 13:52:00 +0000 Message-ID: <20260210135206.229528-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731613520158500 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni While figuring out a better spot for it, put it in whpx_accel_init. Needs to be done before WHvSetupPartition. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- target/arm/whpx/whpx-all.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index c88c67a9e2..44ef42307b 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -939,6 +939,38 @@ int whpx_accel_init(AccelState *as, MachineState *ms) =20 memset(&prop, 0, sizeof(prop)); =20 + /* + * The only currently supported configuration for the interrupt + * controller is kernel-irqchip=3Don,gic-version=3D3, with the `virt` + * machine. + * + * Initialising the vGIC here because it needs to be done prior to + * WHvSetupPartition. + */ + + WHV_ARM64_IC_PARAMETERS ic_params =3D { + .EmulationMode =3D WHvArm64IcEmulationModeGicV3, + .GicV3Parameters =3D { + .GicdBaseAddress =3D 0x08000000, + .GitsTranslaterBaseAddress =3D 0x08080000, + .GicLpiIntIdBits =3D 0, + .GicPpiPerformanceMonitorsInterrupt =3D VIRTUAL_PMU_IRQ, + .GicPpiOverflowInterruptFromCntv =3D ARCH_TIMER_VIRT_IRQ + } + }; + prop.Arm64IcParameters =3D ic_params; + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeArm64IcParameters, + &prop, + sizeof(prop)); + if (FAILED(hr)) { + error_report("WHPX: Failed to enable GICv3 interrupt controller, h= r=3D%08lx", hr); + ret =3D -EINVAL; + goto error; + } + hr =3D whp_dispatch.WHvSetupPartition(whpx->partition); if (FAILED(hr)) { error_report("WHPX: Failed to setup partition, hr=3D%08lx", hr); --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731591; cv=none; d=zohomail.com; s=zohoarc; b=EgbN2L3aLq3Iov6J/73Dy/t2hmhOMv1Ho/xgRfWJm2FJpPTDZxzmY1tA2aZHbASxE5u6FPntiVC7NVAhT7uLm9ex/azHQaWMEqqMoIDWHPwFw51/+jEUQgqgxXRmPp5ZEXsT1ijSU/aBc9JtXniutrngoe9xg4wnKjt7jw0pgoo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731591; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=kq2OeTrUcPIegeZ5VRCi1cFtIhc0er3FyZyNyjg0Krw=; b=kFhLRj3INux2lqtJ+spYFENu61ttnsdSJxsiXOpSPFil0JHH9uYoS8mKwZ+oVbt0HiY4lduFvf3kAd/srin/+A3nOLKkTuhXEQthCHOvJe8DjfuTkuCTD0HxJisQUKYfKkEVOLtZKZBuZmlq0YcYdK5ooxpPGFEMReFefkCld3g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731591338204.62747209526526; Tue, 10 Feb 2026 05:53:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAL-0002EX-Aj; Tue, 10 Feb 2026 08:52:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAH-0002Br-MW for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:29 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAG-0006N9-30 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:29 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-436309f1ad7so2702877f8f.3 for ; Tue, 10 Feb 2026 05:52:27 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731546; x=1771336346; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kq2OeTrUcPIegeZ5VRCi1cFtIhc0er3FyZyNyjg0Krw=; b=R8nTJPOP8JkEEcuIQjye4i1DcboGnfcHbcwRL3V+gNloasHAj5ur6OVfB7Mkw0kMWt xp2ZKvv07ZDEVseDHTFDE7pW/FdzJ5eqr4wN788k4M1gCu8iwoxu+V3WeUXqw/pfqzam H7Frw/llDpM0uEJ/JzobqQ/PUBb7I26LpLYnsiaByqMN1/4f8fo186SKSHBX28MVKRLc uk3kQrX3jb6Q778MR3bt0o67W66bG8JHpmVHYqxWvvUATGIQHS7T+i38JhZuO5iq2Ig/ FE0Cq4U3m14saLakzsD6/qjrzPp658mr8LG0Zfz/GpX95OzSDtFNx9+4WzMCUuIkUjiw jnvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731546; x=1771336346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kq2OeTrUcPIegeZ5VRCi1cFtIhc0er3FyZyNyjg0Krw=; b=YovnQ2tcSJoPR1dweijtd3trG1HA2y4k2XF4Pqb69pV33VtEnem18X9+2Rgb+DretC rP9tCfnS7I+aJCnL1H5TAg3va08Znn30dH3/UjckI1k8FThIq4W9Sh5/BnfXtsWuHNub gOQ/ZaFEmASLjasP3LlkjDcOFd9tzQRU+lrpFI9D6Q9So829RsBuc3tmhy4tua2GARoJ fjlUL/4VlM+QDQV1JMtBvs9j91ZKoA4GqkLg+HIYMTHB3cuZ4CXVTILQ90FImlYM9a5d tA51fPlqVJO9RXSSm9QEB0dXGmaLC7uLkdvcjBFa4In3NCx/hF2lo2Ak3y9iqy4X9ePN rYzw== X-Gm-Message-State: AOJu0YyhDFxY1UFi9D5a91jMtTxOUU2VLWrbu+vkiXMtuPqkisfm9feq QwABIBxFonhU1sVBg09/7s2hlTMtFj9cMKSIXAZAvHeCoruSLDhLFtTwhRg8CIFO0LPYcy8IjgY /i+KL X-Gm-Gg: AZuq6aJ6H8HOAns38dxQn3KfY2PR4RJVAR16W6inI/4RFVc2whsvt/imijLIHWGgWLw I3hAc5YW/7AnBEcvMAOq3TuhcTkAQlzw4UINWoS8w3w5R20CCpnYYslgFZCWP/p/2M+yXxLGpUV Z3hYdGPCF2cMCBykU72UxiW0QrYIbad0ToHU/KHVIQgJQqsiBkJ2YsadXK0DMokEMBIdatQi1CZ J+Ze136Rtry0OmYfGKy3xj6up0h0f0XBsTlQr7NxFU0uCDZX6ET43kqpSrqaHwRvpM0mM+Udc8G DsS6z9ZO4P33W/HkvwFPei3Br8yj7WPo3FSQRNc+KD+Vd78+lmZsG8TCvrGh+ecxQ7KqPoJHWOO ZN9hRB9c93UiwulompYIVUDurdkdW3dhMNmSjxZZRlx5mMVhv9Ik7l4ayFGOh3aFDYtj+zmouVC 10QVhzuxNXqsoIPrqHXNvOUkfKaNC2yjI4wx17zz/qbrq8afzHUdAiKnpitste2OQaiVCkP5QCH lHQTrxrgtrMg0s8vFsuYfgXh3frXdaAS2NhpmKBLg== X-Received: by 2002:a05:600c:34c5:b0:480:1c69:9d36 with SMTP id 5b1f17b1804b1-48320212e11mr263320435e9.17.1770731546402; Tue, 10 Feb 2026 05:52:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/26] whpx: enable arm64 builds Date: Tue, 10 Feb 2026 13:52:01 +0000 Message-ID: <20260210135206.229528-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731593415158501 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- meson.build | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/meson.build b/meson.build index 2d114e9018..e8fd77aac0 100644 --- a/meson.build +++ b/meson.build @@ -301,7 +301,8 @@ accelerator_targets +=3D { 'CONFIG_XEN': xen_targets } =20 if cpu =3D=3D 'aarch64' accelerator_targets +=3D { - 'CONFIG_HVF': ['aarch64-softmmu'] + 'CONFIG_HVF': ['aarch64-softmmu'], + 'CONFIG_WHPX': ['aarch64-softmmu'] } elif cpu =3D=3D 'x86_64' accelerator_targets +=3D { @@ -858,13 +859,18 @@ if get_option('mshv').allowed() and host_os =3D=3D 'l= inux' endif =20 if get_option('whpx').allowed() and host_os =3D=3D 'windows' - if get_option('whpx').enabled() and host_machine.cpu() !=3D 'x86_64' - error('WHPX requires 64-bit host') - elif cc.has_header('winhvplatform.h', required: get_option('whpx')) and \ - cc.has_header('winhvemulation.h', required: get_option('whpx')) - accelerators +=3D 'CONFIG_WHPX' + if cpu =3D=3D 'i386' + if get_option('whpx').enabled() + error('WHPX requires 64-bit host') + endif + # Leave CONFIG_WHPX disabled + else + if cc.has_header('winhvplatform.h', required: get_option('whpx')) and \ + cc.has_header('winhvemulation.h', required: get_option('whpx')) + accelerators +=3D 'CONFIG_WHPX' + endif endif -endif + endif =20 hvf =3D not_found if get_option('hvf').allowed() --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731703; cv=none; d=zohomail.com; s=zohoarc; b=CTjjiYh32RUcLTYdRzXJI12p5SBXk0lFCBN5BWB+uWyUUkTqcWlHqv3s3lvvWeQBmqW+zeVDVVBqY3WixMn9T39AJe9F5bbo1t+JxyFkxxS3D72b1QRVkjYlMiXvs4Yz5uoemQENWic+Hz2Lh9A8i/ovC4HSTWCunjEwvrTGfLg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731703; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=dCm7KHoJAqs8SA7JjFZDtnB2gN/PwqLJzcqLgMLX7XU=; b=d3O3pweaLg0b0L75fW5COACmUO2cOFn1g1J91Pppmgnc7FhnB+PEChSuDJB1VqeH9rRoCcnmYkv26l5VCsRCgNuLRtwuR1wp6UMSPVc6Cfofq/l1oKfILJqf2gLGneJzlWEXTEhVZYdSJvd4mQSH27YV8mU/HruRNIPYc9dgeT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731703679836.128878711768; Tue, 10 Feb 2026 05:55:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAM-0002Ep-1a; Tue, 10 Feb 2026 08:52:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAI-0002C6-Ap for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:30 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAG-0006NF-Rq for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:30 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4801eb2c0a5so53544655e9.3 for ; Tue, 10 Feb 2026 05:52:28 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731547; x=1771336347; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dCm7KHoJAqs8SA7JjFZDtnB2gN/PwqLJzcqLgMLX7XU=; b=uGa0vdTRmy9GClKQcSKqyMcOY/YWykTt3m+H0P65iALt/7A/FfAhS+gTrNC2eemWdL Pfpb4H1pnekdV7zYfm7ZozOyZHP9D5SXEjLRD/DtjnbbCU3bBD9niS3+fVz9yqtsLZxN gQdagfwVA3KHgWG5/a8shKzFGgnWaB3RzMT5SssEOQSqv+++CB/bQFY/FgTJlJt8w88K NoDcbE6V7lRGEPKoCVxxnkBggOEFYeyD9z7I4vr+pUkneSqmZRcpAhQysza2LDwZPV7k QHv8aRhlxwyMrJHhICSTF3cywnjp0Pl8X4b59Vz7wC3RG0Nui8T/OJBTQO06vAiwAQd6 b78w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731547; x=1771336347; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dCm7KHoJAqs8SA7JjFZDtnB2gN/PwqLJzcqLgMLX7XU=; b=Mv6QlMgECyPUywF2xLsXpNK89Q+qdmMSYkjd3zJsb5xYQvu9xE1PWm4G3QluAQCqIy 7VObPOoGzFgDgti62JyjTr/R860gVrGm9hfOFvLoofOemRPi3lpoJmA3Rz/yyEBvbUHr nqW236blIA7b4lVxHzhh9SUJCZa0c5B5jdHykEuF/OcL1wezYD+hAnMzI2bdBUkmPBx6 BXmT4RtRWmmJ4CMB+QawLBiLqdl4rCpAbQlbd7LO31zMdqAy7vzD4783/jKVJ7+X3mNZ FaNKXd5RpngMLFydsltyn1WmI80fJ6ZyAOJsFZJRqKc31RQd5phJX1DG5IE+aD3kn2zw 5CwQ== X-Gm-Message-State: AOJu0Yx9sqcDn6d1zjOcTMjSCijiyt4nR71VYqr7Slz2i+ljxSB6ObHP YTT73UigYIb/3Vy1vw4haIZjDTnbUerjSVA01121S45HPwOLfh9yH54hkcce0bmuaxH11dYeQ6y JRW7i X-Gm-Gg: AZuq6aKAVgRVVXLfX3BUmjQDCprtC1xOmEkJ9k4N9EX4FoBHLd3e/JQqDRPQ/6nJb/H v+qzlKIcw96P0lv4OlRZwqyOjvaA006W+Bm/42kZUp6e0O7qazWYPdMloF2iAoBfkGb9s3Xhod+ dQr+IK/6fT2IFeFlw6hPR6MnBiaZvUtwI1DiCEHFZDazIqp/16t437hcXaDGIcY/R9L+KwCmdCi ZEiS0HOEz0QZ7zM15Ov/isCws2W3OxQYljiodb+8epZQtT9KUwsLPV/MBDZv7VFSRqiPxh+MwEC Zcq8CvPZ9+Gchm8/ppqVaAYz3RMg1eOgcxMxogzgwUHj8hQsdD4r7WaoqncnlyWSy3X/MLKFqGQ rppqDV6Tss/VZvw48Bs+4sv2PpD1KXqRmn4Qe8bUAl7hrkuTxWEBrDl32wsPYCOiJMizhiSswoR AQQmdVnDf0YITC9jxOINjsx6b07ypzElHYnFfE5342rlGfJb9rKdxXo0mIH1WDvCIwOqZsjkzQx hF6c2KG2+Z3GTi/2t/Y+5H6rk3oBP+f9MJE9msCLA== X-Received: by 2002:a05:600c:4e8b:b0:477:7bca:8b2b with SMTP id 5b1f17b1804b1-483507f2bb3mr31237915e9.15.1770731547236; Tue, 10 Feb 2026 05:52:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/26] whpx: arm64: add partition-wide reset on the reboot path Date: Tue, 10 Feb 2026 13:52:02 +0000 Message-ID: <20260210135206.229528-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731704055158500 Content-Type: text/plain; charset="utf-8" From: Mohamed Mediouni This resets non-architectural state to allow for reboots to succeed. Signed-off-by: Mohamed Mediouni Reviewed-by: Pierrick Bouvier Reviewed-by: Akihiko Odaki Signed-off-by: Peter Maydell --- include/system/whpx-internal.h | 2 ++ target/arm/whpx/whpx-all.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/system/whpx-internal.h b/include/system/whpx-internal.h index 8ded54a39b..ad6ade223e 100644 --- a/include/system/whpx-internal.h +++ b/include/system/whpx-internal.h @@ -86,6 +86,8 @@ void whpx_apic_get(APICCommonState *s); X(HRESULT, WHvSetVirtualProcessorInterruptControllerState2, \ (WHV_PARTITION_HANDLE Partition, UINT32 VpIndex, PVOID State, \ UINT32 StateSize)) \ + X(HRESULT, WHvResetPartition, \ + (WHV_PARTITION_HANDLE Partition)) \ =20 #define LIST_WINHVEMULATION_FUNCTIONS(X) \ X(HRESULT, WHvEmulatorCreateEmulator, (const WHV_EMULATOR_CALLBACKS* Cal= lbacks, WHV_EMULATOR_HANDLE* Emulator)) \ diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 44ef42307b..36c5e30a03 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -497,6 +497,8 @@ int whpx_vcpu_run(CPUState *cpu) if (arm_cpu->power_state !=3D PSCI_OFF) { whpx_psci_cpu_off(arm_cpu); } + /* Partition-wide reset, to reset state for reboots to succeed= . */ + whp_dispatch.WHvResetPartition(whpx->partition); bql_unlock(); break; case WHvRunVpExitReasonNone: --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731703; cv=none; d=zohomail.com; s=zohoarc; b=E8xx2RCJOX4GTAfWiHXwn0FWgoJsHt5dncDPbbshlTjRigtUS1AZQvNmdvAFyqG1WABUW7g3b7TiZUJu+EKzelcwW+kPhbXSn8lcOmG6PhUorYJ7IEohaGreMqA2rAnA5vlIO60IJdLJpoRiF0P5e4FicBGXBRO5kzAMSoQmNsQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731703; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=pdpSaZtGa5N0YXyoXR6kPL2wef5TSrP+IEpCI4EPzj4=; b=g0dZjkRAlt0bBAhluZNOfLmDciRfDShshq7g4GDEY6DRsTS8NiwAhJjO4i2xyy8FAV9CSEZwESIaiwMxOsxzO2+02SUDAWVLyH/u0uuKBfySSFRQICIkdsuzkBDoW8KsLUVO4INSAlWonhJ1oaVkSf/Q/B6zM1EwRNxshD9KZww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731703418943.1848464223145; Tue, 10 Feb 2026 05:55:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAM-0002F3-BD; Tue, 10 Feb 2026 08:52:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAK-0002Db-1i for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:32 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAI-0006Nn-Gc for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:31 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4801bc32725so31615255e9.0 for ; Tue, 10 Feb 2026 05:52:30 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731549; x=1771336349; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pdpSaZtGa5N0YXyoXR6kPL2wef5TSrP+IEpCI4EPzj4=; b=OTiRqXSopAa2tOY8vqzoP/YPDuPUnU1xUd8ggK6a1Gqh3gOxCmMuPclH35DK3Mg2IA I1xAbe+o3IKE7NUtAXh5IyIX6z85qWLMKiTNmdG43YIxy2Z9VRrB4GsSKphTYqY+h6Pz l1b1tRSu0hiEwTfFEyoxyV3b5J8p8IhZLlzkxQXuzeQjwd+Tj7Iusmf4gnyFHftJAQs0 EL6KpbPmQD9cx2znLNtrTIxRiAHojx8XomQkpGs2bnmD1n1Br5qAHifhO88F+m8Q6s5/ V+uf0sVCQT/1ZCD767pdONVtV49iRestWadI3P1y1iDap46AnqhhWxr+WXPvpfYzGWvx REwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731549; x=1771336349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=pdpSaZtGa5N0YXyoXR6kPL2wef5TSrP+IEpCI4EPzj4=; b=mnBCCLUQ7JYPaM0lmhqIgN8BBJLyUQWyUOrD2J5kdUL2MXiOuDMGzZb0rsNu344N2g ff6ruTjm90jNnsJRdhe8iLgmRwhGPc0Ux3e18EDmkbokSP8Kik5yh7UKruyXFWdbMXLd ZbMs4wk3dxIMnVXYRBM/J6+bCzIGWpCeAX6lkIvmy2PDULRDDBRdy1ASYSXpllbLCvT8 sqqc9DJuv3ei+I4edO65GluaK5sW6EG9u12M7Hu9Ar8YITB2llsn0ABISNXMp88HmuDf DLPE1E/EcWi+4/9M6VFI3JLKrg/7WzQ29vSBOvHvlwqS6k5dupcVd9jVB/Fm6zyytgkQ Yt3w== X-Gm-Message-State: AOJu0YxDvkColJITeuQUeNVW+y89VGcdcEv91GHPMjXctsvUNtfNhMzy 7HROfycbph8ijCBf3W8BeLu16stSm0+gsc5jexnr5bxza7SszaahwjdbTXoMkO1PJDopwSScX31 mpS2Q X-Gm-Gg: AZuq6aJmoJwY8n1smjbemxrEOnMNRv8LXrFtH57YZVkPsZhDVPBkeLPJ6rdmtw8/UG+ pgyeWFAXT7+xZRfGlngm2yiNDtGYRjfIo6kOv/D7vfv47ixWWFtv7OfpcVyvCkZp/oD9KQ/CSAw eeOqUTGu+Eais2bsTEiiLFB8bms6djvNSon5MVx5ou7+Gmu8FaymYNrwhF3cLRGwL72cJ+scOKm V+VqHX/9d/ZOapdrM/JIkYfRNDbdIhxJLG9n+GQrrmBa3oppwz2TayCJujK1ugMwpaQkNA5pQGQ uoQz8YCFqmI5lUGO27AcnbII3L++7k4c4IVhmFWzB/ZC7AkHBHayOr2LOQKC2vINQSqu/7IqUQN neYGqC+ldzWDlQu6NMJSUZ83UMFMoGevPtYmti6JuQ0zB2RUShtiL4XUeuzORspz63o+JCqOO+u L+DOMb7Rtom0yxqHsVxRGhtiuZ2d5wjm7VIR64BtAzUw6DUtC2KNxE/AsHUKpBYOS/AFK6vZ/CG jzM6crU72UeSWnFLDARyFgMFiwZu8A= X-Received: by 2002:a05:600c:628d:b0:480:1c85:88bf with SMTP id 5b1f17b1804b1-4832021ca66mr227640225e9.27.1770731548717; Tue, 10 Feb 2026 05:52:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/26] hw/arm/virt: Rename arm_virt_compat into arm_virt_compat_defaults Date: Tue, 10 Feb 2026 13:52:03 +0000 Message-ID: <20260210135206.229528-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731705718154100 Content-Type: text/plain; charset="utf-8" From: Eric Auger Renaming arm_virt_compat into arm_virt_compat_defaults makes more obvious that those compats apply to all machine types by default, if not overriden for specific ones. This also matches the terminology used for pc-q35. Suggested-by: Igor Mammedov Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott Reviewed-by: Cornelia Huck Signed-off-by: Peter Maydell --- hw/arm/virt.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5c31695d37..02db6d8579 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -96,20 +96,21 @@ #include "hw/cxl/cxl_host.h" #include "qemu/guest-random.h" =20 -static GlobalProperty arm_virt_compat[] =3D { +static GlobalProperty arm_virt_compat_defaults[] =3D { { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" }, }; -static const size_t arm_virt_compat_len =3D G_N_ELEMENTS(arm_virt_compat); +static const size_t arm_virt_compat_defaults_len =3D + G_N_ELEMENTS(arm_virt_compat_defaults); =20 /* * This cannot be called from the virt_machine_class_init() because * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new() * only is called on virt non abstract class init. */ -static void arm_virt_compat_set(MachineClass *mc) +static void arm_virt_compat_default_set(MachineClass *mc) { - compat_props_add(mc->compat_props, arm_virt_compat, - arm_virt_compat_len); + compat_props_add(mc->compat_props, arm_virt_compat_defaults, + arm_virt_compat_defaults_len); } =20 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \ @@ -118,7 +119,7 @@ static void arm_virt_compat_set(MachineClass *mc) const void *data) \ { \ MachineClass *mc =3D MACHINE_CLASS(oc); \ - arm_virt_compat_set(mc); \ + arm_virt_compat_default_set(mc); \ MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \ mc->desc =3D "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Ma= chine"; \ MACHINE_VER_DEPRECATION(__VA_ARGS__); \ --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731687; cv=none; d=zohomail.com; s=zohoarc; b=NMz603ckb3hQYPbtaDxBaDBF3kehn5Z8Pbd4O9yWK8EFZgbKDCh99vpT3/O66xu7yMkw8wC88yVkRTTodaadR9xw70Tny86TegR1vDoeuf6C3jTZqKfAEzGEOj8WPegNOwmaSPgPHyqO2yfxmM5iephCEQfoydW7660x42SNReo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731687; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xY0d3NFt0HZPqHzHbAfTDIQcZriTqekzYmOm7UjWuJQ=; b=QrSrU26K2YOAt+cMurjbPEO6Ik77N6cF/MTBqpGJLC9/N/vLrXzdkNHWITlbWgRgX1t9mCqzsFolusGA5OvsRtcO/ViGdDFPjIPSnCubYlfMySTiT2j4LbMLUs5AXgxCrGb3Q+We6+CUxVtbYOqxlw/EDN/mANNn5pjM2Pgj1u8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731687357833.1976475719046; Tue, 10 Feb 2026 05:54:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAQ-0002H6-1B; Tue, 10 Feb 2026 08:52:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAK-0002Di-HS for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:32 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAI-0006O5-Tu for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:32 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4832701b9b7so22622265e9.2 for ; Tue, 10 Feb 2026 05:52:30 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731549; x=1771336349; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xY0d3NFt0HZPqHzHbAfTDIQcZriTqekzYmOm7UjWuJQ=; b=BGjGDjeOFP38E2tl/U/0Dt/li5VkbFvgnEOcRyiB6tyCRGQQpIwR0v1EOj9HzMmHwZ VWLLwpnQiMX6oVNhIP4W/SkcLCu0gpadGt8Tb+7eWuDy18yp0d3R7SOL9dvWpIJBZnGH t/VwVZ2xIj1Lk6McZsFeRM88im44ebDKr4L6K2ceVtwc4YhpZAzI2QG/WsN20R4uzeuD Ruto6qwug8wvkOLkvPnxnxRCswUXWqdEk50WTsINF8LPpKFunpeTNfd9++JatqUR1Xwf DBHf+37XLUdfKrSpTwgKGTyWTkzzqKESsHTMlUrhSHCqY5vNYamPfI+c7BuZaKTdf6Nz OroQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731549; x=1771336349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=xY0d3NFt0HZPqHzHbAfTDIQcZriTqekzYmOm7UjWuJQ=; b=pLcZ3Xloq/33N9zL7qkMz6EEBiCWWnMrjKyg3p3ZJsQv5r300cg4joygGCZT0Lhie1 xc1rxxoujuRAo8eIrRIEgxSOrzo+dXsTXnvcGIpnhv2L1Fy9/DlUXp8t0v1fADslnJh4 OHmog5nH8dP9ycpySdy+J/89SF/n5+cR5l8ve832n0syPJaTLoAeA0MffjdA4rn9g45b Rwe0B4G+YU4uhwyuiIj2ngsl5a4iKWXgflbCZgmB0qX2XvgnCMjrzdpjKS0kdGqUiej2 Txt6BL0MINXCgIHstv3xWFI0Pb+aVkLOa7Ig/eVqCGOHtFnahHBPxCwmhhOc2ozcdihS 8cEw== X-Gm-Message-State: AOJu0YyjFhyFWqwf/0xMeBdUvRr7UeYg77s5aCuWZE9rfbvLFlpofma1 MNoEdUB8+g24zKfW+8uR1SfEs8o6CdERphya43a8ZBZMYHAp2N4UVlRSPNNTrG/uH9tjx5aoPy9 rAVtw X-Gm-Gg: AZuq6aJT4KfhTtUtypigMfqcnqTQQqt1vTiWlFgm9kwektZZr+s2KGFyOEYLKTHwlpP JZPUW4mb7fjAtNDrd4ZqTUiqc5bcBpeBolpDCWRwEQFBOjteagjBAK69R6MNpXo5xqYyYceOU2l QDyHVW4Gb5Coy/gHQs/mwe2GGtTCCwAFbdyDusOxc5Gi+qFUUxPvvZssTfgyjcKD+cTn4Y11W30 VvXY0p+M38W2hdYghWAc92UVHd937GTUnUCDWjUOmcXy2mrtM71w7BK6z3a9SXLIzxCXW2W6743 U+WqSvjq7ZcswoynfN/pnChp1t2PL0wVlyr6uyq07iXqIHOS0omFLqMjiaDfsSWUX0tN+hfgfBl A9CzwC1aBuH1N3PUx5Q239893PzPm79NmDXeGwEen6XnHxa1RXi3kWbEbrI4HVuVl26v150Earw 0E99d+gIkDGQQMyHoFtPEoXIvqrqqiGjinuB7w+GMwGl3uclVuctk7qg3Z3oOZ8XBaBh/g52SM9 QRnclVqH4jIX1SCN1zsG9QzNzLPWN8= X-Received: by 2002:a05:600c:4e0e:b0:47e:e71a:e13a with SMTP id 5b1f17b1804b1-48320221645mr196110365e9.32.1770731549435; Tue, 10 Feb 2026 05:52:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/26] target/arm: Remove entry for "any" from cpu32 arm_tcg_cpus[] list Date: Tue, 10 Feb 2026 13:52:04 +0000 Message-ID: <20260210135206.229528-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731689443154100 From: Philippe Mathieu-Daud=C3=A9 Since commit a0032cc5427 ("target/arm: Make 'any' CPU just an alias for 'max'") the 'any' CPU QOM type is never used, because we change "any" to "max" before creating the object. The array entry means we have an unnecessary type in the system, and the only user-visible effect is that "any" is listed in the "-cpu help" output for qemu-arm. (System emulation already doesn't include this array entry.) Since qemu-aarch64 already doesn't include "any" in its "-cpu help" output, we can reasonably drop it for qemu-arm also; remove the not-very-useful array entry. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Message-id: 20260202153618.78675-2-philmd@linaro.org [PMM: update commit message to note effect on help output.] Signed-off-by: Peter Maydell --- target/arm/tcg/cpu32.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 0b0bc96bac..2127d456ad 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -897,9 +897,6 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { #ifndef TARGET_AARCH64 { .name =3D "max", .initfn =3D arm_max_initfn }, #endif -#ifdef CONFIG_USER_ONLY - { .name =3D "any", .initfn =3D arm_max_initfn }, -#endif }; =20 static const TypeInfo idau_interface_type_info =3D { --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731610; cv=none; d=zohomail.com; s=zohoarc; b=XtSXn2jGB8GY5eO6UmHZI0wMBWBZkYCjmD1IYJuE+H2e7qqCNfgFJuUgc/dCZ/QTkKP9hOSDv+pnj0qs0HyWVInne0fXc6Z1kcUPtDc1bF76n3wsx8/K6WuPwGWor/4XiWeb5McKnEle8iByva0JXOUaQkAm3XOj7hQ1aW+YClY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731610; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=i8xU8YorGAD8nVtQ3t6PaTQzkBHPBasWYnnVTTO1ehA=; b=A8q3hVDFvS7hPoTlfSRHKtYhgLrhK+zsn1DOMbAX/Shj+PRfBkWsLnVsejHecdB/3b0sUXQg+tIQ+lJ7OMbPa42ty351FsMayapMznWr/tH+m83J6W8fMYiuZgkZT7u0THJeHULp5R1d9MYwQRyhHwViRlFfy5E1IMLYJXb5JgE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731610814913.1171114020864; Tue, 10 Feb 2026 05:53:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAN-0002FZ-SN; Tue, 10 Feb 2026 08:52:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAM-0002FA-Kw for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:34 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAK-0006OQ-2g for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:34 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-47edd6111b4so82577805e9.1 for ; Tue, 10 Feb 2026 05:52:31 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731551; x=1771336351; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=i8xU8YorGAD8nVtQ3t6PaTQzkBHPBasWYnnVTTO1ehA=; b=PgZeUo+prUeRTIfh5zDFUWBKhufDTT83FmEOEfrYnPZKq7HS4cC1shJdEXlLaQoIH4 O0RcQ+ecQWXy507TztEqA/NBQKqpCVqeFkdaLud1B9MdePG3/0hAIitPTuuWJca/ShIs A1WJZCYKsrCyUZ3uMZDMiaSHEoLuB+FRu2V/+sNCb0Y37NnfTkg8bMiHD8epfdctm8aI s93spxKpAWbxYtMpbcsAFcz5uriTvYeEDfg1E3ZG04OMq/s1mozcjiVJJ04OOyOd7FwW frv0R8HDn/+Nx7NK5ehVYTgOa5qCOEncMiahtGP3pbaf41gWYiWXGTPpKQM/d6XGVjde YaRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731551; x=1771336351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=i8xU8YorGAD8nVtQ3t6PaTQzkBHPBasWYnnVTTO1ehA=; b=L2UW/Ui6qXkh8E33b9Sj0JsufXSDjW3q/ybr+yWWKa2cAZFnPVRcE2NXfHOEPw1VxP yzB3Pk8dLeq3bg/Xy7QrYj+FzXzcYs8FhQ0mt+vQBS/bykQoI//x55TDCo4cx+pTFqME 33Pl8eeINWWxWdkvp+l/08OThy8dVMrxilsR9AAqv43F8c1yq6dcpDVRQX3ZlNW3/eKP kNCukQK9MqkcxjsnLXv79rC0msdhEhxejKQoJhnkJI1GiIZsQPMdMNqR1QaAKz+gEnZY plOLoTOt50hHV3LFW5NW680qJNgJxHupzZi5FihG+o3STTKMi4L96e2ACF5M8zT+ILJc S/7w== X-Gm-Message-State: AOJu0YyCiRrJ19833KUKefjl04KrwyT9fSXZWHpkXqp843KEWe+FkjX/ feNWnyVf7U4+3/6E0a9CjEP3ohBhrqHkObE3WM4bQsl0OPyzB2PiJ3E+vfvr93T7eGvaV26GqiS fPHfD X-Gm-Gg: AZuq6aJcWSZop1PHnza4IRviICpLs4O6NfTkFtCJErj50PKvXBZVS58E0PazAtxoMHn 7fzA1e5DopTmkbw6J02Gs2R2A9TaAy2iL3oyPXAbeta+B9+v/xBEhCxBJP4lqa8sukemCi7xkRz bsWlAUHYa2uRo7RmXMH/3sao2+dGu31SHR0YvHGglnNc2Uxw0meEdbbaZemckJXRQz/4nr7PWA0 Pog3ZdISNaH8jDFkf+JefFebAZ+crKPduwhFBGE0o4DgLhFdS8JGh8HZJn1tB04Mhjv9UtUa/qU xzRxXPSFbb/KruJ12t2feJ/z3Ap3f34n91dPnY6PxIoNKPRdfCTg8Wcu608JzajyP3l3Fg8nELF 7Sambw39QKADi8/eyxB7t0hM3vZWkYDijv6p1PgnBldWz7Xipy2FYX+XtH2PvCyk0PPdn8UocZO wTPlsYAr/hXYTkm9/CObkOXPphkzxT9Vec9QVJ+hr3PeCPTC3HmTWdZkzNsn7PPp7OQ6Qhbhm6J O7oFzEGVxXfBlQYHteAqsdnvYWo2ACKxIXiy88JYw== X-Received: by 2002:a05:600c:8b29:b0:471:1717:411 with SMTP id 5b1f17b1804b1-4835081ed4fmr35061035e9.24.1770731550298; Tue, 10 Feb 2026 05:52:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/26] target/arm: Implement WFE, SEV and SEVONPEND for Cortex-M Date: Tue, 10 Feb 2026 13:52:05 +0000 Message-ID: <20260210135206.229528-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731611601158500 Content-Type: text/plain; charset="utf-8" From: Ashish Anand Currently, QEMU implements the 'Wait For Event' (WFE) instruction as a simple yield. This causes high host CPU usage because guest RTOS idle loops effectively become busy-wait loops. To improve efficiency, this patch transitions WFE to use the architectural 'Halt' state (EXCP_HLT) for M-profile CPUs. This allows the host thread to sleep when the guest is idle. To support this transition, we implement the full architectural behavior required for WFE, specifically the 'Event Register', 'SEVONPEND' logic, and 'R_BPBR' exception handling requirements defined in the ARM Architecture Reference Manual. This patch enables resource-efficient idle emulation for Cortex-M. Signed-off-by: Ashish Anand Message-id: 20260209051931.122531-1-ashish.a6@samsung.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 79 +++++++++++++++++++++++++++++--------- target/arm/cpu.c | 6 +++ target/arm/cpu.h | 7 ++++ target/arm/machine.c | 19 +++++++++ target/arm/tcg/helper.h | 1 + target/arm/tcg/m_helper.c | 5 +++ target/arm/tcg/op_helper.c | 56 +++++++++++++++++++++++---- target/arm/tcg/t16.decode | 5 ++- target/arm/tcg/t32.decode | 5 ++- target/arm/tcg/translate.c | 29 ++++++++++++-- 10 files changed, 179 insertions(+), 33 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 28b34e9944..a7651f831e 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -221,6 +221,29 @@ static int exc_group_prio(NVICState *s, int rawprio, b= ool targets_secure) return rawprio; } =20 +/* + * Update the pending state of an exception vector. + * This is the central function for all updates to vec->pending. + * Handles SEVONPEND: if this is a 0->1 transition on an external interrupt + * and SEVONPEND is set in the appropriate SCR, sets the event register. + */ +static void nvic_update_pending_state(NVICState *s, VecInfo *vec, + int irq, uint8_t next_pending_val) +{ + uint8_t prev_pending_val =3D vec->pending; + vec->pending =3D next_pending_val; + + /* Check for 0->1 transition on interrupts (>=3D NVIC_FIRST_IRQ) only = */ + if (!prev_pending_val && next_pending_val && irq >=3D NVIC_FIRST_IRQ) { + int scr_bank =3D exc_targets_secure(s, irq) ? M_REG_S : M_REG_NS; + /* SEVONPEND: interrupt going to pending is a WFE wakeup event */ + if (s->cpu->env.v7m.scr[scr_bank] & R_V7M_SCR_SEVONPEND_MASK) { + s->cpu->env.event_register =3D true; + qemu_cpu_kick(CPU(s->cpu)); + } + } +} + /* Recompute vectpending and exception_prio for a CPU which implements * the Security extension */ @@ -516,7 +539,7 @@ static void armv7m_nvic_clear_pending(NVICState *s, int= irq, bool secure) } trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio); if (vec->pending) { - vec->pending =3D 0; + nvic_update_pending_state(s, vec, irq, 0); nvic_irq_update(s); } } @@ -656,7 +679,7 @@ static void do_armv7m_nvic_set_pending(void *opaque, in= t irq, bool secure, } =20 if (!vec->pending) { - vec->pending =3D 1; + nvic_update_pending_state(s, vec, irq, 1); nvic_irq_update(s); } } @@ -753,7 +776,7 @@ void armv7m_nvic_set_pending_lazyfp(NVICState *s, int i= rq, bool secure) s->cpu->env.v7m.hfsr |=3D R_V7M_HFSR_FORCED_MASK; } if (!vec->pending) { - vec->pending =3D 1; + nvic_update_pending_state(s, vec, irq, 1); /* * We do not call nvic_irq_update(), because we know our caller * is going to handle causing us to take the exception by @@ -790,7 +813,7 @@ void armv7m_nvic_acknowledge_irq(NVICState *s) trace_nvic_acknowledge_irq(pending, s->vectpending_prio); =20 vec->active =3D 1; - vec->pending =3D 0; + nvic_update_pending_state(s, vec, pending, 0); =20 write_v7m_exception(env, s->vectpending); =20 @@ -898,7 +921,7 @@ int armv7m_nvic_complete_irq(NVICState *s, int irq, boo= l secure) * happens for external IRQs */ assert(irq >=3D NVIC_FIRST_IRQ); - vec->pending =3D 1; + nvic_update_pending_state(s, vec, irq, 1); } =20 nvic_irq_update(s); @@ -1657,7 +1680,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, } /* We don't implement deep-sleep so these bits are RAZ/WI. * The other bits in the register are banked. - * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which + * QEMU's implementation ignores SLEEPONEXIT, which * is architecturally permitted. */ value &=3D ~(R_V7M_SCR_SLEEPDEEP_MASK | R_V7M_SCR_SLEEPDEEPS_MASK); @@ -1722,38 +1745,57 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, (value & (1 << 10)) !=3D 0; s->sec_vectors[ARMV7M_EXCP_SYSTICK].active =3D (value & (1 << 11)) !=3D 0; - s->sec_vectors[ARMV7M_EXCP_USAGE].pending =3D - (value & (1 << 12)) !=3D 0; - s->sec_vectors[ARMV7M_EXCP_MEM].pending =3D (value & (1 << 13)= ) !=3D 0; - s->sec_vectors[ARMV7M_EXCP_SVC].pending =3D (value & (1 << 15)= ) !=3D 0; + nvic_update_pending_state(s, &s->sec_vectors[ARMV7M_EXCP_USAGE= ], + ARMV7M_EXCP_USAGE, + (value & (1 << 12)) !=3D 0); + nvic_update_pending_state(s, &s->sec_vectors[ARMV7M_EXCP_MEM], + ARMV7M_EXCP_MEM, + (value & (1 << 13)) !=3D 0); + nvic_update_pending_state(s, &s->sec_vectors[ARMV7M_EXCP_SVC], + ARMV7M_EXCP_SVC, + (value & (1 << 15)) !=3D 0); s->sec_vectors[ARMV7M_EXCP_MEM].enabled =3D (value & (1 << 16)= ) !=3D 0; s->sec_vectors[ARMV7M_EXCP_BUS].enabled =3D (value & (1 << 17)= ) !=3D 0; s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =3D (value & (1 << 18)) !=3D 0; - s->sec_vectors[ARMV7M_EXCP_HARD].pending =3D (value & (1 << 21= )) !=3D 0; + nvic_update_pending_state(s, &s->sec_vectors[ARMV7M_EXCP_HARD], + ARMV7M_EXCP_HARD, + (value & (1 << 21)) !=3D 0); /* SecureFault not banked, but RAZ/WI to NS */ s->vectors[ARMV7M_EXCP_SECURE].active =3D (value & (1 << 4)) != =3D 0; s->vectors[ARMV7M_EXCP_SECURE].enabled =3D (value & (1 << 19))= !=3D 0; - s->vectors[ARMV7M_EXCP_SECURE].pending =3D (value & (1 << 20))= !=3D 0; + nvic_update_pending_state(s, &s->vectors[ARMV7M_EXCP_SECURE], + ARMV7M_EXCP_SECURE, + (value & (1 << 20)) !=3D 0); } else { s->vectors[ARMV7M_EXCP_MEM].active =3D (value & (1 << 0)) !=3D= 0; if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* HARDFAULTPENDED is not present in v7M */ - s->vectors[ARMV7M_EXCP_HARD].pending =3D (value & (1 << 21= )) !=3D 0; + nvic_update_pending_state(s, &s->vectors[ARMV7M_EXCP_HARD], + ARMV7M_EXCP_HARD, + (value & (1 << 21)) !=3D 0); } s->vectors[ARMV7M_EXCP_USAGE].active =3D (value & (1 << 3)) != =3D 0; s->vectors[ARMV7M_EXCP_SVC].active =3D (value & (1 << 7)) !=3D= 0; s->vectors[ARMV7M_EXCP_PENDSV].active =3D (value & (1 << 10)) = !=3D 0; s->vectors[ARMV7M_EXCP_SYSTICK].active =3D (value & (1 << 11))= !=3D 0; - s->vectors[ARMV7M_EXCP_USAGE].pending =3D (value & (1 << 12)) = !=3D 0; - s->vectors[ARMV7M_EXCP_MEM].pending =3D (value & (1 << 13)) != =3D 0; - s->vectors[ARMV7M_EXCP_SVC].pending =3D (value & (1 << 15)) != =3D 0; + nvic_update_pending_state(s, &s->vectors[ARMV7M_EXCP_USAGE], + ARMV7M_EXCP_USAGE, + (value & (1 << 12)) !=3D 0); + nvic_update_pending_state(s, &s->vectors[ARMV7M_EXCP_MEM], + ARMV7M_EXCP_MEM, + (value & (1 << 13)) !=3D 0); + nvic_update_pending_state(s, &s->vectors[ARMV7M_EXCP_SVC], + ARMV7M_EXCP_SVC, + (value & (1 << 15)) !=3D 0); s->vectors[ARMV7M_EXCP_MEM].enabled =3D (value & (1 << 16)) != =3D 0; s->vectors[ARMV7M_EXCP_USAGE].enabled =3D (value & (1 << 18)) = !=3D 0; } if (attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MA= SK)) { s->vectors[ARMV7M_EXCP_BUS].active =3D (value & (1 << 1)) !=3D= 0; - s->vectors[ARMV7M_EXCP_BUS].pending =3D (value & (1 << 14)) != =3D 0; + nvic_update_pending_state(s, &s->vectors[ARMV7M_EXCP_BUS], + ARMV7M_EXCP_BUS, + (value & (1 << 14)) !=3D 0); s->vectors[ARMV7M_EXCP_BUS].enabled =3D (value & (1 << 17)) != =3D 0; } /* NMIACT can only be written if the write is of a zero, with @@ -2389,7 +2431,8 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, (attrs.secure || s->itns[startvec + i]) && !(setval =3D=3D 0 && s->vectors[startvec + i].level && !s->vectors[startvec + i].active)) { - s->vectors[startvec + i].pending =3D setval; + nvic_update_pending_state(s, &s->vectors[startvec + i], + startvec + i, setval); } } nvic_irq_update(s); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 077f1f9a74..7542444b18 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -144,6 +144,12 @@ static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); =20 + if (arm_feature(&cpu->env, ARM_FEATURE_M)) { + if (cpu->env.event_register) { + return true; + } + } + return (cpu->power_state !=3D PSCI_OFF) && cpu_test_interrupt(cs, CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e146f7e6c4..657ff4ab20 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -760,6 +760,13 @@ typedef struct CPUArchState { /* Optional fault info across tlb lookup. */ ARMMMUFaultInfo *tlb_fi; =20 + /* + * The event register is shared by all ARM profiles (A/R/M), + * so it is stored in the top-level CPU state. + * WFE/SEV handling is currently implemented only for M-profile. + */ + bool event_register; + /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 0befdb0b28..bbaae34449 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -508,6 +508,24 @@ static const VMStateDescription vmstate_m_mve =3D { }, }; =20 +static bool event_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + return cpu->env.event_register; +} + +static const VMStateDescription vmstate_event =3D { + .name =3D "cpu/event", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D event_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_BOOL(env.event_register, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_m =3D { .name =3D "cpu/m", .version_id =3D 4, @@ -1210,6 +1228,7 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_wfxt_timer, &vmstate_syndrome64, &vmstate_pstate64, + &vmstate_event, NULL } }; diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper.h index 4636d1bc03..5a10a9fba3 100644 --- a/target/arm/tcg/helper.h +++ b/target/arm/tcg/helper.h @@ -60,6 +60,7 @@ DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) DEF_HELPER_1(vesb, void, env) +DEF_HELPER_1(sev, void, env) =20 DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 3fb24c7790..0c3832a47f 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -962,7 +962,9 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t l= r, bool dotailchain, * Now we've done everything that might cause a derived exception * we can go ahead and activate whichever exception we're going to * take (which might now be the derived exception). + * Exception entry sets the event register (ARM ARM R_BPBR) */ + env->event_register =3D true; armv7m_nvic_acknowledge_irq(env->nvic); =20 /* Switch to target security state -- must do this before writing SPSE= L */ @@ -1906,6 +1908,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Otherwise, we have a successful exception exit. */ arm_clear_exclusive(env); arm_rebuild_hflags(env); + + /* Exception return sets the event register (ARM ARM R_BPBR) */ + env->event_register =3D true; qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 4fbd219555..c7ab462d1d 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -469,16 +469,58 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) #endif } =20 +void HELPER(sev)(CPUARMState *env) +{ + CPUState *cs =3D env_cpu(env); + CPU_FOREACH(cs) { + ARMCPU *target_cpu =3D ARM_CPU(cs); + if (arm_feature(&target_cpu->env, ARM_FEATURE_M)) { + target_cpu->env.event_register =3D true; + } + if (!qemu_cpu_is_self(cs)) { + qemu_cpu_kick(cs); + } + } +} + void HELPER(wfe)(CPUARMState *env) { - /* This is a hint instruction that is semantically different - * from YIELD even though we currently implement it identically. - * Don't actually halt the CPU, just yield back to top - * level loop. This is not going into a "low power state" - * (ie halting until some event occurs), so we never take - * a configurable trap to a different exception level. +#ifdef CONFIG_USER_ONLY + /* + * WFE in the user-mode emulator is a NOP. Real-world user-mode code + * shouldn't execute WFE, but if it does, we make it a NOP rather than + * aborting when we try to raise EXCP_HLT. */ - HELPER(yield)(env); + return; +#else + /* + * WFE (Wait For Event) is a hint instruction. + * For Cortex-M (M-profile), we implement the strict architectural beh= avior: + * 1. Check the Event Register (set by SEV or SEVONPEND). + * 2. If set, clear it and continue (consume the event). + */ + if (arm_feature(env, ARM_FEATURE_M)) { + CPUState *cs =3D env_cpu(env); + + if (env->event_register) { + env->event_register =3D false; + return; + } + + cs->exception_index =3D EXCP_HLT; + cs->halted =3D 1; + cpu_loop_exit(cs); + } else { + /* + * For A-profile and others, we rely on the existing "yield" behav= ior. + * Don't actually halt the CPU, just yield back to top + * level loop. This is not going into a "low power state" + * (ie halting until some event occurs), so we never take + * a configurable trap to a different exception level + */ + HELPER(yield)(env); + } +#endif } =20 void HELPER(yield)(CPUARMState *env) diff --git a/target/arm/tcg/t16.decode b/target/arm/tcg/t16.decode index 646c74929d..778fbf1627 100644 --- a/target/arm/tcg/t16.decode +++ b/target/arm/tcg/t16.decode @@ -228,8 +228,9 @@ REVSH 1011 1010 11 ... ... @rdm WFE 1011 1111 0010 0000 WFI 1011 1111 0011 0000 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1011 1111 0100 0000 + # M-profile SEV is implemented. + # TODO: Implement SEV for other profiles, and SEVL for all profiles; m= ay help SMP performance. + SEV 1011 1111 0100 0000 # SEVL 1011 1111 0101 0000 =20 # The canonical nop has the second nibble as 0000, but the whole of the diff --git a/target/arm/tcg/t32.decode b/target/arm/tcg/t32.decode index d327178829..49b8d0037e 100644 --- a/target/arm/tcg/t32.decode +++ b/target/arm/tcg/t32.decode @@ -369,8 +369,9 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm WFE 1111 0011 1010 1111 1000 0000 0000 0010 WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # M-profile SEV is implemented. + # TODO: Implement SEV for other profiles, and SEVL for all profile= s; may help SMP performance. + SEV 1111 0011 1010 1111 1000 0000 0000 0100 # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 ESB 1111 0011 1010 1111 1000 0000 0001 0000 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 63735d9789..c90b0106f7 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3241,14 +3241,30 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD = *a) return true; } =20 +static bool trans_SEV(DisasContext *s, arg_SEV *a) +{ + /* + * Currently SEV is a NOP for non-M-profile and in user-mode emulation. + * For system-mode M-profile, it sets the event register. + */ +#ifndef CONFIG_USER_ONLY + if (arm_dc_feature(s, ARM_FEATURE_M)) { + gen_helper_sev(tcg_env); + } +#endif + return true; +} + static bool trans_WFE(DisasContext *s, arg_WFE *a) { /* * When running single-threaded TCG code, use the helper to ensure that - * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we - * just skip this instruction. Currently the SEV/SEVL instructions, - * which are *one* of many ways to wake the CPU from WFE, are not - * implemented so we can't sleep like WFI does. + * the next round-robin scheduled vCPU gets a crack. + * + * For Cortex-M, we implement the architectural WFE behavior (sleeping + * until an event occurs or the Event Register is set). + * For other profiles, we currently treat this as a NOP or yield, + * to preserve existing performance characteristics. */ if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { gen_update_pc(s, curr_insn_len(s)); @@ -6807,6 +6823,11 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cpu) break; case DISAS_WFE: gen_helper_wfe(tcg_env); + /* + * The helper can return if the event register is set, so we + * must go back to the main loop to check for events. + */ + tcg_gen_exit_tb(NULL, 0); break; case DISAS_YIELD: gen_helper_yield(tcg_env); --=20 2.43.0 From nobody Tue Feb 10 20:06:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770731629; cv=none; d=zohomail.com; s=zohoarc; b=kOP5BQZffP66Xm2jum7PD2nlb+zp5DOmbPOtrQRgLqxxBd6/l8OY/tvr9d0h5FGRO2tR3xYEy8fohgEBYa6ts0wBnZ+rcUoTZ6jxSDT4EHccPALtZtWv5p7aexGkkvvHbmjlO57i3yoY1hkuLn7Kenno8wmqmjlhd9QWqBiJZlM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770731629; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=GgDAOb9kz7PXxXREyH/qdM2DkTVepbIG5XlZE6jyCCk=; b=c475S1b3OfOqk+JE1jxH0p6NjscjIH8c+gOByYrPGOOUBaOp0lz581YQ/m3ORQvTPg/lteVqu7qOrOSIHxaBCQnMTKmCKvUbH8BEiKnWxrk+nOHmaiwC2G1BoIUOY0ZFeOCs3YYfSREL1IXqNgTP/VrBPu6Ef7i1EH/VlXNUISc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770731629929834.12165346781; Tue, 10 Feb 2026 05:53:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vpoAP-0002Gd-J6; Tue, 10 Feb 2026 08:52:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vpoAN-0002FN-Ce for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:35 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vpoAK-0006OY-OQ for qemu-devel@nongnu.org; Tue, 10 Feb 2026 08:52:35 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-47ee76e8656so12865285e9.0 for ; Tue, 10 Feb 2026 05:52:32 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5d77f9sm64344875e9.3.2026.02.10.05.52.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:52:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770731551; x=1771336351; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=GgDAOb9kz7PXxXREyH/qdM2DkTVepbIG5XlZE6jyCCk=; b=vUIuzON0vegThJgtJIReirLzbG6t7jrszieT2YbLribSD8lKITi4tlfCqLX9WPKX3S 51AYX64xfsnQOaNk4D2LMrdC5J0MZqeIW1mNg88LPRXNOXtXl+RrmGLCZvQuSeNDOVd/ 4u894uPnaMqPtU/FXzM6SfeypSoGMsOVyMju4bmLZkkTM1upDQJ3YlB7nAcTLqWI15Aq HjxkmQ5S4RGU4yiVZAJCvkbLmqsB9kQlAIYuMTXMJvWdfKi81cGxMRa5kt/HOR5mLSgD +s+Fcnbs75u9Pnk4/UnVJkxLlEdKAlkGkdRc2NVf4RywibCSvcLQWPMBRQDc50cnHOKZ 4fHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770731551; x=1771336351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=GgDAOb9kz7PXxXREyH/qdM2DkTVepbIG5XlZE6jyCCk=; b=HYbSQO/T3BRhSXzaLdByAa71NCG8VpkfkKcziogg45uBCn3/PBDIc/cYt3tqDwsG5d hbK7B6GD+s5qRE0BWR1H32Z1Xh9aXmcbNAqJdJGKyuuklr2Or7Q2IFxSorp8gQG3sPdi fOFUUYR1nlcHkDkTztyy6yxTrx3AWad2GL01qAiukP8sn+WA9ZXOqxRR+3g04nxWumCv kO2T4GZzwqa9CEdfheC8juyUz4GmQCKjlf87CZrs4ST2SENoTdJXwGMtKFl/2n83FEoG Fu04Za37D9Y1C//VPY4LRbHobfD7JFGWGqBoz6C6+Fh+8/3Nj0mBxgd7OveHe3ch+2XF mVUg== X-Gm-Message-State: AOJu0YyDg0I3AuwT7s/O2/Qreuh/wanQKorxxpk1Q54HmaqPoYj+B7vI cmVjrnfQhOLqXCZRuPX0pu3zGSFcidIa0TIiryBS7EtofftezymsPQU5in+/QItd3Tkj+D/musN LaYA2 X-Gm-Gg: AZuq6aJTU/dQ0EbTnPpkick8oiIl7K9/a+XxwkjS0oqp9OPuJwt5xKjm6c/6IHk597f dU8+mP2/PkM/7ebbPz7vLEihW9tOwjshBTpxXTBLKnU5ImQ/P5L6CmUx9Nb36XQmaxml+KrPPSJ bNmaVHbxa4QCdSNVZCQfUXNoctCcpWOi5Uqu5lq1u0I/LvkWiKpfKygL6m5egN/VqkChAzEuOe4 cyG4szB3LpEGu29PTepjB4jJyEQWARQT8jFHGdxne4PdEJQk1m9pSE4WhZxshB6I6X5iZmbpW1e 6XTqk/GTlQYBBQwOCE0gfVD2NAYUE+lacBf8VM4+rm4V/tFJIdngkw5+DUyTimGhKyq6jd+m8YG jmVPE2LxYvZI+TF8JfH43Gm0X6zYWRPuM9BYws/oKJjbz+K/uQo3K1+bumFJlLXQukkYnTalE0L vLLsg+Xj2pZaEMIJ95ucrvLNqDdTq/0ED+0uMnaNzVrss6C0Px6L0vKnG7RFlKefFU7BR/+YGWc JiVp4Vt1mJNheB5EYetDwbbWDrM0MQ= X-Received: by 2002:a05:600c:3590:b0:477:79c7:8994 with SMTP id 5b1f17b1804b1-48320236b01mr234506765e9.30.1770731551153; Tue, 10 Feb 2026 05:52:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/26] target/arm: implement FEAT_E2H0 Date: Tue, 10 Feb 2026 13:52:06 +0000 Message-ID: <20260210135206.229528-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260210135206.229528-1-peter.maydell@linaro.org> References: <20260210135206.229528-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770731632695154100 From: Alex Benn=C3=A9e FEAT_E2H0 is a formalisation of the existing behaviour of HCR_EL2.E2H being programmable to switch between EL2 host mode and the "traditional" nVHE EL2 mode. This implies at some point we might want to model CPUs without FEAT_E2H0 which will always have EL2 host mode enabled. There are two values to represent no E2H0 systems of which 0b1110 will make HCR_EL2.NV1 RES0 for FEAT_NV systems. For FEAT_NV2 the NV1 bit is always valid. Message-ID: <20260130181648.628364-1-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Mohamed Mediouni Message-id: 20260205210231.888199-1-alex.bennee@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 15 +++++++++++++++ target/arm/helper.c | 21 +++++++++++++++------ 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index e0d5f9886e..7787691853 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -54,6 +54,7 @@ the following architecture extensions: - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) +- FEAT_E2H0 (Programming of HCR_EL2.E2H) - FEAT_EBF16 (AArch64 Extended BFloat16 instructions) - FEAT_ECV (Enhanced Counter Virtualization) - FEAT_EL0 (Support for execution at EL0) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index f7b1437340..49c50e850a 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -347,6 +347,7 @@ FIELD(ID_AA64MMFR3, ADERR, 56, 4) FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) =20 FIELD(ID_AA64MMFR4, ASID2, 8, 4) +FIELD(ID_AA64MMFR4, E2H0, 24, 4) =20 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) @@ -1376,6 +1377,20 @@ static inline bool isar_feature_aa64_asid2(const ARM= ISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) !=3D 0; } =20 +/* + * Note the E2H0 ID fields is signed, increasingly negative as more + * isn't implemented. + */ +static inline bool isar_feature_aa64_e2h0(const ARMISARegisters *id) +{ + return FIELD_SEX64_IDREG(id, ID_AA64MMFR4, E2H0) >=3D 0; +} + +static inline bool isar_feature_aa64_nv1_res0(const ARMISARegisters *id) +{ + return FIELD_SEX64_IDREG(id, ID_AA64MMFR4, E2H0) <=3D -2; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index e86ceb130c..8c5769477c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3776,7 +3776,8 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) } =20 if (arm_feature(env, ARM_FEATURE_AARCH64)) { - if (cpu_isar_feature(aa64_vh, cpu)) { + if (cpu_isar_feature(aa64_vh, cpu) && + cpu_isar_feature(aa64_e2h0, cpu)) { valid_mask |=3D HCR_E2H; } if (cpu_isar_feature(aa64_ras, cpu)) { @@ -3801,7 +3802,10 @@ static void do_hcr_write(CPUARMState *env, uint64_t = value, uint64_t valid_mask) valid_mask |=3D HCR_GPF; } if (cpu_isar_feature(aa64_nv, cpu)) { - valid_mask |=3D HCR_NV | HCR_NV1 | HCR_AT; + valid_mask |=3D HCR_NV | HCR_AT; + if (!cpu_isar_feature(aa64_nv1_res0, cpu)) { + valid_mask |=3D HCR_NV1; + } } if (cpu_isar_feature(aa64_nv2, cpu)) { valid_mask |=3D HCR_NV2; @@ -3817,10 +3821,15 @@ static void do_hcr_write(CPUARMState *env, uint64_t= value, uint64_t valid_mask) /* Clear RES0 bits. */ value &=3D valid_mask; =20 - /* RW is RAO/WI if EL1 is AArch64 only */ - if (arm_feature(env, ARM_FEATURE_AARCH64) && - !cpu_isar_feature(aa64_aa32_el1, cpu)) { - value |=3D HCR_RW; + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* RW is RAO/WI if EL1 is AArch64 only */ + if (!cpu_isar_feature(aa64_aa32_el1, cpu)) { + value |=3D HCR_RW; + } + /* Strictly E2H is RES1 unless FEAT_E2H0 relaxes the requirement */ + if (!cpu_isar_feature(aa64_e2h0, cpu)) { + value |=3D HCR_E2H; + } } =20 /* --=20 2.43.0