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Tsirkin" , BALATON Zoltan , Mark Cave-Ayland , Pierrick Bouvier , Zide Chen , Dapeng Mi , Zhao Liu , qemu-devel@nongnu.org, devel@lists.libvirt.org Subject: [PATCH v2 18/21] target/i386: mark x-consistent-cache property as internal-only Date: Tue, 10 Feb 2026 11:23:45 +0800 Message-Id: <20260210032348.987549-19-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260210032348.987549-1-zhao1.liu@intel.com> References: <20260210032348.987549-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770692407954154100 Content-Type: text/plain; charset="utf-8" x-consistent-cache property is a compatibility option that defaults to "true". For old machines, it is set to "false" to maintain the (legacy) inconsistent cache model for Intel CPUs. In fact, such wrong and inconsistent cache model should be treated as buggy "hardware", so that there is no valid use case for users to manually disable this property. Therefore, mark it as internal-only via OBJ_PROP_FLAG_INTERNAL flag, and prohibit all external settings. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3766d453157b..c2f99b98014a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10541,7 +10541,8 @@ static const Property x86_cpu_properties[] =3D { * own cache information (see x86_cpu_load_def()). */ DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), - DEFINE_PROP_BOOL("x-consistent-cache", X86CPU, consistent_cache, true), + DEFINE_PROP_BOOL("x-consistent-cache", X86CPU, consistent_cache, true, + .flags =3D OBJ_PROP_FLAG_INTERNAL), DEFINE_PROP_BOOL("legacy-multi-node", X86CPU, legacy_multi_node, false= ), DEFINE_PROP_BOOL("xen-vapic", X86CPU, xen_vapic, false), =20 --=20 2.34.1