From nobody Tue Feb 10 16:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770723046; cv=none; d=zohomail.com; s=zohoarc; b=fYO8FXL6wRFffDoXG1bnbU55/J46G78/aUM71J/UILJTccdGGQDAbMN63tIvkBGjjRqRP8oNN9nx5rScPZhu7bfL18KQkp0/y9sCa56SgVByI2fIv796q1iKTaIdZtcWUsZ/u0NZOUeN4uBWaX5yMlcN9VGZAEI0wT4MlNUVAYw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770723046; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=1QWf+2DdLLTe76hTUNOLUTqqd9JLohu4JMeszhVSw/g=; b=k6Ek0eQrdkI4Utkp5jXkbdc27RDBcBdO8gpM+pMwwgNnXfZU4sF3OWagvHN9lP0dfXq4UOukV9QfEmexWVRomLC/g+3uNRYONzBqnPIfrhcEUiETx+jA3qGGsdT0CcO86j1SkD29SxB0/bpXN491ZX/BP+h7mBtcuhiQt/4ELiI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770723045620960.8901400120737; Tue, 10 Feb 2026 03:30:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vplwj-0005Jb-DT; Tue, 10 Feb 2026 06:30:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vplwh-0005Gg-Aj for qemu-devel@nongnu.org; Tue, 10 Feb 2026 06:30:19 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vplwf-0008I4-L1 for qemu-devel@nongnu.org; Tue, 10 Feb 2026 06:30:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=1QWf+2DdLLTe76hTUNOLUTqqd9JLohu4JMeszhVSw/g=; b=Uczrj3bkbWEskK/ scWEvH8z+BVg54cYL2aYEgbUaMW+Jjt4J/ihU7zQGj7CRpT7PBJpk4MGS6eKimzcQEQ0KKBsM76J6 FxhybC3x73ip7beBuKw7xxif1siALMC/uKaLViAoSIozaZ+0wqhfNTI2hoo2EyLxcClbxufA/MAQE R0=; Date: Tue, 10 Feb 2026 12:33:12 +0100 Subject: [PATCH v4 1/8] target/alpha: Introduce alpha_phys_addr_space_bits() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-phys_addr-v4-1-725a589e83c8@rev.ng> References: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> In-Reply-To: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn, deller@gmx.de Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770723047704158500 In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, add a a runtime function to correctly represent the size of the physical address space for EV4-6 based on the current CPU version. Reviewed-by: Richard Henderson Signed-off-by: Anton Johansson Suggested-by: Richard Henderson --- linux-user/alpha/target_proc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/alpha/target_proc.h b/linux-user/alpha/target_proc.h index 71949d380d..6b491ffa3a 100644 --- a/linux-user/alpha/target_proc.h +++ b/linux-user/alpha/target_proc.h @@ -6,6 +6,7 @@ #ifndef ALPHA_TARGET_PROC_H #define ALPHA_TARGET_PROC_H =20 +#include "qemu/osdep.h" #include "target/alpha/cpu.h" =20 static uint8_t alpha_phys_addr_space_bits(CPUAlphaState *env) --=20 2.52.0 From nobody Tue Feb 10 16:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770723051; cv=none; d=zohomail.com; s=zohoarc; b=LQ6KUnzDL2fFJiMg/xzacuUmJH3N1QdyMp6oAw+meq1kX3qwJs5sI1gRVKu5pj0LbTrBuZRrYe5f33BYG7NR+oAtZUswsT0r5GA18qSfuS/6eQO0xArvbz5acj4ojNR7A+zG1zsOVbaREgwd+LdqpmugvbEDiYeNmlUlx3IB7T4= ARC-Message-Signature: i=1; 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Date: Tue, 10 Feb 2026 12:33:13 +0100 Subject: [PATCH v4 2/8] target/hppa: Define PA[20|1X] physical address space size MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-phys_addr-v4-2-725a589e83c8@rev.ng> References: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> In-Reply-To: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn, deller@gmx.de Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770723053638154100 When converting virtual to physical addresses, TARGET_PHYS_ADDR_SPACE_BITS is used under PA-RISC 2.0, and an explicit cast to uint32_t is used under PA-RISC 1.X. Replace the former with a more specific macro limited to mem_helper.c, and make the latter conversion explicit by defining the size of the physical address space for PA-RISC 1.X. Note: while 44 bits should be used for the 64-bit address space running a C3700, 40 bits is still chosen as this is expected by the SeaBIOS functional test. Reviewed-by: Richard Henderson Signed-off-by: Anton Johansson Suggested-by: Richard Henderson --- target/hppa/cpu.h | 1 + target/hppa/mem_helper.c | 32 +++++++++++++++++++++++++++----- 2 files changed, 28 insertions(+), 5 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 012e54f8f6..092e647ccf 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -336,6 +336,7 @@ static inline vaddr hppa_form_gva(CPUHPPAState *env, ui= nt64_t spc, return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } =20 +hwaddr hppa_abs_to_phys_pa1x(vaddr addr); hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); =20 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index cce82e6599..9199d1e06a 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,6 +29,28 @@ #include "hw/core/cpu.h" #include "trace.h" =20 +/* + * 64-bit (PA-RISC 2.0) machines are assumed to run PA-8700, and 32-bit + * machines 7300LC. This should give 44 and 32 bits of physical address + * space respectively. + * + * CPU model Physical address space bits + * PA-7000--7300LC 32 + * PA-8000--8600 40 + * PA-8700--8900 44 + * + * FIXME: However, the SeaBIOS firmware that is that tested against + * uses 40-bit physical addresses, despite supposedly running a C3700 + * with a PA-8700 cpu, so use 40-bits for 64-bit. + */ +#define HPPA_PHYS_ADDR_SPACE_BITS_PA20 40 +#define HPPA_PHYS_ADDR_SPACE_BITS_PA1X 32 + +hwaddr hppa_abs_to_phys_pa1x(vaddr addr) +{ + return extract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA1X); +} + hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) { /* @@ -42,8 +64,8 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) * Since the supported physical address space is below 54 bits, the * H-8 algorithm is moot and all that is left is to truncate. */ - QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 54); - return sextract64(addr, 0, TARGET_PHYS_ADDR_SPACE_BITS); + QEMU_BUILD_BUG_ON(HPPA_PHYS_ADDR_SPACE_BITS_PA20 > 54); + return sextract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); } =20 hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) @@ -67,7 +89,7 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) * is what can be seen on physical machines too. */ addr =3D (uint32_t)addr; - addr |=3D -1ull << (TARGET_PHYS_ADDR_SPACE_BITS - 4); + addr |=3D -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 4); } return addr; } @@ -217,7 +239,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr = addr, int mmu_idx, if (hppa_is_pa20(env)) { phys =3D hppa_abs_to_phys_pa2_w0(addr); } else { - phys =3D (uint32_t)addr; + phys =3D hppa_abs_to_phys_pa1x(addr); } break; default: @@ -558,7 +580,7 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong = r1, /* Align per the page size. */ ent->pa &=3D TARGET_PAGE_MASK << mask_shift; /* Ignore the bits beyond physical address space. */ - ent->pa =3D sextract64(ent->pa, 0, TARGET_PHYS_ADDR_SPACE_BITS); + ent->pa =3D sextract64(ent->pa, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); =20 ent->t =3D extract64(r2, 61, 1); ent->d =3D extract64(r2, 60, 1); --=20 2.52.0 From nobody Tue Feb 10 16:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=B6igatEMjsC0RKOlyW4bsYPSobRk1IZSYSyjMkpKf8o=; b=jQzsvmSaPgDQaef uURAyF7OjoZCrZkzCcqtiRtesqqFqM1f8soPuPq9iQFkDSBtIZip7mfiL5fo85dqP7fwvXHC878Yb 8u7S9QyDJtB1nenTX1LxHEiEGAbF5/GqHmNLR7S4FeQB4We6RT4yeSPBfmdaN5mpurwT7zAOm/+yS GQ=; Date: Tue, 10 Feb 2026 12:33:14 +0100 Subject: [PATCH v4 3/8] hw/hppa: Use hppa_abs_to_phys_pa1x() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-phys_addr-v4-3-725a589e83c8@rev.ng> References: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> In-Reply-To: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn, deller@gmx.de Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770723105993154100 Makes the physical address space conversion for 32 bit machines more explicit, using the translation function defined in mem_helper.c. Signed-off-by: Anton Johansson Suggested-by: Richard Henderson --- hw/hppa/machine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 960aefc9e2..472b90aab0 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -181,7 +181,7 @@ static uint64_t linux_kernel_virt_to_phys(void *opaque,= uint64_t addr) =20 static uint64_t translate_pa10(void *dummy, uint64_t addr) { - return (uint32_t)addr; + return hppa_abs_to_phys_pa1x(addr); } =20 static uint64_t translate_pa20(void *dummy, uint64_t addr) --=20 2.52.0 From nobody Tue Feb 10 16:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770723075; cv=none; d=zohomail.com; s=zohoarc; b=Yxo5SqG03rJznlu5Hn2hHqDJXw71PaoWYm/0ejdOrXMncyWWYEIWqRYvN1hT5TEnJ3sOIK3byZTwQOSpEMF/E+UgMLoBvFc7z9p0x5iWjc+JEM5lnG22K9f5kyuelMGmaPwvsdA7vwpYDLv4kasjutFqErUEmSmVKFzhKlKPTEI= ARC-Message-Signature: i=1; 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Date: Tue, 10 Feb 2026 12:33:15 +0100 Subject: [PATCH v4 4/8] target/i386: Drop physical address range checks MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-phys_addr-v4-4-725a589e83c8@rev.ng> References: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> In-Reply-To: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn, deller@gmx.de Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770723077849154100 Since TARGET_PHYS_ADDR_SPACE_BITS is now fixed to 64 bits for all targets we can remove range checks on cpu->phys_bits and TCG_PHYS_ADDR_BITS. Signed-off-by: Anton Johansson Suggested-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 2 -- target/i386/cpu.c | 9 +++------ target/i386/kvm/kvm.c | 3 +-- 3 files changed, 4 insertions(+), 10 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index e41cbda407..f4b2ff740d 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -31,8 +31,6 @@ # define TCG_PHYS_ADDR_BITS 36 #endif =20 -QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS); - /** * x86_cpu_do_interrupt: * @cpu: vCPU the interrupt is to be handled by. diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0a7b884528..11755a5a7e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9943,12 +9943,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) * accel-specific code in cpu_exec_realizefn. */ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { - if (cpu->phys_bits && - (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || - cpu->phys_bits < 32)) { - error_setg(errp, "phys-bits should be between 32 and %u " - " (but is %u)", - TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); + if (cpu->phys_bits && cpu->phys_bits < 32) { + error_setg(errp, "phys-bits should be at least 32" + " (but is %u)", cpu->phys_bits); return; } /* diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 0c940d4b64..a48be342fe 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4765,8 +4765,7 @@ static int kvm_get_msrs(X86CPU *cpu) */ =20 if (cpu->fill_mtrr_mask) { - QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); - assert(cpu->phys_bits <=3D TARGET_PHYS_ADDR_SPACE_BITS); + assert(cpu->phys_bits <=3D 52); mtrr_top_bits =3D MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_b= its); } else { mtrr_top_bits =3D 0; --=20 2.52.0 From nobody Tue Feb 10 16:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770723095049897.4703445944241; Tue, 10 Feb 2026 03:31:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vplx0-0005Oh-Eo; Tue, 10 Feb 2026 06:30:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vplwt-0005ML-3I for qemu-devel@nongnu.org; Tue, 10 Feb 2026 06:30:31 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vplwr-0008KQ-9A for qemu-devel@nongnu.org; Tue, 10 Feb 2026 06:30:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=Z80TN9jbZwmUXaaLMZy0r2yPGv1D70SCG1gJo7mX+Gk=; b=OZAVLzbDprh6p1p BYqButiHmG9XUxg2Grz/yohxXnuiV/LCwlO4TKcR1vswnQhgdugQQAEnJFec3j1iW/rvFeJ8ig07C AiCocQyMUbKiYk5LergMV+nCNw1d6sw0HwprRRBn6eNx0Ms1k2kcUPKfmY6rVkXSkQJt7bVymWl1X iI=; Date: Tue, 10 Feb 2026 12:33:16 +0100 Subject: [PATCH v4 5/8] target/loongarch: Introduce loongarch_palen_mask() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-phys_addr-v4-5-725a589e83c8@rev.ng> References: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> In-Reply-To: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn, deller@gmx.de Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770723097218158500 In preparation for dropping TARGET_PHYS_ADDR_SPACE_BITS, define a runtime function to construct a mask from the PALEN cpucfg field. The mask is then used when converting from virtual to physical addresses. Signed-off-by: Anton Johansson Suggested-by: Richard Henderson --- target/loongarch/cpu-mmu.h | 1 + target/loongarch/internals.h | 1 - target/loongarch/cpu_helper.c | 14 +++++++++++--- target/loongarch/tcg/tlb_helper.c | 12 ++++++++---- 4 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 2259de9d36..3286accc14 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -98,5 +98,6 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *= context, void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, unsigned int level); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +uint64_t loongarch_palen_mask(CPULoongArchState *env); =20 #endif /* LOONGARCH_CPU_MMU_H */ diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h index 8793bd9df6..e01dbed40f 100644 --- a/target/loongarch/internals.h +++ b/target/loongarch/internals.h @@ -13,7 +13,6 @@ #define FCMP_UN 0b0100 /* unordered */ #define FCMP_GT 0b1000 /* fp0 > fp1 */ =20 -#define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS) #define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS) =20 void loongarch_translate_init(void); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 51ad9ff2b4..c94361ba17 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -147,6 +147,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext= *context, { CPUState *cs =3D env_cpu(env); hwaddr index =3D 0, phys =3D 0; + uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; uint64_t base, pte; int level; @@ -154,13 +155,14 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUConte= xt *context, TLBRet ret; MemTxResult ret1; =20 + address =3D context->addr; if ((address >> 63) & 0x1) { base =3D env->CSR_PGDH; } else { base =3D env->CSR_PGDL; } - base &=3D TARGET_PHYS_MASK; + base &=3D palen_mask; =20 for (level =3D 4; level >=3D 0; level--) { get_dir_base_width(env, &dir_base, &dir_width, level); @@ -181,7 +183,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext= *context, break; } else { /* Discard high bits with page directory table */ - base &=3D TARGET_PHYS_MASK; + base &=3D palen_mask; } } } @@ -315,7 +317,7 @@ TLBRet get_physical_address(CPULoongArchState *env, MMU= Context *context, /* Check PG and DA */ address =3D context->addr; if (da & !pg) { - context->physical =3D address & TARGET_PHYS_MASK; + context->physical =3D address & loongarch_palen_mask(env); context->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; context->mmu_index =3D MMU_DA_IDX; return TLBRET_MATCH; @@ -364,3 +366,9 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) } return context.physical; } + +uint64_t loongarch_palen_mask(CPULoongArchState *env) +{ + uint64_t phys_bits =3D FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN); + return MAKE_64BIT_MASK(0, phys_bits); +} diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index b6e9a3a3c7..c1dc77a8f8 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -692,8 +692,10 @@ target_ulong helper_lddir(CPULoongArchState *env, targ= et_ulong base, CPUState *cs =3D env_cpu(env); uint64_t badvaddr; hwaddr index, phys; + uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; =20 + if (unlikely((level =3D=3D 0) || (level > 4))) { qemu_log_mask(LOG_GUEST_ERROR, "Attepted LDDIR with level %u\n", level); @@ -715,11 +717,11 @@ target_ulong helper_lddir(CPULoongArchState *env, tar= get_ulong base, } =20 badvaddr =3D env->CSR_TLBRBADV; - base =3D base & TARGET_PHYS_MASK; + base =3D base & palen_mask; get_dir_base_width(env, &dir_base, &dir_width, level); index =3D (badvaddr >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; - return ldq_le_phys(cs->as, phys) & TARGET_PHYS_MASK; + return ldq_le_phys(cs->as, phys) & palen_mask; } =20 void helper_ldpte(CPULoongArchState *env, target_ulong base, target_ulong = odd, @@ -730,9 +732,11 @@ void helper_ldpte(CPULoongArchState *env, target_ulong= base, target_ulong odd, uint64_t badv; uint64_t ptbase =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTBASE); uint64_t ptwidth =3D FIELD_EX64(env->CSR_PWCL, CSR_PWCL, PTWIDTH); + uint64_t palen_mask =3D loongarch_palen_mask(env); uint64_t dir_base, dir_width; uint8_t ps; =20 + /* * The parameter "base" has only two types, * one is the page table base address, @@ -740,7 +744,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong = base, target_ulong odd, * and the other is the huge page entry, * whose bit 6 should be 1. */ - base =3D base & TARGET_PHYS_MASK; + base =3D base & palen_mask; if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* * Gets the huge page level and Gets huge page size. @@ -781,7 +785,7 @@ void helper_ldpte(CPULoongArchState *env, target_ulong = base, target_ulong odd, ptoffset0 =3D ptindex << 3; ptoffset1 =3D (ptindex + 1) << 3; phys =3D base | (odd ? ptoffset1 : ptoffset0); - tmp0 =3D ldq_le_phys(cs->as, phys) & TARGET_PHYS_MASK; + tmp0 =3D ldq_le_phys(cs->as, phys) & palen_mask; ps =3D ptbase; } =20 --=20 2.52.0 From nobody Tue Feb 10 16:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=3305ChYpDzQijvvnIU5430Ds7+4YJl3MX19qkN2nOSM=; b=iHzlm84ha35VAP7 0skHDpLBubFGSe19MXUhBfOflBkCLa/ZlEKLg+c3Vfk2dry2M+a6X6PToi8muFUDGEyCAhj3JYE2j rTEuQD3W/dsDLYCEWKnwzjFVuXbp5E0IEn1Oppifl/tnVDytqDbB81XVtnl4TCUoGNp1hrLwTb3ZQ Qw=; Date: Tue, 10 Feb 2026 12:33:17 +0100 Subject: [PATCH v4 6/8] hw/loongarch: Use loongarch_palen_mask() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-phys_addr-v4-6-725a589e83c8@rev.ng> References: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> In-Reply-To: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn, deller@gmx.de Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770723110100154100 Replaces remaining uses of TARGET_PHYS_ADDR_SPACE_BITS with runtime calls to loongarch_palen_mask() to fetch the physical address mask from the cpucfg PALEN field. Signed-off-by: Anton Johansson Suggested-by: Richard Henderson --- include/hw/loongarch/boot.h | 3 ++- hw/loongarch/boot.c | 28 ++++++++++++++++------------ hw/loongarch/virt.c | 5 ++++- 3 files changed, 22 insertions(+), 14 deletions(-) diff --git a/include/hw/loongarch/boot.h b/include/hw/loongarch/boot.h index 9819f7fbe3..4984322f75 100644 --- a/include/hw/loongarch/boot.h +++ b/include/hw/loongarch/boot.h @@ -113,6 +113,7 @@ struct memmap_entry { uint32_t reserved; }; =20 -void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *i= nfo); +void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *i= nfo, + uint64_t phys_addr_mask); =20 #endif /* HW_LOONGARCH_BOOT_H */ diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c index 711d5ffbbc..ef8eae237c 100644 --- a/hw/loongarch/boot.c +++ b/hw/loongarch/boot.c @@ -217,10 +217,12 @@ static void init_cmdline(struct loongarch_boot_info *= info, void *p, void *start) =20 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) { - return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS); + uint64_t *phys_addr_mask =3D opaque; + return addr & *phys_addr_mask; } =20 static int64_t load_loongarch_linux_image(const char *filename, + uint64_t phys_addr_mask, uint64_t *kernel_entry, uint64_t *kernel_low, uint64_t *kernel_high) @@ -251,10 +253,8 @@ static int64_t load_loongarch_linux_image(const char *= filename, } =20 /* Early kernel versions may have those fields in virtual address */ - *kernel_entry =3D extract64(le64_to_cpu(hdr->kernel_entry), - 0, TARGET_PHYS_ADDR_SPACE_BITS); - *kernel_low =3D extract64(le64_to_cpu(hdr->load_offset), - 0, TARGET_PHYS_ADDR_SPACE_BITS); + *kernel_entry =3D le64_to_cpu(hdr->kernel_entry) & phys_addr_mask; + *kernel_low =3D le64_to_cpu(hdr->load_offset) & phys_addr_mask; *kernel_high =3D *kernel_low + size; =20 rom_add_blob_fixed(filename, buffer, size, *kernel_low); @@ -303,19 +303,21 @@ static ram_addr_t alloc_initrd_memory(struct loongarc= h_boot_info *info, exit(1); } =20 -static int64_t load_kernel_info(struct loongarch_boot_info *info) +static int64_t load_kernel_info(struct loongarch_boot_info *info, + uint64_t phys_addr_mask) { uint64_t kernel_entry, kernel_low, kernel_high, initrd_offset =3D 0; ssize_t kernel_size; =20 kernel_size =3D load_elf(info->kernel_filename, NULL, - cpu_loongarch_virt_to_phys, NULL, + cpu_loongarch_virt_to_phys, &phys_addr_mask, &kernel_entry, &kernel_low, &kernel_high, NULL, ELFDATA2LSB, EM_LOONGARCH, 1, 0); - kernel_entry =3D cpu_loongarch_virt_to_phys(NULL, kernel_entry); + kernel_entry =3D cpu_loongarch_virt_to_phys(&phys_addr_mask, kernel_en= try); if (kernel_size < 0) { kernel_size =3D load_loongarch_linux_image(info->kernel_filename, + phys_addr_mask, &kernel_entry, &kernel_lo= w, &kernel_high); } @@ -395,14 +397,15 @@ static void init_boot_rom(MachineState *ms, } =20 static void loongarch_direct_kernel_boot(MachineState *ms, - struct loongarch_boot_info *info) + struct loongarch_boot_info *info, + uint64_t phys_addr_mask) { void *p, *bp; int64_t kernel_addr =3D VIRT_FLASH0_BASE; uint64_t *data; =20 if (info->kernel_filename) { - kernel_addr =3D load_kernel_info(info); + kernel_addr =3D load_kernel_info(info, phys_addr_mask); } else { if (!qtest_enabled()) { warn_report("No kernel provided, booting from flash drive."); @@ -429,7 +432,8 @@ static void loongarch_direct_kernel_boot(MachineState *= ms, g_free(bp); } =20 -void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *i= nfo) +void loongarch_load_kernel(MachineState *ms, struct loongarch_boot_info *i= nfo, + uint64_t phys_addr_mask) { LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(ms); =20 @@ -440,6 +444,6 @@ void loongarch_load_kernel(MachineState *ms, struct loo= ngarch_boot_info *info) if (lvms->bios_loaded) { loongarch_firmware_boot(lvms, info); } else { - loongarch_direct_kernel_boot(ms, info); + loongarch_direct_kernel_boot(ms, info, phys_addr_mask); } } diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index a75968e4c9..9e26c25c23 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -34,6 +34,7 @@ #include "hw/misc/unimp.h" #include "hw/loongarch/fw_cfg.h" #include "target/loongarch/cpu.h" +#include "target/loongarch/cpu-mmu.h" #include "hw/firmware/smbios.h" #include "qapi/qapi-visit-common.h" #include "hw/acpi/generic_event_device.h" @@ -928,6 +929,7 @@ static void virt_init(MachineState *machine) hwaddr base, size, ram_size =3D machine->ram_size; MachineClass *mc =3D MACHINE_GET_CLASS(machine); Object *cpuobj; + uint64_t phys_addr_mask =3D 0; =20 if (!cpu_model) { cpu_model =3D LOONGARCH_CPU_TYPE_NAME("la464"); @@ -1017,7 +1019,8 @@ static void virt_init(MachineState *machine) qemu_register_powerdown_notifier(&lvms->powerdown_notifier); =20 lvms->bootinfo.ram_size =3D ram_size; - loongarch_load_kernel(machine, &lvms->bootinfo); + phys_addr_mask =3D loongarch_palen_mask(&LOONGARCH_CPU(first_cpu)->env= ); + loongarch_load_kernel(machine, &lvms->bootinfo, phys_addr_mask); } =20 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, --=20 2.52.0 From nobody Tue Feb 10 16:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770723104; cv=none; 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bh=Yvjn4hcvICFMZZkelelqcz1XeQe1JxSatdUgrAWmycM=; b=Z4whQu8lbobT7lt RsEfF51fIxFOpqalJbgbwBXOhQERtbIafpIjEO/KLTIQTE9Cw+5rjR9XBsTJJ87BpaLsn5dxbJYbm Ad1rSMsSegq/YX1Ak+alhp8Xdor1DgSW1IsHUt4v9XJ4/sz155ipIBevpag2cmO4TVdnLS5BzpwDC og=; Date: Tue, 10 Feb 2026 12:33:18 +0100 Subject: [PATCH v4 7/8] hw/riscv: Fix IOMMU PAS capability to 56 bits MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-phys_addr-v4-7-725a589e83c8@rev.ng> References: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> In-Reply-To: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn, deller@gmx.de Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770723106000154100 Replaces the only remaining use of TARGET_PHYS_ADDR_SPACE_BITS for RISCV with the fixed size of the riscv64 physical address space. Better would be to somehow determine if a 32-bit or 64-bit cpu is running and set accordingly, but I'm not sure how that would be done from the device instance init function. This field is unused anyway. Signed-off-by: Anton Johansson Suggested-by: Richard Henderson --- hw/riscv/riscv-iommu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index b46b337375..c3d48541b7 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2453,9 +2453,15 @@ static void riscv_iommu_instance_init(Object *obj) /* Enable translation debug interface */ s->cap =3D RISCV_IOMMU_CAP_DBG; =20 - /* Report QEMU target physical address space limits */ - s->cap =3D set_field(s->cap, RISCV_IOMMU_CAP_PAS, - TARGET_PHYS_ADDR_SPACE_BITS); + /* + * Report QEMU target physical address space limits. + * + * Currently set to the riscv64 limit of 56 bits (44 bit PPN), + * riscv32 would use 34 bits (22 bit PPN). + * + * This field is currently unused. + */ + s->cap =3D set_field(s->cap, RISCV_IOMMU_CAP_PAS, 56); =20 /* TODO: method to report supported PID bits */ s->pid_bits =3D 8; /* restricted to size of MemTxAttrs.pid */ --=20 2.52.0 From nobody Tue Feb 10 16:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=1G5C5mK8Z7iY/p02AMfuk2WS4d5n7ES5YnjTpLmvtLo=; b=HSp8SPjp34iNIdX 8lkZ0dd7npEaKa9K0Utbtl9wfVLxBBzbvXGylSl5GiYPyoFiEswR3a0yxxPx8i9ZOV76p/KK/5C3W hlOKcuYdqi2N89ZZxZ2xYcCAcm5ZMKYgm+4jDHVarIk1AVcspO7wu6cDFaDJCaoRGv5sNEt67+Miz OU=; Date: Tue, 10 Feb 2026 12:33:19 +0100 Subject: [PATCH v4 8/8] Drop TARGET_PHYS_ADDR_SPACE_BITS MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-phys_addr-v4-8-725a589e83c8@rev.ng> References: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> In-Reply-To: <20260210-phys_addr-v4-0-725a589e83c8@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Anton Johansson , palmer@dabbelt.com, alistair.francis@wdc.com, pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn, deller@gmx.de, Brian Cain Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770723110023154100 The macro is no longer in use and can safely be dropped. Reviewed-by: Richard Henderson Reviewed-by: Brian Cain Signed-off-by: Anton Johansson Suggested-by: Richard Henderson --- include/exec/cpu-defs.h | 3 --- include/exec/poison.h | 2 -- target/alpha/cpu-param.h | 3 --- target/arm/cpu-param.h | 2 -- target/avr/cpu-param.h | 1 - target/hexagon/cpu-param.h | 1 - target/hppa/cpu-param.h | 3 --- target/i386/cpu-param.h | 2 -- target/loongarch/cpu-param.h | 1 - target/m68k/cpu-param.h | 1 - target/microblaze/cpu-param.h | 2 -- target/mips/cpu-param.h | 2 -- target/openrisc/cpu-param.h | 1 - target/ppc/cpu-param.h | 7 ------- target/riscv/cpu-param.h | 2 -- target/rx/cpu-param.h | 1 - target/s390x/cpu-param.h | 1 - target/sh4/cpu-param.h | 1 - target/sparc/cpu-param.h | 2 -- target/tricore/cpu-param.h | 1 - target/xtensa/cpu-param.h | 1 - 21 files changed, 40 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index e01acb7c90..141b5a9929 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -28,9 +28,6 @@ #ifndef TARGET_LONG_BITS # error TARGET_LONG_BITS must be defined in cpu-param.h #endif -#ifndef TARGET_PHYS_ADDR_SPACE_BITS -# error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h -#endif #ifndef TARGET_VIRT_ADDR_SPACE_BITS # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h #endif diff --git a/include/exec/poison.h b/include/exec/poison.h index a779adbb7a..2caf2d92f1 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -43,8 +43,6 @@ #pragma GCC poison TARGET_FMT_ld #pragma GCC poison TARGET_FMT_lu =20 -#pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS - #pragma GCC poison CONFIG_ALPHA_DIS #pragma GCC poison CONFIG_HPPA_DIS #pragma GCC poison CONFIG_I386_DIS diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index a799f42db3..e04bfeee12 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -8,9 +8,6 @@ #ifndef ALPHA_CPU_PARAM_H #define ALPHA_CPU_PARAM_H =20 -/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 44 - #ifdef CONFIG_USER_ONLY /* * Allow user-only to vary page size. Real hardware allows only 8k and 64= k, diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 8b46c7c570..08785125ad 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -9,10 +9,8 @@ #define ARM_CPU_PARAM_H =20 #ifdef TARGET_AARCH64 -# define TARGET_PHYS_ADDR_SPACE_BITS 52 # define TARGET_VIRT_ADDR_SPACE_BITS 52 #else -# define TARGET_PHYS_ADDR_SPACE_BITS 40 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f74bfc2580..066ada1e9c 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -22,7 +22,6 @@ #define AVR_CPU_PARAM_H =20 #define TARGET_PAGE_BITS 10 -#define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 #define TARGET_INSN_START_EXTRA_WORDS 0 diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e74..31da1a239f 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -20,7 +20,6 @@ =20 #define TARGET_PAGE_BITS 16 /* 64K pages */ =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 #define TARGET_INSN_START_EXTRA_WORDS 0 diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 9bf7ac76d0..3a874c29ee 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -9,11 +9,8 @@ #define HPPA_CPU_PARAM_H =20 #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) -# define TARGET_PHYS_ADDR_SPACE_BITS 32 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -/* ??? PA-8000 through 8600 have 40 bits; PA-8700 and 8900 have 44 bits. */ -# define TARGET_PHYS_ADDR_SPACE_BITS 40 # define TARGET_VIRT_ADDR_SPACE_BITS 64 #endif =20 diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index ebb844bcc8..9e4cb74e04 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -9,7 +9,6 @@ #define I386_CPU_PARAM_H =20 #ifdef TARGET_X86_64 -# define TARGET_PHYS_ADDR_SPACE_BITS 52 /* * ??? This is really 48 bits, sign-extended, but the only thing * accessible to userland with bit 48 set is the VSYSCALL, and that @@ -17,7 +16,6 @@ */ # define TARGET_VIRT_ADDR_SPACE_BITS 47 #else -# define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #define TARGET_PAGE_BITS 12 diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 58cc45a377..7779461054 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -8,7 +8,6 @@ #ifndef LOONGARCH_CPU_PARAM_H #define LOONGARCH_CPU_PARAM_H =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 48 #define TARGET_VIRT_ADDR_SPACE_BITS 48 =20 #define TARGET_PAGE_BITS 12 diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 256a2b5f8b..802d8fc674 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -14,7 +14,6 @@ * use the smallest one */ #define TARGET_PAGE_BITS 12 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 #define TARGET_INSN_START_EXTRA_WORDS 1 diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index e0a3794513..90a0cf2435 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -17,10 +17,8 @@ * of address space. */ #ifdef CONFIG_USER_ONLY -#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 #else -#define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 #endif =20 diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 58f450827f..d62110e732 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -8,10 +8,8 @@ #define MIPS_CPU_PARAM_H =20 #ifdef TARGET_ABI_MIPSN64 -#define TARGET_PHYS_ADDR_SPACE_BITS 48 #define TARGET_VIRT_ADDR_SPACE_BITS 48 #else -#define TARGET_PHYS_ADDR_SPACE_BITS 40 # ifdef CONFIG_USER_ONLY # define TARGET_VIRT_ADDR_SPACE_BITS 31 # else diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h index b4f57bbe69..740cf76ddd 100644 --- a/target/openrisc/cpu-param.h +++ b/target/openrisc/cpu-param.h @@ -9,7 +9,6 @@ #define OPENRISC_CPU_PARAM_H =20 #define TARGET_PAGE_BITS 13 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 #define TARGET_INSN_START_EXTRA_WORDS 1 diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index e4ed9080ee..2065915dc5 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -9,12 +9,6 @@ #define PPC_CPU_PARAM_H =20 #ifdef TARGET_PPC64 -/* - * Note that the official physical address space bits is 62-M where M - * is implementation dependent. I've not looked up M for the set of - * cpus we emulate at the system level. - */ -#define TARGET_PHYS_ADDR_SPACE_BITS 62 /* * Note that the PPC environment architecture talks about 80 bit virtual * addresses, with segmentation. Obviously that's not all visible to a @@ -26,7 +20,6 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 64 # endif #else -# define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index cfdc67c258..b96e1ce12e 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -9,10 +9,8 @@ #define RISCV_CPU_PARAM_H =20 #if defined(TARGET_RISCV64) -# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ #elif defined(TARGET_RISCV32) -# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 84934f3bca..4cf6183aa0 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -21,7 +21,6 @@ =20 #define TARGET_PAGE_BITS 12 =20 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 #define TARGET_INSN_START_EXTRA_WORDS 0 diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index abfae3bedf..e46e0757c6 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -9,7 +9,6 @@ #define S390_CPU_PARAM_H =20 #define TARGET_PAGE_BITS 12 -#define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 #define TARGET_INSN_START_EXTRA_WORDS 2 diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index f328715ee8..e2632bb20f 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -9,7 +9,6 @@ #define SH4_CPU_PARAM_H =20 #define TARGET_PAGE_BITS 12 /* 4k */ -#define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY # define TARGET_VIRT_ADDR_SPACE_BITS 31 #else diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 45eea9d6ba..4c92862ea3 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -9,7 +9,6 @@ =20 #ifdef TARGET_SPARC64 # define TARGET_PAGE_BITS 13 /* 8k */ -# define TARGET_PHYS_ADDR_SPACE_BITS 41 # ifdef TARGET_ABI32 # define TARGET_VIRT_ADDR_SPACE_BITS 32 # else @@ -17,7 +16,6 @@ # endif #else # define TARGET_PAGE_BITS 12 /* 4k */ -# define TARGET_PHYS_ADDR_SPACE_BITS 36 # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index eb33a67c41..f260a888c2 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -9,7 +9,6 @@ #define TRICORE_CPU_PARAM_H =20 #define TARGET_PAGE_BITS 14 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 #define TARGET_INSN_START_EXTRA_WORDS 0 diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 7a0c22c900..328176281e 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -9,7 +9,6 @@ #define XTENSA_CPU_PARAM_H =20 #define TARGET_PAGE_BITS 12 -#define TARGET_PHYS_ADDR_SPACE_BITS 32 #ifdef CONFIG_USER_ONLY #define TARGET_VIRT_ADDR_SPACE_BITS 30 #else --=20 2.52.0