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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=z3ddyhImOBiQmW8TUvq1wPXGh+L3b2sHhaH1aUXyHik=; b=CCKu5p6OWrPgbDU 2jIb6bBSV3Mj4IkP9VwbuktdInidSmvL0b3g35/GAC3y0OAF1YkUWICMJBqqinSKoFHUV5RNzX6aK iE5+7JUPXpMI3XrKzqZEvYVndrKYyji3N/CBnxb7D7iTt7a9jHM2uKI5Q1CkPHkbde0DGxhcoINc8 as=; Date: Tue, 10 Feb 2026 17:37:17 +0100 Subject: [PATCH v2 3/4] hppa: Get physical address space bits from CPUHPPADef MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-hppa-c3600-v2-3-9ca09c677012@rev.ng> References: <20260210-hppa-c3600-v2-0-9ca09c677012@rev.ng> In-Reply-To: <20260210-hppa-c3600-v2-0-9ca09c677012@rev.ng> To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , Anton Johansson X-Developer-Signature: v=1; a=ed25519-sha256; t=1770741450; l=5929; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=8biG2AKHU3sl2FkiQV2s2IuKWObejFDMFkCAOQ0Dxb4=; b=z77OShx7n+nEadmnybEoIF19lmR9opcI3oVMj7VvilaHUkblV44sW55N3QoQtf38CI3UUpqQJ hMoTPP9Uqf6A0zYkD+4pUf4RQT28yFdvK8Zc0oqxnlH5UVjKpoF896N X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770741309656158500 Signed-off-by: Anton Johansson --- target/hppa/cpu.h | 11 ++++++++--- hw/hppa/machine.c | 4 ++-- hw/pci-host/astro.c | 2 +- target/hppa/mem_helper.c | 40 ++++++++++++---------------------------- 4 files changed, 23 insertions(+), 34 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 43b4882fb4..487f0f5e9e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -320,6 +320,11 @@ static inline const HPPACPUDef *hppa_def(CPUHPPAState = *env) return HPPA_CPU_GET_CLASS(env_cpu(env))->def; } =20 +static inline uint8_t hppa_phys_addr_bits(CPUHPPAState *env) +{ + return hppa_def(env)->phys_addr_bits; +} + static inline bool hppa_is_pa20(CPUHPPAState *env) { return hppa_def(env)->is_pa20; @@ -352,9 +357,9 @@ static inline vaddr hppa_form_gva(CPUHPPAState *env, ui= nt64_t spc, return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } =20 -hwaddr hppa_abs_to_phys_pa1x(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); +hwaddr hppa_abs_to_phys_pa1x(CPUHPPAState *env, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w0(CPUHPPAState *env, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w1(CPUHPPAState *env, vaddr addr); =20 /* * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 6a0487c362..8246f6bf65 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -181,12 +181,12 @@ static uint64_t linux_kernel_virt_to_phys(void *opaqu= e, uint64_t addr) =20 static uint64_t translate_pa10(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa1x(addr); + return hppa_abs_to_phys_pa1x(cpu_env(first_cpu), addr); } =20 static uint64_t translate_pa20(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa2_w0(addr); + return hppa_abs_to_phys_pa2_w0(cpu_env(first_cpu), addr); } =20 static HPPACPU *cpu[HPPA_MAX_CPUS]; diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 00a904277c..d38f81e553 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -303,7 +303,7 @@ static IOMMUTLBEntry astro_translate_iommu(IOMMUMemoryR= egion *iommu, * language which not-coincidentally matches the PSW.W=3D0 mapping. */ if (addr <=3D UINT32_MAX) { - entry =3D hppa_abs_to_phys_pa2_w0(addr); + entry =3D hppa_abs_to_phys_pa2_w0(cpu_env(first_cpu), addr); } else { entry =3D addr; } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9199d1e06a..4bd806a53f 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,29 +29,12 @@ #include "hw/core/cpu.h" #include "trace.h" =20 -/* - * 64-bit (PA-RISC 2.0) machines are assumed to run PA-8700, and 32-bit - * machines 7300LC. This should give 44 and 32 bits of physical address - * space respectively. - * - * CPU model Physical address space bits - * PA-7000--7300LC 32 - * PA-8000--8600 40 - * PA-8700--8900 44 - * - * FIXME: However, the SeaBIOS firmware that is that tested against - * uses 40-bit physical addresses, despite supposedly running a C3700 - * with a PA-8700 cpu, so use 40-bits for 64-bit. - */ -#define HPPA_PHYS_ADDR_SPACE_BITS_PA20 40 -#define HPPA_PHYS_ADDR_SPACE_BITS_PA1X 32 - -hwaddr hppa_abs_to_phys_pa1x(vaddr addr) +hwaddr hppa_abs_to_phys_pa1x(CPUHPPAState *env, vaddr addr) { - return extract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA1X); + return extract64(addr, 0, hppa_phys_addr_bits(env)); } =20 -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w1(CPUHPPAState *env, vaddr addr) { /* * Figure H-8 "62-bit Absolute Accesses when PSW W-bit is 1" describes @@ -64,11 +47,12 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) * Since the supported physical address space is below 54 bits, the * H-8 algorithm is moot and all that is left is to truncate. */ - QEMU_BUILD_BUG_ON(HPPA_PHYS_ADDR_SPACE_BITS_PA20 > 54); - return sextract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + const uint8_t pa =3D hppa_phys_addr_bits(env); + g_assert(pa <=3D 54); + return sextract64(addr, 0, pa); } =20 -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w0(CPUHPPAState *env, vaddr addr) { /* * See Figure H-10, "Absolute Accesses when PSW W-bit is 0", @@ -89,7 +73,7 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) * is what can be seen on physical machines too. */ addr =3D (uint32_t)addr; - addr |=3D -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 4); + addr |=3D -1ull << (hppa_phys_addr_bits(env) - 4); } return addr; } @@ -233,13 +217,13 @@ int hppa_get_physical_address(CPUHPPAState *env, vadd= r addr, int mmu_idx, if (MMU_IDX_MMU_DISABLED(mmu_idx)) { switch (mmu_idx) { case MMU_ABS_W_IDX: - phys =3D hppa_abs_to_phys_pa2_w1(addr); + phys =3D hppa_abs_to_phys_pa2_w1(env, addr); break; case MMU_ABS_IDX: if (hppa_is_pa20(env)) { - phys =3D hppa_abs_to_phys_pa2_w0(addr); + phys =3D hppa_abs_to_phys_pa2_w0(env, addr); } else { - phys =3D hppa_abs_to_phys_pa1x(addr); + phys =3D hppa_abs_to_phys_pa1x(env, addr); } break; default: @@ -580,7 +564,7 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong = r1, /* Align per the page size. */ ent->pa &=3D TARGET_PAGE_MASK << mask_shift; /* Ignore the bits beyond physical address space. */ - ent->pa =3D sextract64(ent->pa, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + ent->pa =3D sextract64(ent->pa, 0, hppa_phys_addr_bits(env)); =20 ent->t =3D extract64(r2, 61, 1); ent->d =3D extract64(r2, 60, 1); --=20 2.52.0