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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=mGZqekR5KuigYMAGEYYO6SIER9j/yw9F40Czkb0c+0s=; b=nYa7gJipGeVKd3F yoWnuySmF+WQsGU+KZT13h7u+Z1BuJ99siglc/HP2gjMI1ddbG1XyIlCivDsAOfdDlOujOmaGTwAG 4y5/TtZH3YPP8tU57tsuwnZ7+XNN5TLsOJgOtzxMqJpmJ17nLHU74rGTkPW5cvz5/auYkA4jQIIU+ hQ=; Date: Tue, 10 Feb 2026 17:37:16 +0100 Subject: [PATCH v2 2/4] hppa: Introduce HPPACPUDef MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260210-hppa-c3600-v2-2-9ca09c677012@rev.ng> References: <20260210-hppa-c3600-v2-0-9ca09c677012@rev.ng> In-Reply-To: <20260210-hppa-c3600-v2-0-9ca09c677012@rev.ng> To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , Anton Johansson X-Developer-Signature: v=1; a=ed25519-sha256; t=1770741450; l=4109; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=/arWOy2RPq0eIp7ThdLx5jWVszNSSZWqLKaJ1eoyaDE=; b=9EMkFedcTBMGzhuZIx+zEbtXnu4SijuvT3bRH2RW+yQJDJTEzmB1qk7AZum8A7hk/CNIgQZqP i2KBpwolLUBDMM1DbEf5oTy2bXmIruUwl0sEz9m24ZMzAWE4wp+QpNs X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1770741306213154100 In preparation for adding a C3600 machine with 40 bits of physical address space, and moving C3700 to 44 bits, a CPU model configuration struct is added to HPPACPUClass. Two fields are added describing the size of the physical address space, and whether or not the CPU uses the PA-RISC 2.0 architecture. The latter was previously a field in CPUHPPAState. phys_addr_bits is currently set but unused, and will be used in the following commit. Signed-off-by: Anton Johansson --- target/hppa/cpu.h | 24 ++++++++++++++++++++---- target/hppa/cpu.c | 27 +++++++++++++++++++-------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 092e647ccf..43b4882fb4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -270,8 +270,6 @@ typedef struct CPUArchState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - bool is_pa20; - target_ulong kernel_entry; /* Linux kernel was loaded here */ target_ulong cmdline_or_bootorder; target_ulong initrd_base, initrd_end; @@ -290,6 +288,18 @@ struct ArchCPU { QEMUTimer *alarm_timer; }; =20 +/** + * HPPACPUDef: + * @phys_addr_bits: Number of bits in the physical address space. + * @is_pa20: Whether the CPU model follows the PA-RISC 2.0 or 1.1 spec. + * + * Configuration options for a HPPA CPU model. + */ +typedef struct HPPACPUDef { + uint8_t phys_addr_bits; + bool is_pa20; +} HPPACPUDef; + /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. @@ -302,11 +312,17 @@ struct HPPACPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + const HPPACPUDef *def; }; =20 -static inline bool hppa_is_pa20(const CPUHPPAState *env) +static inline const HPPACPUDef *hppa_def(CPUHPPAState *env) +{ + return HPPA_CPU_GET_CLASS(env_cpu(env))->def; +} + +static inline bool hppa_is_pa20(CPUHPPAState *env) { - return env->is_pa20; + return hppa_def(env)->is_pa20; } =20 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c8079016bf..1ba281df20 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,13 +203,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error= **errp) tcg_cflags_set(cs, CF_PCREL); } =20 -static void hppa_cpu_initfn(Object *obj) -{ - CPUHPPAState *env =3D cpu_env(CPU(obj)); - - env->is_pa20 =3D !!object_dynamic_cast(obj, TYPE_HPPA64_CPU_PA_8700); -} - static void hppa_cpu_reset_hold(Object *obj, ResetType type) { HPPACPUClass *scc =3D HPPA_CPU_GET_CLASS(obj); @@ -284,6 +277,16 @@ static const TCGCPUOps hppa_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static void hppa_cpu_class_base_init(ObjectClass *oc, const void *data) +{ + HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); + /* Make sure all CPU models define a HPPACPUDef */ + g_assert(!object_class_is_abstract(oc) && data !=3D NULL); + if (data) { + acc->def =3D data; + } +} + static void hppa_cpu_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -318,18 +321,26 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(HPPACPU), .instance_align =3D __alignof(HPPACPU), - .instance_init =3D hppa_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(HPPACPUClass), .class_init =3D hppa_cpu_class_init, + .class_base_init =3D hppa_cpu_class_base_init, }, { .name =3D TYPE_HPPA_CPU_PA_7300LC, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 32, + .is_pa20 =3D false, + }, }, { .name =3D TYPE_HPPA_CPU_PA_8700, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 40, + .is_pa20 =3D true, + }, }, }; =20 --=20 2.52.0