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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-436296bd1bcsm6372721f8f.12.2026.02.06.10.21.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 06 Feb 2026 10:21:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770402065; x=1771006865; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wzES1qng8rWM3+acoSyUBkVai5xaMJnvu2yQlPPQ03I=; b=uI4jHFXIxSCp20HFnl59aShDpoIewDYJQlCY/S+khBDNFxwXd54TfzPXUr94rAmAPo 9FFzNp/ihrAbPeuibSMEGU72FuzkO4QrL0jEsQNRFJLb6eu2/Y7SMd38fCiwg5DSYssW 0Ki/PIFeAV4RmxTwKruQP5lokUfq8GbCBMf809DsA2bSCbaB7Dy0AmauoujJ+XoRR2gj lhdzrenCHZFVUpVpilmbchVg6rWkhxnika9RdMVkhkyOwDVFPjb18Aod8yPzxkaBs94e P5tWFUXxE06io14tSdtNxNtN9+BqCxbImsGWh0eQbW1QgxEAqmgAOhpgD40h7zvrgumz 9jTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770402065; x=1771006865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wzES1qng8rWM3+acoSyUBkVai5xaMJnvu2yQlPPQ03I=; b=ksC8+XfbB1z5eXbxTTqyBBsGoz42blbS5CrOjShYTQhiXCWeH3maQWGYr5/gR/bMt1 hKeKCi3/nCfN2pP4KRitJz85Bw93UJpdh3xSW/7/U/8Atu8JhbAF5T0kC1Rw63KR2BGE TCtMI9KnSA9iMXL403SlAc8dbN3HWDwJKnbWy61Jb/VpNc2NTmhuo10DSCKSipSGaL2B Z8K/3km1UjXZrbiANALS5kwyDR4JoliAEav+HtbVBC5C6Hg6dzS6/24F4MMwgGYwo/Sc TckqjERzfOJWpicXlaI7tegT7CXtNfUBf5V51+Of7pXvXZ8suMxwx6kAKBi3JgBhw3cg m/0w== X-Gm-Message-State: AOJu0YzlH4hw7BgCfziqYfz4zGe143SlsywBy12qQSbYFw7YhfOJNprS dqd0OxR5diI+gZLiA6tYp/1YaD0IspCv8hNxsuu9qmsrxnVz6450QXXoChSrcL2dOLRGj+Mj8wO saF5fFAU= X-Gm-Gg: AZuq6aKt4rbKpgyuEsLpNgvYaQAYKG3f3/cfSJjpBHnYjT/flitF+RN5JINECm1QggV 1wFlLqwIBvbDMQaWCaMkixRLiGByKqPBughl5l4DcW3R1KeMBFSuidcDFGz1hnq/kWiod15f+gT u45GUaPXNeQLlgO6hZ5qToCyS1CgV9iOPmLFNV8K/gEaLQwl2igd9adw4NFR/yTAK1s34ZkWb5c m4fnbsZHL640zWcFDYvHSHmtIYDQUNHi2Ag8eS07/vuvwkAtBkQFqclMhoQvz1iUdcfclzG3AO1 DohuMNV7hRnxrGiiiIdfpRVVP4Rwme2bsI/M0nWdbRbO0rd4b30to9JRsY0pOAUQpMwhwkWeYMC y1vZ2LSy8p5xoJbhYZ0mAWX3g+3zONAyTJnBRehOkFdumNYUSWE6CSFQNvoss4Y21cK+f0Nbvxc HFEohMGqeq2u3/nGzM0BnjWsjkQfvp4P57WQcHvdMuRf26kX3pX358ikkw0GH8OjTuRz2dXqQ= X-Received: by 2002:a05:6000:2210:b0:435:92c6:d556 with SMTP id ffacd0b85a97d-4362933ec62mr6116926f8f.16.1770402065436; Fri, 06 Feb 2026 10:21:05 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Matthew Rosato , Thomas Huth , qemu-s390x@nongnu.org, Ilya Leoshkevich , Halil Pasic , Richard Henderson , Christian Borntraeger , Eric Farman , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 09/10] target/s390x: Expand tcg_gen_qemu_ld/st_tl() as 64-bit target Date: Fri, 6 Feb 2026 19:19:52 +0100 Message-ID: <20260206181953.18683-10-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260206181953.18683-1-philmd@linaro.org> References: <20260206181953.18683-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770402136714158500 The s390x target is a 64-bit one, so we have these expansions in the "tcg/tcg-op.h" header: . tcg_gen_qemu_ld_tl() -> tcg_gen_qemu_ld_i64() . tcg_gen_qemu_st_tl() -> tcg_gen_qemu_st_i64() Use the expanded form which is more explicit when a target isn't built for different words size. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- target/s390x/tcg/translate.c | 54 ++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 437f5a4aeb7..4dabd49840f 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1259,7 +1259,7 @@ static DisasJumpType op_asi(DisasContext *s, DisasOps= *o) =20 o->in1 =3D tcg_temp_new_i64(); if (non_atomic) { - tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->d= ata); } else { /* Perform the atomic addition in memory. */ tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_ind= ex(s), @@ -1270,7 +1270,7 @@ static DisasJumpType op_asi(DisasContext *s, DisasOps= *o) tcg_gen_add_i64(o->out, o->in1, o->in2); =20 if (non_atomic) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->d= ata); } return DISAS_NEXT; } @@ -1281,7 +1281,7 @@ static DisasJumpType op_asiu64(DisasContext *s, Disas= Ops *o) =20 o->in1 =3D tcg_temp_new_i64(); if (non_atomic) { - tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->d= ata); } else { /* Perform the atomic addition in memory. */ tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_ind= ex(s), @@ -1293,7 +1293,7 @@ static DisasJumpType op_asiu64(DisasContext *s, Disas= Ops *o) tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src); =20 if (non_atomic) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->d= ata); } return DISAS_NEXT; } @@ -1374,7 +1374,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps = *o) o->in1 =3D tcg_temp_new_i64(); =20 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) { - tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->d= ata); } else { /* Perform the atomic operation in memory. */ tcg_gen_atomic_fetch_and_i64(o->in1, o->addr1, o->in2, get_mem_ind= ex(s), @@ -1385,7 +1385,7 @@ static DisasJumpType op_ni(DisasContext *s, DisasOps = *o) tcg_gen_and_i64(o->out, o->in1, o->in2); =20 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->d= ata); } return DISAS_NEXT; } @@ -1917,8 +1917,8 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps= *o) mop =3D ctz32(l + 1) | MO_BE; /* Do not update cc_src yet: loading cc_dst may cause an exception= . */ src =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop); - tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop); + tcg_gen_qemu_ld_i64(src, o->addr1, get_mem_index(s), mop); + tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), mop); gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, src, cc_dst); return DISAS_NEXT; default: @@ -2747,15 +2747,15 @@ static DisasJumpType op_ld16u(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), - MO_BESL | s->insn->data); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), + MO_BESL | s->insn->data); return DISAS_NEXT; } =20 static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s), - MO_BEUL | s->insn->data); + tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), + MO_BEUL | s->insn->data); return DISAS_NEXT; } =20 @@ -3087,7 +3087,7 @@ static DisasJumpType op_lpq(DisasContext *s, DisasOps= *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_lura(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_ld_tl(o->out, o->in2, MMU_REAL_IDX, s->insn->data); + tcg_gen_qemu_ld_i64(o->out, o->in2, MMU_REAL_IDX, s->insn->data); return DISAS_NEXT; } #endif @@ -3506,7 +3506,7 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps = *o) o->in1 =3D tcg_temp_new_i64(); =20 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) { - tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->d= ata); } else { /* Perform the atomic operation in memory. */ tcg_gen_atomic_fetch_or_i64(o->in1, o->addr1, o->in2, get_mem_inde= x(s), @@ -3517,7 +3517,7 @@ static DisasJumpType op_oi(DisasContext *s, DisasOps = *o) tcg_gen_or_i64(o->out, o->in1, o->in2); =20 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->d= ata); } return DISAS_NEXT; } @@ -4334,7 +4334,7 @@ static DisasJumpType op_stnosm(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_stura(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); + tcg_gen_qemu_st_i64(o->in1, o->in2, MMU_REAL_IDX, s->insn->data); =20 if (s->base.tb->flags & FLAG_MASK_PER_STORE_REAL) { update_cc_op(s); @@ -4367,8 +4367,8 @@ static DisasJumpType op_st16(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_st32(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s), - MO_BEUL | s->insn->data); + tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), + MO_BEUL | s->insn->data); return DISAS_NEXT; } =20 @@ -4836,7 +4836,7 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps = *o) o->in1 =3D tcg_temp_new_i64(); =20 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) { - tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), s->insn->d= ata); } else { /* Perform the atomic operation in memory. */ tcg_gen_atomic_fetch_xor_i64(o->in1, o->addr1, o->in2, get_mem_ind= ex(s), @@ -4847,7 +4847,7 @@ static DisasJumpType op_xi(DisasContext *s, DisasOps = *o) tcg_gen_xor_i64(o->out, o->in1, o->in2); =20 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->da= ta); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), s->insn->d= ata); } return DISAS_NEXT; } @@ -5291,7 +5291,7 @@ static void wout_m1_16(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static void wout_m1_16a(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_AL= IGN); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUW | MO_A= LIGN); } #define SPEC_wout_m1_16a 0 #endif @@ -5305,7 +5305,7 @@ static void wout_m1_32(DisasContext *s, DisasOps *o) #ifndef CONFIG_USER_ONLY static void wout_m1_32a(DisasContext *s, DisasOps *o) { - tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_AL= IGN); + tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUL | MO_A= LIGN); } #define SPEC_wout_m1_32a 0 #endif @@ -5816,7 +5816,7 @@ static void in2_m2_32u(DisasContext *s, DisasOps *o) static void in2_m2_32ua(DisasContext *s, DisasOps *o) { in2_a2(s, o); - tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALIG= N); + tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL | MO_ALI= GN); } #define SPEC_in2_m2_32ua 0 #endif @@ -5862,16 +5862,16 @@ static void in2_mri2_16u(DisasContext *s, DisasOps = *o) static void in2_mri2_32s(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), - MO_BESL | MO_ALIGN); + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), + MO_BESL | MO_ALIGN); } #define SPEC_in2_mri2_32s 0 =20 static void in2_mri2_32u(DisasContext *s, DisasOps *o) { o->in2 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s), - MO_BEUL | MO_ALIGN); + tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), + MO_BEUL | MO_ALIGN); } #define SPEC_in2_mri2_32u 0 =20 --=20 2.52.0