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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , Subject: [PATCH v2 06/24] hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub Date: Fri, 6 Feb 2026 14:48:05 +0000 Message-ID: <20260206144823.80655-7-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206144823.80655-1-skolothumtho@nvidia.com> References: <20260206144823.80655-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066E6:EE_|CH2PR12MB9542:EE_ X-MS-Office365-Filtering-Correlation-Id: b6a8c0c9-1ad2-470b-7802-08de658efd0f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated CMDQV ops interface. This patch wires up the Tegra241 CMDQV backend and provides a stub implementation for CMDQV initialization, vIOMMU/vEVENTQ allocation and reset handling. Functional CMDQV support is added in follow-up patches. Signed-off-by: Shameer Kolothum --- hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 1 + hw/arm/tegra241-cmdqv.c | 60 +++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 23 ++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 hw/arm/tegra241-cmdqv.c create mode 100644 hw/arm/tegra241-cmdqv.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c66c452737..3305c6e76e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -626,6 +626,10 @@ config FSL_IMX8MP_EVK depends on TCG select FSL_IMX8MP =20 +config TEGRA241_CMDQV + bool + depends on ARM_SMMUV3_ACCEL + config ARM_SMMUV3_ACCEL bool depends on ARM_SMMUV3 @@ -633,6 +637,7 @@ config ARM_SMMUV3_ACCEL config ARM_SMMUV3 bool select ARM_SMMUV3_ACCEL if IOMMUFD + imply TEGRA241_CMDQV =20 config FSL_IMX6UL bool diff --git a/hw/arm/meson.build b/hw/arm/meson.build index c250487e64..4ec91db50a 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -86,6 +86,7 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP', if_true: fil= es('fsl-imx8mp.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true: files('imx8mp-ev= k.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c= ')) +arm_ss.add(when: 'CONFIG_TEGRA241_CMDQV', if_true: files('tegra241-cmdqv.c= ')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c new file mode 100644 index 0000000000..6f30ca035b --- /dev/null +++ b/hw/arm/tegra241-cmdqv.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2025, NVIDIA CORPORATION + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + +static void tegra241_cmdqv_free_veventq(SMMUv3State *s) +{ +} + +static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static void tegra241_cmdqv_free_viommu(SMMUv3State *s) +{ +} + +static bool +tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static void tegra241_cmdqv_reset(SMMUv3State *s) +{ +} + +static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops_impl =3D { + .init =3D tegra241_cmdqv_init, + .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, + .free_viommu =3D tegra241_cmdqv_free_viommu, + .alloc_veventq =3D tegra241_cmdqv_alloc_veventq, + .free_veventq =3D tegra241_cmdqv_free_veventq, + .reset =3D tegra241_cmdqv_reset, +}; + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void) +{ + return &tegra241_cmdqv_ops_impl; +} diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h new file mode 100644 index 0000000000..81c9deb384 --- /dev/null +++ b/hw/arm/tegra241-cmdqv.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2025, NVIDIA CORPORATION + * NVIDIA Tegra241 CMDQ-Virtualiisation extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_TEGRA241_CMDQV_H +#define HW_TEGRA241_CMDQV_H + +#include CONFIG_DEVICES + +#ifdef CONFIG_TEGRA241_CMDQV +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void); +#else +static inline const SMMUv3AccelCmdqvOps *tegra241_cmdqv_ops(void) +{ + return NULL; +} +#endif +#endif /* HW_TEGRA241_CMDQV_H */ --=20 2.43.0