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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , Subject: [PATCH v2 19/24] hw/arm/tegra241-cmdqv: Add reset handler Date: Fri, 6 Feb 2026 14:48:18 +0000 Message-ID: <20260206144823.80655-20-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206144823.80655-1-skolothumtho@nvidia.com> References: <20260206144823.80655-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE37:EE_|CH3PR12MB8458:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ce1eb1f-e049-4636-c0f1-08de658f1f09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" From: Nicolin Chen Introduce a reset handler for the Tegra241 CMDQV and initialize its register state. CMDQV gets initialized early during guest boot, hence the handler verifies that at least one cold-plugged device is attached to the associated vIOMMU before proceeding. This is required to retrieve host CMDQV info and to validate it against the QEMU implementation support. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 6 ++- hw/arm/tegra241-cmdqv.c | 107 ++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 6 +++ hw/arm/trace-events | 1 + 4 files changed, 119 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index b1a8ab79b5..96224a7632 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -707,7 +707,11 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, QLIST_REMOVE(accel_dev, next); trace_smmuv3_accel_unset_iommu_device(devfn, idev->devid); =20 - if (QLIST_EMPTY(&accel->device_list)) { + /* + * Keep the vIOMMU alive when CMDQV is present, as the vIOMMU to host + * SMMUv3 association cannot be changed via device hot-plug. + */ + if (QLIST_EMPTY(&accel->device_list) && !accel->cmdqv) { smmuv3_accel_free_viommu(accel); } } diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 3dc5315677..678e53d23e 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -582,8 +582,115 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMU= DeviceIOMMUFD *idev, return true; } =20 +static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) +{ + SMMUv3AccelState *s_accel =3D s->s_accel; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV; + struct iommu_hw_info_tegra241_cmdqv cmdqv_info; + SMMUv3AccelDevice *accel_dev; + Error *local_err =3D NULL; + uint64_t caps; + int i; + + if (QLIST_EMPTY(&s_accel->device_list)) { + error_report("tegra241-cmdqv=3Don: requires at least one cold-plug= ged " + "vfio-pci device"); + goto out_err; + } + + accel_dev =3D QLIST_FIRST(&s_accel->device_list); + if (!iommufd_backend_get_device_info(accel_dev->idev->iommufd, + accel_dev->idev->devid, + &data_type, &cmdqv_info, + sizeof(cmdqv_info), &caps, + NULL, &local_err)) { + error_append_hint(&local_err, "Failed to get Host CMDQV device inf= o"); + error_report_err(local_err); + goto out_err; + } + + if (data_type !=3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV) { + error_report("Wrong data type (%d) from Host CMDQV device info", + data_type); + goto out_err; + } + if (cmdqv_info.version !=3D TEGRA241_CMDQV_VERSION) { + error_report("Wrong version (%d) from Host CMDQV device info", + cmdqv_info.version); + goto out_err; + } + if (cmdqv_info.log2vcmdqs !=3D TEGRA241_CMDQV_NUM_CMDQ_LOG2) { + error_report("Wrong num of cmdqs (%d) from Host CMDQV device info", + cmdqv_info.version); + goto out_err; + } + if (cmdqv_info.log2vsids !=3D TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2) { + error_report("Wrong num of SID per VM (%d) from Host CMDQV device = info", + cmdqv_info.version); + goto out_err; + } + + cmdqv->config =3D V_CONFIG_RESET; + cmdqv->param =3D + FIELD_DP32(cmdqv->param, PARAM, CMDQV_VER, TEGRA241_CMDQV_VERSION); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2, + TEGRA241_CMDQV_NUM_CMDQ_LOG2); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VM_= LOG2, + TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2); + trace_tegra241_cmdqv_init_regs(cmdqv->param); + cmdqv->status =3D R_STATUS_CMDQV_ENABLED_MASK; + for (i =3D 0; i < 2; i++) { + cmdqv->vi_err_map[i] =3D 0; + cmdqv->vi_int_mask[i] =3D 0; + cmdqv->cmdq_err_map[i] =3D 0; + } + cmdqv->vintf_config =3D 0; + cmdqv->vintf_status =3D 0; + for (i =3D 0; i < 4; i++) { + cmdqv->vintf_cmdq_err_map[i] =3D 0; + } + for (i =3D 0; i < 128; i++) { + cmdqv->cmdq_alloc_map[i] =3D 0; + cmdqv->vcmdq_cons_indx[i] =3D 0; + cmdqv->vcmdq_prod_indx[i] =3D 0; + cmdqv->vcmdq_config[i] =3D 0; + cmdqv->vcmdq_status[i] =3D 0; + cmdqv->vcmdq_gerror[i] =3D 0; + cmdqv->vcmdq_gerrorn[i] =3D 0; + cmdqv->vcmdq_base[i] =3D 0; + cmdqv->vcmdq_cons_indx_base[i] =3D 0; + } + return; + +out_err: + exit(1); +} + static void tegra241_cmdqv_reset(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + int i; + + if (!cmdqv) { + return; + } + + if (cmdqv->vintf_page0_mapped) { + memory_region_del_subregion(&cmdqv->mmio_cmdqv, + &cmdqv->mmio_vintf_page0); + cmdqv->vintf_page0_mapped =3D false; + } + + for (i =3D 127; i >=3D 0; i--) { + if (cmdqv->vcmdq[i]) { + iommufd_backend_free_id(accel->viommu->iommufd, + cmdqv->vcmdq[i]->hw_queue_id); + g_free(cmdqv->vcmdq[i]); + cmdqv->vcmdq[i] =3D NULL; + } + } + tegra241_cmdqv_init_regs(s, cmdqv); } =20 static const MemoryRegionOps mmio_cmdqv_ops =3D { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index fddb3ac6e9..2aad697170 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -25,6 +25,10 @@ */ #define TEGRA241_CMDQV_IO_LEN 0x50000 =20 +#define TEGRA241_CMDQV_VERSION 0x1 +#define TEGRA241_CMDQV_NUM_CMDQ_LOG2 0x1 +#define TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2 0x4 + typedef struct Tegra241CMDQV { struct iommu_viommu_tegra241_cmdqv cmdqv_data; SMMUv3AccelState *s_accel; @@ -67,6 +71,8 @@ FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) FIELD(CONFIG, CONS_DRAM_EN, 20, 1) =20 +#define V_CONFIG_RESET 0x00020403 + REG32(PARAM, 0x4) FIELD(PARAM, CMDQV_VER, 0, 4) FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 76bda0efef..ef495c040c 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -74,6 +74,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS =20 # tegra241-cmdqv tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" +tegra241_cmdqv_init_regs(uint32_t param) "hw info received. param: 0x%04X" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0