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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , Subject: [PATCH v2 14/24] hw/arm/tegra241-cmdqv: Allocate HW VCMDQs on base register programming Date: Fri, 6 Feb 2026 14:48:13 +0000 Message-ID: <20260206144823.80655-15-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260206144823.80655-1-skolothumtho@nvidia.com> References: <20260206144823.80655-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066E6:EE_|BL3PR12MB6547:EE_ X-MS-Office365-Filtering-Correlation-Id: 2968cc7c-476e-4ed0-b1ac-08de658f0be5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" From: Nicolin Chen Add support for allocating IOMMUFD hardware queues when VCMDQ base registers are programmed by the guest. When a VCMDQ BASE register is written with a valid RAM-backed address, allocate a corresponding IOMMUFD hardware queue for the CMDQV device. Any previously allocated queue for the VCMDQ is freed before reallocation. Writes with invalid addresses (e.g. during reset) are ignored. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 51 ++++++++++++++++++++++++++++++++++++++--- hw/arm/tegra241-cmdqv.h | 1 + 2 files changed, 49 insertions(+), 3 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 71f9a43bce..57f47a4997 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -170,6 +170,45 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwad= dr offset, unsigned size) } } =20 +static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index, + Error **errp) +{ + SMMUv3AccelState *accel =3D cmdqv->s_accel; + uint64_t base_mask =3D (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK | + (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32; + uint64_t addr =3D cmdqv->vcmdq_base[index] & base_mask; + uint64_t log2 =3D cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_= MASK; + uint64_t size =3D 1ULL << (log2 + 4); + IOMMUFDHWqueue *vcmdq =3D cmdqv->vcmdq[index]; + IOMMUFDViommu *viommu =3D accel->viommu; + IOMMUFDHWqueue *hw_queue; + uint32_t hw_queue_id; + + /* Ignore any invalid address. This may come as part of reset etc */ + if (!address_space_is_ram(&address_space_memory, addr)) { + return true; + } + + if (vcmdq) { + iommufd_backend_free_id(viommu->iommufd, vcmdq->hw_queue_id); + cmdqv->vcmdq[index] =3D NULL; + g_free(vcmdq); + } + + if (!iommufd_backend_alloc_hw_queue(viommu->iommufd, viommu->viommu_id, + IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV, + index, addr, size, &hw_queue_id, + errp)) { + return false; + } + hw_queue =3D g_new(IOMMUFDHWqueue, 1); + hw_queue->hw_queue_id =3D hw_queue_id; + hw_queue->viommu =3D viommu; + cmdqv->vcmdq[index] =3D hw_queue; + + return true; +} + /* * Write a VCMDQ register using VCMDQ0_* offsets. * @@ -178,7 +217,7 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwadd= r offset, unsigned size) */ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, - uint64_t value, unsigned size) + uint64_t value, unsigned size, Error **errp) { =20 switch (offset0) { @@ -207,11 +246,13 @@ tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwad= dr offset0, int index, (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) | (value & 0xffffffffULL); } + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); return; case A_VCMDQ0_BASE_H: cmdqv->vcmdq_base[index] =3D (cmdqv->vcmdq_base[index] & 0xffffffffULL) | ((uint64_t)value << 32); + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); return; case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: if (size =3D=3D 8) { @@ -303,7 +344,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, case A_VCMDQ0_CONS_INDX ... A_VCMDQ127_GERRORN: index =3D (offset - 0x10000) / 0x80; tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, - size); + size, &local_err); break; case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ127_CONS_INDX_BASE_DRAM_H: /* Same decoding as read() case: See comments above */ @@ -312,12 +353,16 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr= offset, uint64_t value, case A_VCMDQ0_BASE_L ... A_VCMDQ127_CONS_INDX_BASE_DRAM_H: index =3D (offset - 0x20000) / 0x80; tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, - size); + size, &local_err); break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", __func__, offset); } + + if (local_err) { + error_report_err(local_err); + } } =20 static void tegra241_cmdqv_free_veventq(SMMUv3State *s) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 1bc03c4f97..2f4a8ab35f 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -31,6 +31,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; void *vintf_page0; + IOMMUFDHWqueue *vcmdq[128]; =20 /* Register Cache */ uint32_t config; --=20 2.43.0