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Wed, 04 Feb 2026 22:12:23 -0500 Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 19:12:20 -0800 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 19:12:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770261142; x=1801797142; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kQwPUXHBESbKgby107KY4wXFzIf0n4iCnj9Jt6Vi3kk=; b=AeX1qOgVAxrzCgFGQkGNBiztmqgjEqoawL0p50sBQUFWl65xGqlE9Xxx zcka3GZPgtDm+jwLGrGyi7fOD86RWZP7IBG6+GdB7Vq1KowaAN3fM3cz1 qB4D1peM3FDtskztBvrkVbQ3vJU/11zEzhKELD2d/bQBEv63TwKH9v0Sl nZLM21Wz7gTnK0QsYmRXqOz/wku3vNcOu4dKVIL3Bg8tGcofgELLEC/qS /rrS6EY6rggbKVBnqTHldtTJqzbZKl2D4zPMNiFjaPs6MbVqXzcAM0e0h Qt5d43Jvcg5MyEgIwZ86GAz1WLPrDE4WpvuuroKNJ0XfiJSyTfr6NUzQ+ g==; X-CSE-ConnectionGUID: 5Hc0vUHsQj6dDuSvTZ7L5A== X-CSE-MsgGUID: sNwBFHv7QJyim6ORFDtupQ== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="96910419" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910419" X-CSE-ConnectionGUID: 7Nt1QztHSUu1NgRVH/rHmg== X-CSE-MsgGUID: aQi5WADhSX2k/UlspblVug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209651972" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 01/14] backends/iommufd: Add pasid attach/detach callbacks Date: Wed, 4 Feb 2026 22:11:19 -0500 Message-ID: <20260205031133.74357-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261165848154100 Content-Type: text/plain; charset="utf-8" Add two wrappers host_iommu_device_iommufd_pasid_[at|de]tach_hwpt to wrap the two callbacks. Use assert to ensure the corresponding callbacks exist. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- include/system/iommufd.h | 40 ++++++++++++++++++++++++++++++++++++++++ backends/iommufd.c | 23 +++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 80d72469a9..615be10aed 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -145,10 +145,50 @@ struct HostIOMMUDeviceIOMMUFDClass { * Returns: true on success, false on failure. */ bool (*detach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, Error **errp); + /** + * @attach_hwpt: attach host IOMMU device's pasid to IOMMUFD hardware = page + * table. VFIO and VDPA device can have different implementation. + * + * Mandatory callback. + * + * @idev: host IOMMU device backed by IOMMUFD backend. + * + * @pasid: pasid of host IOMMU device. + * + * @hwpt_id: ID of IOMMUFD hardware page table. + * + * @errp: pass an Error out when attachment fails. + * + * Returns: true on success, false on failure. + */ + bool (*pasid_attach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, uint32_t pasid, + uint32_t hwpt_id, Error **errp); + /** + * @detach_hwpt: detach host IOMMU device's from IOMMUFD hardware page + * table. VFIO and VDPA device can have different implementation. + * + * Mandatory callback. + * + * @idev: host IOMMU device backed by IOMMUFD backend. + * + * @pasid: pasid of host IOMMU device. + * + * @errp: pass an Error out when attachment fails. + * + * Returns: true on success, false on failure. + */ + bool (*pasid_detach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, uint32_t pasid, + Error **errp); }; =20 bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp); bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *idev, Error **errp); +bool host_iommu_device_iommufd_pasid_attach_hwpt(HostIOMMUDeviceIOMMUFD *i= dev, + uint32_t pasid, + uint32_t hwpt_id, + Error **errp); +bool host_iommu_device_iommufd_pasid_detach_hwpt(HostIOMMUDeviceIOMMUFD *i= dev, + uint32_t pasid, Error **e= rrp); #endif diff --git a/backends/iommufd.c b/backends/iommufd.c index 13822df82f..93d3612471 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -539,6 +539,29 @@ static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod,= int cap, Error **errp) } } =20 +bool host_iommu_device_iommufd_pasid_attach_hwpt(HostIOMMUDeviceIOMMUFD *i= dev, + uint32_t pasid, + uint32_t hwpt_id, + Error **errp) +{ + HostIOMMUDeviceIOMMUFDClass *idevc =3D + HOST_IOMMU_DEVICE_IOMMUFD_GET_CLASS(idev); + + g_assert(idevc->pasid_attach_hwpt); + return idevc->pasid_attach_hwpt(idev, pasid, hwpt_id, errp); +} + +bool host_iommu_device_iommufd_pasid_detach_hwpt(HostIOMMUDeviceIOMMUFD *i= dev, + uint32_t pasid, + Error **errp) +{ + HostIOMMUDeviceIOMMUFDClass *idevc =3D + HOST_IOMMU_DEVICE_IOMMUFD_GET_CLASS(idev); + + g_assert(idevc->pasid_detach_hwpt); + return idevc->pasid_detach_hwpt(idev, pasid, errp); +} + static bool hiod_iommufd_get_pasid_info(HostIOMMUDevice *hiod, PasidInfo *pasid_info) { --=20 2.47.3 From nobody Sun Feb 8 22:22:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1770261165; cv=none; d=zohomail.com; s=zohoarc; b=NQObFP611n+lfthw3dcX8xssNBtIuciuqptThP1GQzTMrqWpTV6cdpYG3Tc40nLLvsXLfnChq0BVoL+E6V8GpzqJIpkJkerdOzgtlI3YqIZltF+4X5XG1otRSncnIWsWbPiiANhF79AicCfAAyKPrYGwQFVc82rXooucneT3RiQ= ARC-Message-Signature: i=1; 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bh=nG/Q1hP9oWffW3oHIIiKle9Emle1I2v65QDhot0QVng=; b=ByxnYGPLW0MYfKmJ8hvgL3+HSY/zfJE58/pj3mAvkzy2BAiytgnnaDTq uOQLRzs5HfQdwOK43sbGgilHDe9hJHDvjKzv5F2Z/PXjUV/o5bRf2ADnV xbF3dyfMwWjhKk72l2D6ZVGCurn3Z42KSpd0kKujjsEERJUmUPcx9nTFW 2+wqKp5O2Y3TXnMSFxUER0mIyT6gD5ulCWxDUG/ITq4UpvYzof0IKyttb YL0zmjs0qt+BUoq869T3FpQHIG/zswpqVKQuxCVXn5xejeV0F9oBZEAit fbYMd/xb8NeTzdqzVbNlujOVsqNb9Yq+EPWiksjXm+8GCQI4BKa8uVSK1 Q==; X-CSE-ConnectionGUID: J3zfWqTRQGi/keiAgUGq1g== X-CSE-MsgGUID: q5T0L0c0S064NgKFhRF1aw== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="96910426" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910426" X-CSE-ConnectionGUID: LCZ6MSW3ROyx3YQaXlRQNA== X-CSE-MsgGUID: Gi1ZDFPpTbucWHssQQTHEw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209651982" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 02/14] vfio/iommufd: Implement pasid attach/detach callbacks in TYPE_HOST_IOMMU_DEVICE_IOMMUFD_VFIO Date: Wed, 4 Feb 2026 22:11:20 -0500 Message-ID: <20260205031133.74357-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261167322154100 Content-Type: text/plain; charset="utf-8" 2 new class functions are pasid_[at|de]tach_hwpt(). They are used to attach/detach pasid to/from hwpt. VFIO and VDPA can have different implementions, so implementation will be in sub-class instead of HostIOMMUDeviceIOMMUFD, e.g., in HostIOMMUDeviceIOMMUFDVFIO. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 47 ++++++++++++++++++++++++++++++++++++++++++++ hw/vfio/trace-events | 2 ++ 2 files changed, 49 insertions(+) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 131612eb83..96735f1fc8 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -931,6 +931,51 @@ host_iommu_device_iommufd_vfio_detach_hwpt(HostIOMMUDe= viceIOMMUFD *idev, return iommufd_cdev_detach_ioas_hwpt(vbasedev, errp); } =20 +static bool +host_iommu_device_iommufd_vfio_pasid_attach_hwpt(HostIOMMUDeviceIOMMUFD *i= dev, + uint32_t pasid, + uint32_t hwpt_id, + Error **errp) +{ + VFIODevice *vbasedev =3D HOST_IOMMU_DEVICE(idev)->agent; + struct vfio_device_attach_iommufd_pt attach =3D { + .argsz =3D sizeof(attach), + .flags =3D VFIO_DEVICE_ATTACH_PASID, + .pasid =3D pasid, + .pt_id =3D hwpt_id, + }; + + if (ioctl(vbasedev->fd, VFIO_DEVICE_ATTACH_IOMMUFD_PT, &attach)) { + error_setg_errno(errp, errno, "error attach %s pasid %d to id=3D%d= ", + vbasedev->name, pasid, hwpt_id); + return false; + } + + trace_hiod_iommufd_vfio_pasid_attach_hwpt(vbasedev->name, pasid, hwpt_= id); + return true; +} + +static bool +host_iommu_device_iommufd_vfio_pasid_detach_hwpt(HostIOMMUDeviceIOMMUFD *i= dev, + uint32_t pasid, Error **e= rrp) +{ + VFIODevice *vbasedev =3D HOST_IOMMU_DEVICE(idev)->agent; + struct vfio_device_detach_iommufd_pt detach =3D { + .argsz =3D sizeof(detach), + .pasid =3D pasid, + .flags =3D VFIO_DEVICE_DETACH_PASID, + }; + + if (ioctl(vbasedev->fd, VFIO_DEVICE_DETACH_IOMMUFD_PT, &detach)) { + error_setg_errno(errp, errno, "detach %s pasid %d failed", + vbasedev->name, pasid); + return false; + } + + trace_hiod_iommufd_vfio_pasid_detach_hwpt(vbasedev->name, pasid); + return true; +} + static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *hiod, void *opaque, Error **errp) { @@ -993,6 +1038,8 @@ static void hiod_iommufd_vfio_class_init(ObjectClass *= oc, const void *data) =20 idevc->attach_hwpt =3D host_iommu_device_iommufd_vfio_attach_hwpt; idevc->detach_hwpt =3D host_iommu_device_iommufd_vfio_detach_hwpt; + idevc->pasid_attach_hwpt =3D host_iommu_device_iommufd_vfio_pasid_atta= ch_hwpt; + idevc->pasid_detach_hwpt =3D host_iommu_device_iommufd_vfio_pasid_deta= ch_hwpt; }; =20 static const TypeInfo types[] =3D { diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events index 846e3625c5..2af6f46014 100644 --- a/hw/vfio/trace-events +++ b/hw/vfio/trace-events @@ -188,6 +188,8 @@ iommufd_cdev_fail_attach_existing_container(const char = *msg) " %s" iommufd_cdev_alloc_ioas(int iommufd, int ioas_id) " [iommufd=3D%d] new IOM= MUFD container with ioasid=3D%d" iommufd_cdev_device_info(char *name, int devfd, int num_irqs, int num_regi= ons, int flags) " %s (%d) num_irqs=3D%d num_regions=3D%d flags=3D%d" iommufd_cdev_pci_hot_reset_dep_devices(int domain, int bus, int slot, int = function, int dev_id) "\t%04x:%02x:%02x.%x devid %d" +hiod_iommufd_vfio_pasid_attach_hwpt(const char *name, uint32_t paisd, uint= 32_t hwpt_id) " Successfully attached device %s pasid %d to id=3D%d" +hiod_iommufd_vfio_pasid_detach_hwpt(const char *name, uint32_t paisd) " Su= ccessfully detached device %s pasid %d" =20 # cpr-iommufd.c vfio_cpr_find_device(uint32_t ioas_id, int devid, uint32_t hwpt_id) "ioas_= id %u, devid %d, hwpt_id %u" --=20 2.47.3 From nobody Sun Feb 8 22:22:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 04 Feb 2026 22:12:30 -0500 Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 19:12:27 -0800 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 19:12:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770261149; x=1801797149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7jxsfmsgdwcTUAekZcRZAkQoAGIK1HAINM8QKao+wdY=; b=If77dpqR+BQoxMVjmBOd8rZIqC8/xu7mlpd0/Fnv3DHL5pBD0UY5if52 jn5dVxP2G4sAn7/HTISXWGPR517EwFg/ENCvOFEglQOzOWHMT8JP+7xyV n89Zvmhi8vFHye7APtWSwIYNEmIxOBTKEGa7SW+EUyQmbmtKScsawYZGh isYdYIa5/qI7PdofQrwNYRbP3GMRcKaOjXKCyPhonKtg/+DXMwQ7qE1wu UH/kY2O9Uj6nM8Q2xfp95N6xS4uVqij/0/bCjFSFT4uTAON1FdhuUPe/U ghj7Fm+336HhSPcACJhBmhzYSwjBFYWkvL5RGEyD1EWekLEFYRi7mp+PI w==; X-CSE-ConnectionGUID: JfEvAy++QjOXb3oQzkvdjw== X-CSE-MsgGUID: r0mdoOYETVuKDxxP5LrobQ== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="96910432" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910432" X-CSE-ConnectionGUID: l59SAg+0T2aIKD2OtdS+Mg== X-CSE-MsgGUID: B+Gij9wJQBOG7AP3ETykSQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209651992" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 03/14] vfio/iommufd: Create nesting parent hwpt with IOMMU_HWPT_ALLOC_PASID flag Date: Wed, 4 Feb 2026 22:11:21 -0500 Message-ID: <20260205031133.74357-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261213943154100 Content-Type: text/plain; charset="utf-8" When both host device and vIOMMU have PASID enabled, then guest may setup pasid attached translation. We need to create the nesting parent hwpt with IOMMU_HWPT_ALLOC_PASID flag because according to uAPI, any domain attached to the non-PASID part of the device must also be flagged, otherwise attaching a PASID will blocked. Introduce a vfio_device_get_viommu_flags_pasid_supported() helper to facilitate this implementation. Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-device.h | 1 + hw/vfio/device.c | 11 +++++++++++ hw/vfio/iommufd.c | 8 +++++++- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/include/hw/vfio/vfio-device.h b/include/hw/vfio/vfio-device.h index 35a5ec6d92..983eb0ecce 100644 --- a/include/hw/vfio/vfio-device.h +++ b/include/hw/vfio/vfio-device.h @@ -268,6 +268,7 @@ void vfio_device_prepare(VFIODevice *vbasedev, VFIOCont= ainer *bcontainer, void vfio_device_unprepare(VFIODevice *vbasedev); =20 bool vfio_device_get_viommu_flags_want_nesting(VFIODevice *vbasedev); +bool vfio_device_get_viommu_flags_pasid_supported(VFIODevice *vbasedev); bool vfio_device_get_host_iommu_quirk_bypass_ro(VFIODevice *vbasedev, uint32_t type, void *caps, uint32_t size); diff --git a/hw/vfio/device.c b/hw/vfio/device.c index 973fc35b59..b15ca6ef0a 100644 --- a/hw/vfio/device.c +++ b/hw/vfio/device.c @@ -533,6 +533,17 @@ bool vfio_device_get_viommu_flags_want_nesting(VFIODev= ice *vbasedev) return false; } =20 +bool vfio_device_get_viommu_flags_pasid_supported(VFIODevice *vbasedev) +{ + VFIOPCIDevice *vdev =3D vfio_pci_from_vfio_device(vbasedev); + + if (vdev) { + return !!(pci_device_get_viommu_flags(PCI_DEVICE(vdev)) & + VIOMMU_FLAG_PASID_SUPPORTED); + } + return false; +} + bool vfio_device_get_host_iommu_quirk_bypass_ro(VFIODevice *vbasedev, uint32_t type, void *caps, uint32_t size) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 96735f1fc8..9605bf73b7 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -354,6 +354,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, VendorCaps caps; VFIOIOASHwpt *hwpt; uint32_t hwpt_id; + uint8_t max_pasid_log2; int ret; =20 /* Try to find a domain */ @@ -398,7 +399,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, */ if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devi= d, &type, &caps, sizeof(caps), &hw_c= aps, - NULL, errp)) { + &max_pasid_log2, errp)) { return false; } =20 @@ -420,6 +421,11 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *v= basedev, } } =20 + if (max_pasid_log2 && + vfio_device_get_viommu_flags_pasid_supported(vbasedev)) { + flags |=3D IOMMU_HWPT_ALLOC_PASID; + } + if (cpr_is_incoming()) { hwpt_id =3D vbasedev->cpr.hwpt_id; goto skip_alloc; --=20 2.47.3 From nobody Sun Feb 8 22:22:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1770261185; cv=none; d=zohomail.com; s=zohoarc; b=Plmc6FyvykBmAQqzeCjluv9C3AOKbKaACy4WJpV8gBtDQKlC0cPRMqM72AZqQqOrsyl+UdZcTwIw4TWjmxCWY2M1gdJSRJub6h6S3cw42lTWqwRxqkBirhDO9+3QzBAfICu1gZ/KAWVArwPUZ/kcA6CDegPStNKuNPkt8L4NTd8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770261185; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: 2Z2vBastTl+V5okyu+A2vg== X-CSE-MsgGUID: qFJR4UQZTFKjtY6Stqh7aw== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="96910440" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910440" X-CSE-ConnectionGUID: utthaBveTzKQiIKUjIztVA== X-CSE-MsgGUID: CdWs4sk0T2ebUtcznXbuIA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209651999" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 04/14] intel_iommu: Create the nested hwpt with IOMMU_HWPT_ALLOC_PASID flag Date: Wed, 4 Feb 2026 22:11:22 -0500 Message-ID: <20260205031133.74357-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261190826158500 Content-Type: text/plain; charset="utf-8" When pasid is enabled, any hwpt attached to non-PASID or PASID should be IOMMU_HWPT_ALLOC_PASID flagged, or else attachment fails. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_accel.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 67d54849f2..d61cfec1e6 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -69,11 +69,13 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpa= ce *as) return NULL; } =20 -static bool vtd_create_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, +static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod, VTDPASIDEntry *pe, uint32_t *fs_hwpt_id, Error **errp) { + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); struct iommu_hwpt_vtd_s1 vtd =3D {}; + uint32_t flags =3D vtd_hiod->iommu_state->pasid ? IOMMU_HWPT_ALLOC_PAS= ID : 0; =20 vtd.flags =3D (VTD_SM_PASID_ENTRY_SRE(pe) ? IOMMU_VTD_S1_SRE : 0) | (VTD_SM_PASID_ENTRY_WPE(pe) ? IOMMU_VTD_S1_WPE : 0) | @@ -82,8 +84,8 @@ static bool vtd_create_fs_hwpt(HostIOMMUDeviceIOMMUFD *id= ev, vtd.pgtbl_addr =3D (uint64_t)vtd_pe_get_fspt_base(pe); =20 return iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, idev->hw= pt_id, - 0, IOMMU_HWPT_DATA_VTD_S1, sizeof(vt= d), - &vtd, fs_hwpt_id, errp); + flags, IOMMU_HWPT_DATA_VTD_S1, + sizeof(vtd), &vtd, fs_hwpt_id, errp); } =20 static void vtd_destroy_old_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, @@ -116,7 +118,7 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDevic= e *vtd_hiod, } =20 if (vtd_pe_pgtt_is_fst(pe)) { - if (!vtd_create_fs_hwpt(idev, pe, &hwpt_id, errp)) { + if (!vtd_create_fs_hwpt(vtd_hiod, pe, &hwpt_id, errp)) { return false; } } --=20 2.47.3 From nobody Sun Feb 8 22:22:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="209652028" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 05/14] intel_iommu: Change pasid property from bool to uint8 Date: Wed, 4 Feb 2026 22:11:23 -0500 Message-ID: <20260205031133.74357-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261217647158500 Content-Type: text/plain; charset="utf-8" 'x-pasid-mode' is a bool property, we need an extra 'pss' property to represent PASID size supported. Because there is no any device in QEMU supporting pasid capability yet, no guest could use the pasid feature until now, 'x-pasid-mode' takes no effect. So instead of an extra 'pss' property we can use a single 'pasid' property of uint8 type to represent if pasid is supported and the PASID bits size. A value of N > 0 means pasid is supported and N - 1 is the value in PSS field in ECAP register. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 - include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 4 ++-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index a2ca79f925..71cb3b662e 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -194,7 +194,6 @@ #define VTD_ECAP_PRS (1ULL << 29) #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) -#define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid= */ #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) #define VTD_ECAP_SSTS (1ULL << 46) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 6c61fd39c7..5e5779e460 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -315,7 +315,7 @@ struct IntelIOMMUState { bool buggy_eim; /* Force buggy EIM unless eim=3Doff */ uint8_t aw_bits; /* Host/IOVA address width (in bits) */ bool dma_drain; /* Whether DMA r/w draining enabled */ - bool pasid; /* Whether to support PASID */ + uint8_t pasid; /* PASID supported in bits, 0 if not */ bool fs1gp; /* First Stage 1-GByte Page Support */ =20 /* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e8a6f50a5a..916eb0af5a 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4151,7 +4151,7 @@ static const Property vtd_properties[] =3D { DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FA= LSE), DEFINE_PROP_BOOL("x-flts", IntelIOMMUState, fsts, FALSE), DEFINE_PROP_BOOL("snoop-control", IntelIOMMUState, snoop_control, fals= e), - DEFINE_PROP_BOOL("x-pasid-mode", IntelIOMMUState, pasid, false), + DEFINE_PROP_UINT8("pasid", IntelIOMMUState, pasid, 0), DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false), DEFINE_PROP_BOOL("fs1gp", IntelIOMMUState, fs1gp, true), @@ -4981,7 +4981,7 @@ static void vtd_cap_init(IntelIOMMUState *s) } =20 if (s->pasid) { - s->ecap |=3D VTD_ECAP_PASID | VTD_ECAP_PSS; + s->ecap =3D VTD_ECAP_PASID | deposit64(s->ecap, 35, 5, s->pasid - = 1); } } =20 --=20 2.47.3 From nobody Sun Feb 8 22:22:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1770261196; cv=none; d=zohomail.com; s=zohoarc; b=b5RL0CKZYdEvqtN8uI1OdfQS0MF3k03KQD/bsBdqfaMTonN7a+3gPPCPa5KT9LKiJkdCKwWjN8yhGjNu7ofySahflJAOse3Qc+tbpEdro6hhMq4p8rK1YoWzYr5eYeIRK1BUfyh4FlY8UMaRpTakeGvsxSDDZwh/Tl3zhUMkjvU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770261196; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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X-CSE-ConnectionGUID: zV+xFbNlT4a0R1QIw+NlBw== X-CSE-MsgGUID: fIdjQnj4SzKQaCNbwy1v/A== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="96910461" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910461" X-CSE-ConnectionGUID: qGI3Nh2xT1Ol2XzQbrVNuw== X-CSE-MsgGUID: HjJI6Zc4RliVtPRvXedNPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209652032" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 06/14] intel_iommu: Export some functions Date: Wed, 4 Feb 2026 22:11:24 -0500 Message-ID: <20260205031133.74357-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261199374158500 Content-Type: text/plain; charset="utf-8" Export some functions for accel code usages. Inline functions and MACROs are moved to internal header files. Then accel code in following patches could access them. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 31 +++++++++++++++++++++++++ hw/i386/intel_iommu.c | 42 ++++++++-------------------------- 2 files changed, 40 insertions(+), 33 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 71cb3b662e..6753a20ca4 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -615,6 +615,12 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL =20 +/* context entry operations */ +#define VTD_CE_GET_PASID_DIR_TABLE(ce) \ + ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) +#define VTD_CE_GET_PRE(ce) \ + ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE) + typedef struct VTDPASIDCacheInfo { uint8_t type; uint16_t did; @@ -733,4 +739,29 @@ static inline bool vtd_pe_pgtt_is_fst(VTDPASIDEntry *p= e) { return (VTD_SM_PASID_ENTRY_PGTT(pe) =3D=3D VTD_SM_PASID_ENTRY_FST); } + +static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) +{ + return pdire->val & 1; +} + +static inline bool vtd_pe_present(VTDPASIDEntry *pe) +{ + return pe->val[0] & VTD_PASID_ENTRY_P; +} + +static inline int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry= *p2) +{ + return memcmp(p1, p2, sizeof(*p1)); +} + +int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasi= d, + VTDPASIDDirEntry *pdire); +int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, + dma_addr_t addr, VTDPASIDEntry *pe); +int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, + uint8_t devfn, VTDContextEntry *ce); +int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, + VTDPASIDEntry *pe, uint32_t pasid); +VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid); #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 916eb0af5a..ab52a688c5 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -42,12 +42,6 @@ #include "migration/vmstate.h" #include "trace.h" =20 -/* context entry operations */ -#define VTD_CE_GET_PASID_DIR_TABLE(ce) \ - ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK) -#define VTD_CE_GET_PRE(ce) \ - ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE) - /* * Paging mode for first-stage translation (VTD spec Figure 9-6) * 00: 4-level paging, 01: 5-level paging @@ -831,18 +825,12 @@ static inline bool vtd_pe_type_check(IntelIOMMUState = *s, VTDPASIDEntry *pe) } } =20 -static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) -{ - return pdire->val & 1; -} - /** * Caller of this function should check present bit if wants * to use pdir entry for further usage except for fpd bit check. */ -static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, - uint32_t pasid, - VTDPASIDDirEntry *pdire) +int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasi= d, + VTDPASIDDirEntry *pdire) { uint32_t index; dma_addr_t addr, entry_size; @@ -860,15 +848,8 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pa= sid_dir_base, return 0; } =20 -static inline bool vtd_pe_present(VTDPASIDEntry *pe) -{ - return pe->val[0] & VTD_PASID_ENTRY_P; -} - -static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, - uint32_t pasid, - dma_addr_t addr, - VTDPASIDEntry *pe) +int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, + dma_addr_t addr, VTDPASIDEntry *pe) { uint8_t pgtt; uint32_t index; @@ -954,8 +935,8 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, return 0; } =20 -static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, - VTDPASIDEntry *pe, uint32_t pasid) +int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, + VTDPASIDEntry *pe, uint32_t pasid) { dma_addr_t pasid_dir_base; =20 @@ -1531,8 +1512,8 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, V= TDContextEntry *ce) } =20 /* Map a device to its corresponding domain (context-entry) */ -static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, - uint8_t devfn, VTDContextEntry *ce) +int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, + uint8_t devfn, VTDContextEntry *ce) { VTDRootEntry re; int ret_fr; @@ -1894,7 +1875,7 @@ static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(I= ntelIOMMUState *s, vtd_find_as_by_sid_and_pasid, &key); } =20 -static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) +VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) { return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID); } @@ -3112,11 +3093,6 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddre= ssSpace *vtd_as, return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid); } =20 -static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) -{ - return memcmp(p1, p2, sizeof(*p1)); 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X-CSE-ConnectionGUID: gxfA/IM6TJWuaSGy1jCDuA== X-CSE-MsgGUID: Kyi68hYlQpePEKIE94UlFA== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="96910478" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910478" X-CSE-ConnectionGUID: FMDwv16cSkyf7QwCh8hWjQ== X-CSE-MsgGUID: KTTnhylwR9GbPzJISqUMkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209652047" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 07/14] intel_iommu: Handle PASID entry addition for pc_inv_dsc request Date: Wed, 4 Feb 2026 22:11:25 -0500 Message-ID: <20260205031133.74357-8-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261258822154100 Content-Type: text/plain; charset="utf-8" Structure VTDAddressSpace includes some elements suitable for emulated device and passthrough device without PASID, e.g., address space, different memory regions, etc, it is also protected by vtd iommu lock, all these are useless and become a burden for passthrough device with PASID. When there are lots of PASIDs used in one device, the AS and MRs are all registered to memory core and impact the whole system performance. So instead of using VTDAddressSpace to cache pasid entry for each pasid of a passthrough device, we define a light weight structure VTDACCELPASIDCacheEntry with only necessary elements for each pasid. We will use this struct as a parameter to conduct binding/unbinding to nested hwpt and to record the current binded nested hwpt. It's also designed to support PASID_0. When guest creates new PASID entries, QEMU will capture the pc_inv_dsc (pasid cache invalidation) request, walk through each pasid in each passthrough device for valid pasid entries, create a new VTDACCELPASIDCacheEntry if not existing yet. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_accel.h | 13 +++ hw/i386/intel_iommu_internal.h | 8 ++ hw/i386/intel_iommu.c | 3 + hw/i386/intel_iommu_accel.c | 170 +++++++++++++++++++++++++++++++++ 4 files changed, 194 insertions(+) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index e5f0b077b4..a77fd06fe0 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -12,6 +12,13 @@ #define HW_I386_INTEL_IOMMU_ACCEL_H #include CONFIG_DEVICES =20 +typedef struct VTDACCELPASIDCacheEntry { + VTDHostIOMMUDevice *vtd_hiod; + VTDPASIDEntry pe; + uint32_t pasid; + QLIST_ENTRY(VTDACCELPASIDCacheEntry) next; +} VTDACCELPASIDCacheEntry; + #ifdef CONFIG_VTD_ACCEL bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); @@ -20,6 +27,7 @@ bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, E= rror **errp); void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_= id, uint32_t pasid, hwaddr addr, uint64_t npages, bool ih); +void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, @@ -49,6 +57,11 @@ static inline void vtd_flush_host_piotlb_all_locked(Inte= lIOMMUState *s, { } =20 +static inline void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info) +{ +} + static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { } diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 6753a20ca4..fe81c47819 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -611,6 +611,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 #define PASID_0 0 +#define VTD_SM_CONTEXT_ENTRY_PDTS(x) extract64((x)->val[0], 9, 3) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL @@ -641,6 +642,7 @@ typedef struct VTDPIOTLBInvInfo { #define VTD_PASID_DIR_BITS_MASK (0x3fffULL) #define VTD_PASID_DIR_INDEX(pasid) (((pasid) >> 6) & VTD_PASID_DIR_BITS= _MASK) #define VTD_PASID_DIR_FPD (1ULL << 1) /* Fault Processing Disa= ble */ +#define VTD_PASID_TABLE_ENTRY_NUM (1ULL << 6) #define VTD_PASID_TABLE_BITS_MASK (0x3fULL) #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK) #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disa= ble */ @@ -698,6 +700,7 @@ typedef struct VTDHostIOMMUDevice { PCIBus *bus; uint8_t devfn; HostIOMMUDevice *hiod; + QLIST_HEAD(, VTDACCELPASIDCacheEntry) pasid_cache_list; } VTDHostIOMMUDevice; =20 /* @@ -755,6 +758,11 @@ static inline int vtd_pasid_entry_compare(VTDPASIDEntr= y *p1, VTDPASIDEntry *p2) return memcmp(p1, p2, sizeof(*p1)); } =20 +static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTDContextEntry *ce) +{ + return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce) + 7); +} + int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasi= d, VTDPASIDDirEntry *pdire); int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid, diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index ab52a688c5..50569460ab 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3181,6 +3181,8 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, = VTDPASIDCacheInfo *pc_info) g_hash_table_foreach(s->vtd_address_spaces, vtd_pasid_cache_sync_locke= d, pc_info); vtd_iommu_unlock(s); + + vtd_pasid_cache_sync_accel(s, pc_info); } =20 static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s) @@ -4691,6 +4693,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->devfn =3D (uint8_t)devfn; vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; + QLIST_INIT(&vtd_hiod->pasid_cache_list); =20 if (!vtd_check_hiod(s, vtd_hiod, errp)) { g_free(vtd_hiod); diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index d61cfec1e6..57286f443e 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -253,6 +253,176 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState= *s, uint16_t domain_id, vtd_flush_host_piotlb_locked, &piotlb_info); } =20 +static void vtd_find_add_pc(VTDHostIOMMUDevice *vtd_hiod, uint32_t pasid, + VTDPASIDEntry *pe) +{ + VTDACCELPASIDCacheEntry *vtd_pce; + + QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { + if (vtd_pce->pasid =3D=3D pasid) { + if (vtd_pasid_entry_compare(pe, &vtd_pce->pe)) { + vtd_pce->pe =3D *pe; + } + return; + } + } + + vtd_pce =3D g_malloc0(sizeof(VTDACCELPASIDCacheEntry)); + vtd_pce->vtd_hiod =3D vtd_hiod; + vtd_pce->pasid =3D pasid; + vtd_pce->pe =3D *pe; + QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); +} + +/* + * This function walks over PASID range within [start, end) in a single + * PASID table for entries matching @info type/did, then create + * VTDACCELPASIDCacheEntry if not exist yet. + */ +static void vtd_sm_pasid_table_walk_one(VTDHostIOMMUDevice *vtd_hiod, + dma_addr_t pt_base, + int start, + int end, + VTDPASIDCacheInfo *info) +{ + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + VTDPASIDEntry pe; + int pasid; + + for (pasid =3D start; pasid < end; pasid++) { + if (vtd_get_pe_in_pasid_leaf_table(s, pasid, pt_base, &pe) || + !vtd_pe_present(&pe)) { + continue; + } + + if ((info->type =3D=3D VTD_INV_DESC_PASIDC_G_DSI || + info->type =3D=3D VTD_INV_DESC_PASIDC_G_PASID_SI) && + (info->did !=3D VTD_SM_PASID_ENTRY_DID(&pe))) { + /* + * VTD_PASID_CACHE_DOMSI and VTD_PASID_CACHE_PASIDSI + * requires domain id check. If domain id check fail, + * go to next pasid. + */ + continue; + } + + vtd_find_add_pc(vtd_hiod, pasid, &pe); + } +} + +/* + * In VT-d scalable mode translation, PASID dir + PASID table is used. + * This function aims at looping over a range of PASIDs in the given + * two level table to identify the pasid config in guest. + */ +static void vtd_sm_pasid_table_walk(VTDHostIOMMUDevice *vtd_hiod, + dma_addr_t pdt_base, + int start, int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDDirEntry pdire; + int pasid =3D start; + int pasid_next; + dma_addr_t pt_base; + + while (pasid < end) { + pasid_next =3D (pasid + VTD_PASID_TABLE_ENTRY_NUM) & + ~(VTD_PASID_TABLE_ENTRY_NUM - 1); + pasid_next =3D pasid_next < end ? pasid_next : end; + + if (!vtd_get_pdire_from_pdir_table(pdt_base, pasid, &pdire) + && vtd_pdire_present(&pdire)) { + pt_base =3D pdire.val & VTD_PASID_TABLE_BASE_ADDR_MASK; + vtd_sm_pasid_table_walk_one(vtd_hiod, pt_base, pasid, pasid_ne= xt, + info); + } + pasid =3D pasid_next; + } +} + +static void vtd_replay_pasid_bind_for_dev(VTDHostIOMMUDevice *vtd_hiod, + int start, int end, + VTDPASIDCacheInfo *pc_info) +{ + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + VTDContextEntry ce; + int dev_max_pasid =3D 1 << vtd_hiod->hiod->caps.max_pasid_log2; + + if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_hiod->bus), + vtd_hiod->devfn, &ce)) { + VTDPASIDCacheInfo walk_info =3D *pc_info; + uint32_t ce_max_pasid =3D vtd_sm_ce_get_pdt_entry_num(&ce) * + VTD_PASID_TABLE_ENTRY_NUM; + + end =3D MIN(end, MIN(dev_max_pasid, ce_max_pasid)); + + vtd_sm_pasid_table_walk(vtd_hiod, VTD_CE_GET_PASID_DIR_TABLE(&ce), + start, end, &walk_info); + } +} + +/* + * This function replays the guest pasid bindings by walking the two level + * guest PASID table. For each valid pasid entry, it creates an entry + * VTDACCELPASIDCacheEntry dynamically if not exist yet. This entry holds + * info specific to a pasid + */ +void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info) +{ + int start =3D PASID_0, end =3D 1 << s->pasid; + VTDHostIOMMUDevice *vtd_hiod; + GHashTableIter as_it; + + if (!s->fsts) { + return; + } + + /* + * VTDPASIDCacheInfo honors PCI pasid but VTDACCELPASIDCacheEntry hono= rs + * iommu pasid + */ + if (pc_info->pasid =3D=3D PCI_NO_PASID) { + pc_info->pasid =3D 0; + } + + switch (pc_info->type) { + case VTD_INV_DESC_PASIDC_G_PASID_SI: + start =3D pc_info->pasid; + end =3D pc_info->pasid + 1; + /* fall through */ + case VTD_INV_DESC_PASIDC_G_DSI: + /* + * loop all assigned devices, do domain id check in + * vtd_sm_pasid_table_walk_one() after get pasid entry. + */ + break; + case VTD_INV_DESC_PASIDC_G_GLOBAL: + /* loop all assigned devices */ + break; + default: + g_assert_not_reached(); + } + + /* + * In this replay, one only needs to care about the devices which are + * backed by host IOMMU. Those devices have a corresponding vtd_hiod + * in s->vtd_host_iommu_dev. For devices not backed by host IOMMU, it + * is not necessary to replay the bindings since their cache should be + * created in the future DMA address translation. + * + * VTD translation callback never accesses vtd_hiod and its correspond= ing + * cached pasid entry, so no iommu lock needed here. + */ + g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) { + if (!object_dynamic_cast(OBJECT(vtd_hiod->hiod), + TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { + continue; + } + vtd_replay_pasid_bind_for_dev(vtd_hiod, start, end, pc_info); + } +} + static uint64_t vtd_get_host_iommu_quirks(uint32_t type, void *caps, uint32_t size) { --=20 2.47.3 From nobody Sun Feb 8 22:22:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="209652058" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 08/14] intel_iommu: Handle PASID entry removal for pc_inv_dsc request Date: Wed, 4 Feb 2026 22:11:26 -0500 Message-ID: <20260205031133.74357-9-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261244452154100 Content-Type: text/plain; charset="utf-8" When guest deletes PASID entries, QEMU will capture the pasid cache invalidation request, walk through pasid_cache_list in each passthrough device to find stale VTDACCELPASIDCacheEntry and delete them. This happen before the PASID entry addition, because a new added entry should never be removed. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_accel.c | 70 +++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 57286f443e..2c17365a27 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -16,6 +16,28 @@ #include "hw/pci/pci_bus.h" #include "trace.h" =20 +static inline int vtd_hiod_get_pe_from_pasid(VTDACCELPASIDCacheEntry *vtd_= pce, + VTDPASIDEntry *pe) +{ + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + uint32_t pasid =3D vtd_pce->pasid; + VTDContextEntry ce; + int ret; + + if (!s->dmar_enabled || !s->root_scalable) { + return -VTD_FR_RTADDR_INV_TTM; + } + + ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_hiod->bus), + vtd_hiod->devfn, &ce); + if (ret) { + return ret; + } + + return vtd_ce_get_pasid_entry(s, &ce, pe, pasid); +} + bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp) { @@ -253,6 +275,52 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState = *s, uint16_t domain_id, vtd_flush_host_piotlb_locked, &piotlb_info); } =20 +static void vtd_pasid_cache_invalidate_one(VTDACCELPASIDCacheEntry *vtd_pc= e, + VTDPASIDCacheInfo *pc_info) +{ + VTDPASIDEntry pe; + uint16_t did; + + /* + * VTD_INV_DESC_PASIDC_G_DSI and VTD_INV_DESC_PASIDC_G_PASID_SI require + * DID check. If DID doesn't match the value in cache or memory, then + * it's not a pasid entry we want to invalidate. + */ + switch (pc_info->type) { + case VTD_INV_DESC_PASIDC_G_PASID_SI: + if (pc_info->pasid !=3D vtd_pce->pasid) { + return; + } + /* Fall through */ + case VTD_INV_DESC_PASIDC_G_DSI: + did =3D VTD_SM_PASID_ENTRY_DID(&vtd_pce->pe); + if (pc_info->did !=3D did) { + return; + } + } + + if (vtd_hiod_get_pe_from_pasid(vtd_pce, &pe)) { + /* + * No valid pasid entry in guest memory. e.g. pasid entry was modi= fied + * to be either all-zero or non-present. Either case means existing + * pasid cache should be invalidated. + */ + QLIST_REMOVE(vtd_pce, next); + g_free(vtd_pce); + } +} + +/* Delete invalid pasid cache entry from pasid_cache_list */ +static void vtd_pasid_cache_invalidate(VTDHostIOMMUDevice *vtd_hiod, + VTDPASIDCacheInfo *pc_info) +{ + VTDACCELPASIDCacheEntry *vtd_pce, *next; + + QLIST_FOREACH_SAFE(vtd_pce, &vtd_hiod->pasid_cache_list, next, next) { + vtd_pasid_cache_invalidate_one(vtd_pce, pc_info); + } +} + static void vtd_find_add_pc(VTDHostIOMMUDevice *vtd_hiod, uint32_t pasid, VTDPASIDEntry *pe) { @@ -419,6 +487,8 @@ void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTD= PASIDCacheInfo *pc_info) TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { continue; } + + vtd_pasid_cache_invalidate(vtd_hiod, pc_info); vtd_replay_pasid_bind_for_dev(vtd_hiod, start, end, pc_info); } } --=20 2.47.3 From nobody Sun Feb 8 22:22:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="209652065" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 09/14] intel_iommu: Handle PASID entry removal for system reset Date: Wed, 4 Feb 2026 22:11:27 -0500 Message-ID: <20260205031133.74357-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261209834154100 Content-Type: text/plain; charset="utf-8" When system level reset, DMA translation is turned off, all PASID entries become stale and should be deleted. vtd_hiod list is never accessed without BQL, so no need to guard with iommu lock. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_accel.h | 5 +++++ hw/i386/intel_iommu.c | 2 ++ hw/i386/intel_iommu_accel.c | 13 +++++++++++++ 3 files changed, 20 insertions(+) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index a77fd06fe0..914c690c26 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -28,6 +28,7 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s,= uint16_t domain_id, uint32_t pasid, hwaddr addr, uint64_t npages, bool ih); void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); +void vtd_pasid_cache_reset_accel(IntelIOMMUState *s); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, @@ -62,6 +63,10 @@ static inline void vtd_pasid_cache_sync_accel(IntelIOMMU= State *s, { } =20 +static inline void vtd_pasid_cache_reset_accel(IntelIOMMUState *s) +{ +} + static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops) { } diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 50569460ab..1d0f0bf68b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -391,6 +391,8 @@ static void vtd_reset_caches(IntelIOMMUState *s) vtd_reset_context_cache_locked(s); vtd_pasid_cache_reset_locked(s); vtd_iommu_unlock(s); + + vtd_pasid_cache_reset_accel(s); } =20 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 2c17365a27..1d7dae87ec 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -493,6 +493,19 @@ void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VT= DPASIDCacheInfo *pc_info) } } =20 +/* Fake a gloal pasid cache invalidation to remove all pasid cache entries= */ +void vtd_pasid_cache_reset_accel(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info =3D { .type =3D VTD_INV_DESC_PASIDC_G_GLOBAL= }; + VTDHostIOMMUDevice *vtd_hiod; + GHashTableIter as_it; + + g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) { + vtd_pasid_cache_invalidate(vtd_hiod, &pc_info); + } +} + static uint64_t vtd_get_host_iommu_quirks(uint32_t type, void *caps, uint32_t size) { --=20 2.47.3 From nobody Sun Feb 8 22:22:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="96910508" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910508" X-CSE-ConnectionGUID: ZsbCcKJgStK/3NhE93QDvQ== X-CSE-MsgGUID: CqxfQRKSQtORQ8Kt22l3Fg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209652069" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 10/14] intel_iommu_accel: Support pasid binding/unbinding and PIOTLB flushing Date: Wed, 4 Feb 2026 22:11:28 -0500 Message-ID: <20260205031133.74357-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261217757158500 Content-Type: text/plain; charset="utf-8" We just switched to use VTDACCELPASIDCacheEntry to cache pasid entry of a PASID, also need to switch the binding/unbinding and PIOTLB flushing functions to use the same structure. The backend implementations of binding/unbinding to nonzero PASID and PASID_0 are different, so we need to check the pasid to call different callbacks. After the switching, we could remove accel related code from vtd_pasid_cache_[reset/sync]_locked() to make intel_iommu.c cleaner. The VTDAddressSpace of PASID_0 is still useful as VTD supports a legacy mode which needs shadow page table instead of nested page table. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_accel.h | 2 +- include/hw/i386/intel_iommu.h | 2 - hw/i386/intel_iommu.c | 17 +---- hw/i386/intel_iommu_accel.c | 128 ++++++++++++++++++---------------- 4 files changed, 70 insertions(+), 79 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 914c690c26..1ae46d9250 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -16,6 +16,7 @@ typedef struct VTDACCELPASIDCacheEntry { VTDHostIOMMUDevice *vtd_hiod; VTDPASIDEntry pe; uint32_t pasid; + uint32_t fs_hwpt_id; QLIST_ENTRY(VTDACCELPASIDCacheEntry) next; } VTDACCELPASIDCacheEntry; =20 @@ -23,7 +24,6 @@ typedef struct VTDACCELPASIDCacheEntry { bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); -bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp); void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_= id, uint32_t pasid, hwaddr addr, uint64_t npages, bool ih); diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 5e5779e460..dfcd8ee652 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -154,8 +154,6 @@ struct VTDAddressSpace { * with the guest IOMMU pgtables for a device. */ IOVATree *iova_tree; - - uint32_t fs_hwpt_id; }; =20 struct VTDIOTLBEntry { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1d0f0bf68b..1626c8f96b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -86,8 +86,6 @@ static void vtd_pasid_cache_reset_locked(IntelIOMMUState = *s) VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; if (pc_entry->valid) { pc_entry->valid =3D false; - /* It's fatal to get failure during reset */ - vtd_propagate_guest_pasid(vtd_as, &error_fatal); } } } @@ -3105,8 +3103,6 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, VTDPASIDEntry pe; IOMMUNotifier *n; uint16_t did; - const char *err_prefix =3D "Attaching to HWPT failed: "; - Error *local_err =3D NULL; =20 if (vtd_dev_get_pe_from_pasid(vtd_as, &pe)) { if (!pc_entry->valid) { @@ -3127,9 +3123,6 @@ static void vtd_pasid_cache_sync_locked(gpointer key,= gpointer value, vtd_address_space_unmap(vtd_as, n); } vtd_switch_address_space(vtd_as); - - err_prefix =3D "Detaching from HWPT failed: "; - goto do_bind_unbind; } =20 /* @@ -3157,20 +3150,12 @@ static void vtd_pasid_cache_sync_locked(gpointer ke= y, gpointer value, if (!pc_entry->valid) { pc_entry->pasid_entry =3D pe; pc_entry->valid =3D true; - } else if (vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { - err_prefix =3D "Replacing HWPT attachment failed: "; - } else { + } else if (!vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { return; } =20 vtd_switch_address_space(vtd_as); vtd_address_space_sync(vtd_as); - -do_bind_unbind: - /* TODO: Fault event injection into guest, report error to QEMU for no= w */ - if (!vtd_propagate_guest_pasid(vtd_as, &local_err)) { - error_reportf_err(local_err, "%s", err_prefix); - } } =20 static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 1d7dae87ec..5abc462a45 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -111,21 +111,22 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vt= d_hiod, } =20 static void vtd_destroy_old_fs_hwpt(HostIOMMUDeviceIOMMUFD *idev, - VTDAddressSpace *vtd_as) + VTDACCELPASIDCacheEntry *vtd_pce) { - if (!vtd_as->fs_hwpt_id) { + if (!vtd_pce->fs_hwpt_id) { return; } - iommufd_backend_free_id(idev->iommufd, vtd_as->fs_hwpt_id); - vtd_as->fs_hwpt_id =3D 0; + iommufd_backend_free_id(idev->iommufd, vtd_pce->fs_hwpt_id); + vtd_pce->fs_hwpt_id =3D 0; } =20 -static bool vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, - VTDAddressSpace *vtd_as, Error **err= p) +static bool vtd_device_attach_iommufd(VTDACCELPASIDCacheEntry *vtd_pce, + Error **errp) { + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); - VTDPASIDEntry *pe =3D &vtd_as->pasid_cache_entry.pasid_entry; - uint32_t hwpt_id =3D idev->hwpt_id; + VTDPASIDEntry *pe =3D &vtd_pce->pe; + uint32_t hwpt_id =3D idev->hwpt_id, pasid =3D vtd_pce->pasid; bool ret; =20 /* @@ -145,13 +146,18 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDev= ice *vtd_hiod, } } =20 - ret =3D host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp); - trace_vtd_device_attach_hwpt(idev->devid, vtd_as->pasid, hwpt_id, ret); + if (pasid =3D=3D PASID_0) { + ret =3D host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp); + } else { + ret =3D host_iommu_device_iommufd_pasid_attach_hwpt(idev, pasid, + hwpt_id, errp); + } + trace_vtd_device_attach_hwpt(idev->devid, pasid, hwpt_id, ret); if (ret) { /* Destroy old fs_hwpt if it's a replacement */ - vtd_destroy_old_fs_hwpt(idev, vtd_as); + vtd_destroy_old_fs_hwpt(idev, vtd_pce); if (vtd_pe_pgtt_is_fst(pe)) { - vtd_as->fs_hwpt_id =3D hwpt_id; + vtd_pce->fs_hwpt_id =3D hwpt_id; } } else if (vtd_pe_pgtt_is_fst(pe)) { iommufd_backend_free_id(idev->iommufd, hwpt_id); @@ -160,15 +166,19 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDev= ice *vtd_hiod, return ret; } =20 -static bool vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, - VTDAddressSpace *vtd_as, Error **err= p) +static bool vtd_device_detach_iommufd(VTDACCELPASIDCacheEntry *vtd_pce, + Error **errp) { + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); - IntelIOMMUState *s =3D vtd_as->iommu_state; - uint32_t pasid =3D vtd_as->pasid; + IntelIOMMUState *s =3D vtd_hiod->iommu_state; + uint32_t pasid =3D vtd_pce->pasid; bool ret; =20 - if (s->dmar_enabled && s->root_scalable) { + if (pasid !=3D PASID_0) { + ret =3D host_iommu_device_iommufd_pasid_detach_hwpt(idev, pasid, e= rrp); + trace_vtd_device_detach_hwpt(idev->devid, pasid, ret); + } else if (s->dmar_enabled && s->root_scalable) { ret =3D host_iommu_device_iommufd_detach_hwpt(idev, errp); trace_vtd_device_detach_hwpt(idev->devid, pasid, ret); } else { @@ -183,65 +193,40 @@ static bool vtd_device_detach_iommufd(VTDHostIOMMUDev= ice *vtd_hiod, } =20 if (ret) { - vtd_destroy_old_fs_hwpt(idev, vtd_as); + vtd_destroy_old_fs_hwpt(idev, vtd_pce); } =20 return ret; } =20 -bool vtd_propagate_guest_pasid(VTDAddressSpace *vtd_as, Error **errp) -{ - VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; - VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); - - /* Ignore emulated device or legacy VFIO backed device */ - if (!vtd_as->iommu_state->fsts || !vtd_hiod) { - return true; - } - - if (pc_entry->valid) { - return vtd_device_attach_iommufd(vtd_hiod, vtd_as, errp); - } - - return vtd_device_detach_iommufd(vtd_hiod, vtd_as, errp); -} - /* - * This function is a loop function for the s->vtd_address_spaces - * list with VTDPIOTLBInvInfo as execution filter. It propagates - * the piotlb invalidation to host. + * This function is a loop function for the s->vtd_host_iommu_dev + * and vtd_hiod->pasid_cache_list lists with VTDPIOTLBInvInfo as + * execution filter. It propagates the piotlb invalidation to host. */ -static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value, - gpointer user_data) +static void vtd_flush_host_piotlb(VTDACCELPASIDCacheEntry *vtd_pce, + VTDPIOTLBInvInfo *piotlb_info) { - VTDPIOTLBInvInfo *piotlb_info =3D user_data; - VTDAddressSpace *vtd_as =3D value; - VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(vtd_as); - VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_pce->vtd_hiod; + VTDPASIDEntry *pe =3D &vtd_pce->pe; uint16_t did; =20 - if (!vtd_hiod) { - return; - } - - assert(vtd_as->pasid =3D=3D PCI_NO_PASID); - /* Nothing to do if there is no first stage HWPT attached */ - if (!pc_entry->valid || - !vtd_pe_pgtt_is_fst(&pc_entry->pasid_entry)) { + if (!vtd_pe_pgtt_is_fst(pe)) { return; } =20 - did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); + did =3D VTD_SM_PASID_ENTRY_DID(pe); =20 - if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D PAS= ID_0) { + if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D vtd= _pce->pasid) { HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod); uint32_t entry_num =3D 1; /* Only implement one request for simpli= city */ Error *local_err =3D NULL; struct iommu_hwpt_vtd_s1_invalidate *cache =3D piotlb_info->inv_da= ta; =20 - if (!iommufd_backend_invalidate_cache(idev->iommufd, vtd_as->fs_hw= pt_id, + if (!iommufd_backend_invalidate_cache(idev->iommufd, + vtd_pce->fs_hwpt_id, IOMMU_HWPT_INVALIDATE_DATA_V= TD_S1, sizeof(*cache), &entry_num, = cache, &local_err)) { @@ -257,6 +242,8 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *= s, uint16_t domain_id, { struct iommu_hwpt_vtd_s1_invalidate cache_info =3D { 0 }; VTDPIOTLBInvInfo piotlb_info; + VTDHostIOMMUDevice *vtd_hiod; + GHashTableIter as_it; =20 cache_info.addr =3D addr; cache_info.npages =3D npages; @@ -267,12 +254,19 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState= *s, uint16_t domain_id, piotlb_info.inv_data =3D &cache_info; =20 /* - * Go through each vtd_as instance in s->vtd_address_spaces, find out - * affected host devices which need host piotlb invalidation. Piotlb - * invalidation should check pasid cache per architecture point of vie= w. + * Go through each vtd_pce in vtd_hiod->pasid_cache_list for each host + * device, find out affected host device pasid which need host piotlb + * invalidation. Piotlb invalidation should check pasid cache per + * architecture point of view. */ - g_hash_table_foreach(s->vtd_address_spaces, - vtd_flush_host_piotlb_locked, &piotlb_info); + g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) { + VTDACCELPASIDCacheEntry *vtd_pce; + + QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { + vtd_flush_host_piotlb(vtd_pce, &piotlb_info); + } + } } =20 static void vtd_pasid_cache_invalidate_one(VTDACCELPASIDCacheEntry *vtd_pc= e, @@ -280,6 +274,7 @@ static void vtd_pasid_cache_invalidate_one(VTDACCELPASI= DCacheEntry *vtd_pce, { VTDPASIDEntry pe; uint16_t did; + Error *local_err =3D NULL; =20 /* * VTD_INV_DESC_PASIDC_G_DSI and VTD_INV_DESC_PASIDC_G_PASID_SI require @@ -305,6 +300,9 @@ static void vtd_pasid_cache_invalidate_one(VTDACCELPASI= DCacheEntry *vtd_pce, * to be either all-zero or non-present. Either case means existing * pasid cache should be invalidated. */ + if (!vtd_device_detach_iommufd(vtd_pce, &local_err)) { + error_reportf_err(local_err, "%s", "Detaching from HWPT failed= : "); + } QLIST_REMOVE(vtd_pce, next); g_free(vtd_pce); } @@ -325,11 +323,17 @@ static void vtd_find_add_pc(VTDHostIOMMUDevice *vtd_h= iod, uint32_t pasid, VTDPASIDEntry *pe) { VTDACCELPASIDCacheEntry *vtd_pce; + Error *local_err =3D NULL; =20 QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) { if (vtd_pce->pasid =3D=3D pasid) { if (vtd_pasid_entry_compare(pe, &vtd_pce->pe)) { vtd_pce->pe =3D *pe; + + if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { + error_reportf_err(local_err, "%s", + "Replacing HWPT attachment failed: "= ); + } } return; } @@ -340,6 +344,10 @@ static void vtd_find_add_pc(VTDHostIOMMUDevice *vtd_hi= od, uint32_t pasid, vtd_pce->pasid =3D pasid; vtd_pce->pe =3D *pe; QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next); + + if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) { + error_reportf_err(local_err, "%s", "Attaching to HWPT failed: "); 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a="96910515" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910515" X-CSE-ConnectionGUID: S8yN3RaWSfq9dsbcywbYJQ== X-CSE-MsgGUID: OltTE8ZESPCnazN5hdANsA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209652079" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 11/14] intel_iommu_accel: drop _lock suffix in vtd_flush_host_piotlb_all_locked() Date: Wed, 4 Feb 2026 22:11:29 -0500 Message-ID: <20260205031133.74357-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261209389158500 Content-Type: text/plain; charset="utf-8" In order to support PASID, we have switched from looping vtd_as to vtd_hiod, vtd_hiod represents host passthrough device and never deferenced without BQ= L. So we don't need extra iommu lock to protect it. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_accel.h | 14 +++++++------- hw/i386/intel_iommu.c | 7 ++++--- hw/i386/intel_iommu_accel.c | 6 +++--- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 1ae46d9250..3f1b1002b8 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -24,9 +24,9 @@ typedef struct VTDACCELPASIDCacheEntry { bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); -void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_= id, - uint32_t pasid, hwaddr addr, - uint64_t npages, bool ih); +void vtd_flush_host_piotlb_all_accel(IntelIOMMUState *s, uint16_t domain_i= d, + uint32_t pasid, hwaddr addr, + uint64_t npages, bool ih); void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_= info); void vtd_pasid_cache_reset_accel(IntelIOMMUState *s); void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops); @@ -51,10 +51,10 @@ static inline bool vtd_propagate_guest_pasid(VTDAddress= Space *vtd_as, return true; } =20 -static inline void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, - uint16_t domain_id, - uint32_t pasid, hwaddr= addr, - uint64_t npages, bool = ih) +static inline void vtd_flush_host_piotlb_all_accel(IntelIOMMUState *s, + uint16_t domain_id, + uint32_t pasid, hwaddr = addr, + uint64_t npages, bool i= h) { } =20 diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1626c8f96b..17252c804b 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2990,11 +2990,11 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUS= tate *s, info.domain_id =3D domain_id; info.pasid =3D pasid; =20 + vtd_flush_host_piotlb_all_accel(s, domain_id, pasid, 0, (uint64_t)-1, + false); vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, &info); - vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, 0, (uint64_t)-1, - false); vtd_iommu_unlock(s); =20 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { @@ -3024,10 +3024,11 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUSt= ate *s, uint16_t domain_id, info.addr =3D addr; info.mask =3D ~((1 << am) - 1); =20 + vtd_flush_host_piotlb_all_accel(s, domain_id, pasid, addr, 1 << am, ih= ); + vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page_piotlb, &info); - vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, addr, 1 << am, i= h); vtd_iommu_unlock(s); =20 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, pasid); diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index 5abc462a45..a30786e361 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -236,9 +236,9 @@ static void vtd_flush_host_piotlb(VTDACCELPASIDCacheEnt= ry *vtd_pce, } } =20 -void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_= id, - uint32_t pasid, hwaddr addr, - uint64_t npages, bool ih) +void vtd_flush_host_piotlb_all_accel(IntelIOMMUState *s, uint16_t domain_i= d, + uint32_t pasid, hwaddr addr, + uint64_t npages, bool ih) { struct iommu_hwpt_vtd_s1_invalidate cache_info =3D { 0 }; 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Wed, 04 Feb 2026 22:13:06 -0500 Received: from orviesa010.jf.intel.com ([10.64.159.150]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 19:13:02 -0800 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2026 19:12:59 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770261184; x=1801797184; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+7Rg4CxfOwO1+maXnQeeixDZgCurQHse/sW7HpMdvmA=; b=A+5wTJsSVDlwNpbfynre5OQBf//5EXGjPwi6xxOABZpXtB5o5QyGuMjl DIrINK6uCb2ENtJDlF6Nn6GLV3bN3EZfLLNpa81exWScRrCQ+1EEsxlUL CfLukg7OH+tdA4n+ofvWouKZRQO9DHspRg8v6alU1dn0rF+V+gIOravnr 4jVPMnPEXKkmt5C9I7kODmP/6VjogA70YmQoq99TIGJSXaUw/ndybZ+nn 7uGCtErsU2rN2WPRjNLoY6gtT/SpQjEg9zAiJb5DZpOIpL08bkNoOpahV YZ7Sv/YMROq619HddhAm4nWGY8sH8jrpYzpZLruB0JET7cLb2itTR38SS g==; X-CSE-ConnectionGUID: 3oIujSkoTOSBv1qgLARM/w== X-CSE-MsgGUID: YV9LjWfoSiSRrsrYIjNcVw== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="96910524" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910524" X-CSE-ConnectionGUID: QiKbCeqCShCDLt813VssPQ== X-CSE-MsgGUID: UQJMJ5tRRr2yCzVydM6xWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209652094" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 12/14] intel_iommu_accel: Add pasid bits size check Date: Wed, 4 Feb 2026 22:11:30 -0500 Message-ID: <20260205031133.74357-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261258781158500 Content-Type: text/plain; charset="utf-8" If pasid bits size is bigger than host side, host could fail to emulate all bindings in guest. Add a check to fail device plug early. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu_accel.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index fe81c47819..2901cf44aa 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -194,6 +194,7 @@ #define VTD_ECAP_PRS (1ULL << 29) #define VTD_ECAP_MHMV (15ULL << 20) #define VTD_ECAP_SRS (1ULL << 31) +#define VTD_ECAP_PSS(x) extract64(x, 35, 5) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_SMTS (1ULL << 43) #define VTD_ECAP_SSTS (1ULL << 46) diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index a30786e361..61ff531803 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -44,6 +44,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMM= UDevice *vtd_hiod, HostIOMMUDevice *hiod =3D vtd_hiod->hiod; struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; 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d="scan'208";a="209652108" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan , Yi Sun Subject: [RFC PATCH 13/14] intel_iommu: Drop pasid related check Date: Wed, 4 Feb 2026 22:11:31 -0500 Message-ID: <20260205031133.74357-14-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261228162154100 Content-Type: text/plain; charset="utf-8" The check of 's->pasid && x86_iommu->dt_supported' is an overkill, because all emulated devices don't support PASID capability yet, they never send Requests-with-PASID, no pasid tagged iotlb entries are cached in the device. Even if guest send PASID-based-Device-TLB invalidation request, we can ignore it safely. Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 17252c804b..4ab50a9fd9 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5490,17 +5490,6 @@ static void vtd_realize(DeviceState *dev, Error **er= rp) X86MachineState *x86ms =3D X86_MACHINE(ms); PCIBus *bus =3D pcms->pcibus; IntelIOMMUState *s =3D INTEL_IOMMU_DEVICE(dev); - X86IOMMUState *x86_iommu =3D X86_IOMMU_DEVICE(s); - - if (s->pasid && x86_iommu->dt_supported) { - /* - * PASID-based-Device-TLB Invalidate Descriptor is not - * implemented and it requires support from vhost layer which - * needs to be implemented in the future. - */ - error_setg(errp, "PASID based device IOTLB is not supported"); - return; - } =20 if (!vtd_decide_config(s, errp)) { return; --=20 2.47.3 From nobody Sun Feb 8 22:22:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="96910537" X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="96910537" X-CSE-ConnectionGUID: AnFYNdwVQf+fV0iOjLj5Bg== X-CSE-MsgGUID: 9mg2eEq7SkiOJyLN7VtG0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,273,1763452800"; d="scan'208";a="209652138" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [RFC PATCH 14/14] intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED when configured Date: Wed, 4 Feb 2026 22:11:32 -0500 Message-ID: <20260205031133.74357-15-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260205031133.74357-1-zhenzhong.duan@intel.com> References: <20260205031133.74357-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.7; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1770261229355158500 Content-Type: text/plain; charset="utf-8" VFIO device will check flag VIOMMU_FLAG_PASID_SUPPORTED and expose PASID capability, or else guest could not enable PASID of this device even if vIOMMU's pasid is configured. This is the final knob to enable PASID. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4ab50a9fd9..86998dad94 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4727,6 +4727,7 @@ static uint64_t vtd_get_viommu_flags(void *opaque) uint64_t flags; =20 flags =3D s->fsts ? VIOMMU_FLAG_WANT_NESTING_PARENT : 0; + flags |=3D s->pasid ? VIOMMU_FLAG_PASID_SUPPORTED : 0; =20 return flags; } --=20 2.47.3