From nobody Mon Feb 9 08:11:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770226423; cv=none; d=zohomail.com; s=zohoarc; b=KwIWtAB2EClDg8FWdsSWLJBSWCegY6P5Yc0UDYwOMSNDoeTs+/k6Dp1y/8PiJ23qRrEKQtoPDMnOM6cvrQlsjTGZpH++nLaXskUGKX+q6UlJF6dfcASAJ3lcA0d+nliMu2Tw1AamI4OwnWTpGshpPZ+FTqP8Mamraiff09YujVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770226423; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=BhZHOq1/iyOAkpBxYww/WWqSyiBRgh597mSXBHBJ9Ts=; b=W0ZQigDmG5eVB93TMbODVEBm8pEAeW07D9mcU9NTKjTomwyuceBMS+8Y4K9w/UHUVefd0YyLny6a84PHkRQ5vlqk3DvsJSxhxoqnaL+x/WN8eLHjON73mbe2RJABNGC9OC27Q18T31x0MZCcSDS7z0uvpKoxPISHPihtkpZkPHs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770226423027683.8800300864228; Wed, 4 Feb 2026 09:33:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vngkw-0007cR-C9; Wed, 04 Feb 2026 12:33:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vngkt-0007Sd-Jt for qemu-devel@nongnu.org; Wed, 04 Feb 2026 12:33:31 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vngkr-0005es-Mg for qemu-devel@nongnu.org; Wed, 04 Feb 2026 12:33:31 -0500 Received: from mail.maildlp.com (unknown [172.18.224.150]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4f5nVZ1RWVzJ46BN; Thu, 5 Feb 2026 01:32:38 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id 883624056A; Thu, 5 Feb 2026 01:33:27 +0800 (CST) Received: from SecurePC-101-06.huawei.com (10.122.19.247) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Feb 2026 17:33:26 +0000 To: Michael Tsirkin , , Arpit Kumar CC: , , Ravi Shankar , Marcel Apfelbaum , Michael Roth Subject: [PATCH qemu v5 2/3] hw/cxl: Get Physical Port State - update for PCIe flit mode Date: Wed, 4 Feb 2026 17:32:22 +0000 Message-ID: <20260204173223.44122-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204173223.44122-1-Jonathan.Cameron@huawei.com> References: <20260204173223.44122-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml500011.china.huawei.com (7.191.174.215) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770226426109158500 Content-Type: text/plain; charset="utf-8" Recent support for 256B flits, was not accounted for in this FMAPI command that should be retrieving the current status of Physical Switch Ports. Note x-flit-mode control is via the downstream devices, so for USPs the property must be checked to establish support, but for DSPs this mode is always supported (control is with the next port downstream, typically the end point. All cases the linksta2 register may be queried to obtain current status. Note the PCI spec is a little confusing as it refers to this bit only being non 0 if Device Readiness Status (DRS) is in particular states (basically link trained) but Flit mode is a separate feature and DRS may not be present. It is not yet emulated in QEMU. So assume that we should reflect what states DRS would be reporting if it were actually present. One small thing to note is that the current link width for a port with nothing connected reports the same as the capability. This is odd but valid because the value under these circumstances is undefined (PCIe r6.2 table 7-26 Link Status Register - field Current Link Speed.) Signed-off-by: Jonathan Cameron --- hw/cxl/cxl-mailbox-utils.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 1c8cbe0f682d..b6ac987ee021 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -627,9 +627,26 @@ static CXLRetCode cmd_get_physical_port_state(const st= ruct cxl_cmd *cmd, port->config_state =3D CXL_PORT_CONFIG_STATE_DSP; if (ds_dev) { if (object_dynamic_cast(OBJECT(ds_dev), TYPE_CXL_TYPE3)) { + uint16_t lnksta2; + + if (!port_dev->exp.exp_cap) { + return CXL_MBOX_INTERNAL_ERROR; + } + + lnksta2 =3D port_dev->config_read(port_dev, + port_dev->exp.exp_cap + PCI_EXP_LNKSTA2, + sizeof(lnksta2)); + /* Assume MLD for now */ port->connected_device_type =3D CXL_PORT_CONNECTED_DEV_TYPE_3_MLD; + if (lnksta2 & PCI_EXP_LNKSTA2_FLIT) { + port->connected_device_mode =3D + CXL_PORT_CONNECTED_DEV_MODE_256B; + } else { + port->connected_device_mode =3D + CXL_PORT_CONNECTED_DEV_MODE_68B_VH; + } } else { port->connected_device_type =3D CXL_PORT_CONNECTED_DEV_TYPE_PCIE; @@ -642,12 +659,17 @@ static CXLRetCode cmd_get_physical_port_state(const s= truct cxl_cmd *cmd, port->connected_device_mode =3D CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN; } + /* DSP currently always support modes implemented in QEMU */ + port->supported_cxl_mode_bitmask =3D CXL_PORT_SUPPORTS_68B_VH | + CXL_PORT_SUPPORTS_256B; port->supported_ld_count =3D 3; } else if (usp->port =3D=3D in->ports[i]) { /* USP */ port_dev =3D PCI_DEVICE(usp); port->config_state =3D CXL_PORT_CONFIG_STATE_USP; port->connected_device_type =3D 0; /* Reserved for USP */ port->connected_device_mode =3D 0; /* Reserved for USP */ + port->supported_cxl_mode_bitmask =3D CXL_PORT_SUPPORTS_68B_VH | + (CXL_USP(usp)->flitmode ? CXL_PORT_SUPPORTS_256B : 0); } else { return CXL_MBOX_INVALID_INPUT; } @@ -676,8 +698,6 @@ static CXLRetCode cmd_get_physical_port_state(const str= uct cxl_cmd *cmd, /* TODO: Track down if we can get the rest of the info */ port->ltssm_state =3D 0x7; port->first_lane_num =3D 0; - port->link_state =3D 0; - port->supported_cxl_mode_bitmask =3D CXL_PORT_SUPPORTS_68B_VH; } =20 pl_size =3D sizeof(*out) + sizeof(*out->ports) * in->num_ports; --=20 2.51.0