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charset="utf-8" Hardware testing on the Rage 128 confirms that (SRC/DST)_OFFSET, and (SRC/DST)_PITCH are latched when (SRC/DST)_PITCH_OFFSET_CNTL bits in DP_GUI_MASTER_CNTL are set to "default". The earlier approach looked at the state of the (SRC/DST)_PITCH_OFFSET_CNTL bits when offset and pitch registers were used. This meant that when (SRC/DST)_PITCH_OFFSET_CNTL was reset to "leave alone" the old values stored in the registers would return. This is not how the real hardware works. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 9 +++++++++ hw/display/ati_2d.c | 13 ++++--------- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 028efd13e1..ce23e5e48b 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -868,6 +868,15 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dp_datatype =3D (data & 0x0f00) >> 8 | (data & 0x30f0) << = 4 | (data & 0x4000) << 16; s->regs.dp_mix =3D (data & GMC_ROP3_MASK) | (data & 0x7000000) >> = 16; + + if (!(data & GMC_SRC_PITCH_OFFSET_CNTL)) { + s->regs.src_offset =3D s->regs.default_offset; + s->regs.src_pitch =3D s->regs.default_pitch; + } + if (!(data & GMC_DST_PITCH_OFFSET_CNTL)) { + s->regs.dst_offset =3D s->regs.default_offset; + s->regs.dst_pitch =3D s->regs.default_pitch; + } break; case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 309bb5ccb6..a8c4c534b9 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -43,8 +43,6 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } =20 -#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CN= TL) - void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -63,13 +61,12 @@ void ati_2d_blt(ATIVGAState *s) qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; } - int dst_stride =3D DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_= pitch; + int dst_stride =3D s->regs.dst_pitch; if (!dst_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - uint8_t *dst_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? - s->regs.dst_offset : s->regs.default_offset); + uint8_t *dst_bits =3D s->vga.vram_ptr + s->regs.dst_offset; =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; @@ -97,14 +94,12 @@ void ati_2d_blt(ATIVGAState *s) s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_wid= th); unsigned src_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_hei= ght); - int src_stride =3D DEFAULT_CNTL ? - s->regs.src_pitch : s->regs.default_pitch; + int src_stride =3D s->regs.src_pitch; if (!src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); return; } - uint8_t *src_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? - s->regs.src_offset : s->regs.default_offset); + uint8_t *src_bits =3D s->vga.vram_ptr + s->regs.src_offset; =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { src_bits +=3D s->regs.crtc_offset & 0x07ffffff; --=20 2.52.0