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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=202.12.124.156; envelope-from=chad@jablonski.xyz; helo=fhigh-b5-smtp.messagingengine.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.499, PDS_OTHER_BAD_TLD=1.999, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1770223649199154100 Content-Type: text/plain; charset="utf-8" Writing to any of the HOST_DATA0-7 registers pushes the written data into a 128-bit accumulator. When the accumulator is full a flush is triggered to copy it to the framebuffer. A final write to HOST_DATA_LAST will also initiate a flush. The flush itself is left for the next patch. Unaligned HOST_DATA* writes result in, from what I can tell, undefined behavior on real hardware. A well-behaved driver shouldn't be doing this anyway. For that reason they are not handled here at all. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 32 ++++++++++++++++++++++++++++++++ hw/display/ati_dbg.c | 9 +++++++++ hw/display/ati_int.h | 8 ++++++++ hw/display/ati_regs.h | 9 +++++++++ 4 files changed, 58 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index 6cf243bcf9..fd717044b0 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -561,6 +561,13 @@ static inline void ati_reg_write_offs(uint32_t *reg, i= nt offs, } } =20 +static void ati_host_data_reset(ATIHostDataState *hd) +{ + hd->next =3D 0; + hd->row =3D 0; + hd->col =3D 0; +} + static void ati_mm_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -836,6 +843,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, break; case DST_WIDTH: s->regs.dst_width =3D data & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DST_HEIGHT: @@ -886,6 +894,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_HEIGHT_WIDTH: s->regs.dst_width =3D data & 0x3fff; s->regs.dst_height =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DP_GUI_MASTER_CNTL: @@ -916,6 +925,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; s->regs.dst_width =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case SRC_X_Y: @@ -929,6 +939,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_WIDTH_HEIGHT: s->regs.dst_height =3D data & 0x3fff; s->regs.dst_width =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DST_HEIGHT_Y: @@ -1024,6 +1035,25 @@ static void ati_mm_write(void *opaque, hwaddr addr, case SRC_SC_BOTTOM: s->regs.src_sc_bottom =3D data & 0x3fff; break; + case HOST_DATA0: + case HOST_DATA1: + case HOST_DATA2: + case HOST_DATA3: + case HOST_DATA4: + case HOST_DATA5: + case HOST_DATA6: + case HOST_DATA7: + s->host_data.acc[s->host_data.next++] =3D data; + if (s->host_data.next >=3D 4) { + qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\= n"); + s->host_data.next =3D 0; + } + break; + case HOST_DATA_LAST: + s->host_data.acc[s->host_data.next] =3D data; + qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\n"); + ati_host_data_reset(&s->host_data); + break; default: break; } @@ -1129,6 +1159,8 @@ static void ati_vga_reset(DeviceState *dev) /* reset vga */ vga_common_reset(&s->vga); s->mode =3D VGA_MODE; + + ati_host_data_reset(&s->host_data); } =20 static void ati_vga_exit(PCIDevice *dev) diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c index 3ffa7f35df..5c799d540a 100644 --- a/hw/display/ati_dbg.c +++ b/hw/display/ati_dbg.c @@ -252,6 +252,15 @@ static struct ati_regdesc ati_reg_names[] =3D { {"MC_SRC1_CNTL", 0x19D8}, {"TEX_CNTL", 0x1800}, {"RAGE128_MPP_TB_CONFIG", 0x01c0}, + {"HOST_DATA0", 0x17c0}, + {"HOST_DATA1", 0x17c4}, + {"HOST_DATA2", 0x17c8}, + {"HOST_DATA3", 0x17cc}, + {"HOST_DATA4", 0x17d0}, + {"HOST_DATA5", 0x17d4}, + {"HOST_DATA6", 0x17d8}, + {"HOST_DATA7", 0x17dc}, + {"HOST_DATA_LAST", 0x17e0}, {NULL, -1} }; =20 diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 98f57ca5fa..ef474e366e 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -95,6 +95,13 @@ typedef struct ATIVGARegs { uint32_t default_tile; } ATIVGARegs; =20 +typedef struct ATIHostDataState { + uint32_t row; + uint32_t col; + uint32_t next; + uint32_t acc[4]; +} ATIHostDataState; + struct ATIVGAState { PCIDevice dev; VGACommonState vga; @@ -112,6 +119,7 @@ struct ATIVGAState { MemoryRegion io; MemoryRegion mm; ATIVGARegs regs; + ATIHostDataState host_data; }; =20 const char *ati_reg_name(int num); diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 3999edb9b7..48f15e9b1d 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -252,6 +252,15 @@ #define DP_T12_CNTL 0x178c #define DST_BRES_T1_LNTH 0x1790 #define DST_BRES_T2_LNTH 0x1794 +#define HOST_DATA0 0x17c0 +#define HOST_DATA1 0x17c4 +#define HOST_DATA2 0x17c8 +#define HOST_DATA3 0x17cc +#define HOST_DATA4 0x17d0 +#define HOST_DATA5 0x17d4 +#define HOST_DATA6 0x17d8 +#define HOST_DATA7 0x17dc +#define HOST_DATA_LAST 0x17e0 #define SCALE_SRC_HEIGHT_WIDTH 0x1994 #define SCALE_OFFSET_0 0x1998 #define SCALE_PITCH 0x199c --=20 2.52.0