From nobody Mon Feb 9 06:08:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770217269; cv=none; d=zohomail.com; s=zohoarc; b=bMAjiDF0+4UtepKeipG8Ih/xF73ssmhenRkmASWIT0rdHpY/AMX8BBco48JSCt3lmvihQ8SGPZMfzna+/bCxgP+ejvQDr1tz6Cu0MDNrUNWAc+rQgYRyRv3qrP4bs4kj9i22rkiLOT3clWUhxc3Wijo6aXMm+lhFWFWcU/IGtsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770217269; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=aVGCBFedSzfOUOq2Dkz7hWF8+pQAUixGv3BumgXHm3w=; b=aM5hL4FyMUqWtR5gjF5Nb4xTKUOU9QWg0nHhglYMu7SeE5xfxT3yB6eea12t2/iEYoXKxrTpw460xirKd9GU9m/z3znJUx8nLswlj4Ymaq59QE++Z51t5/EmDvfUfR4z9yru7xctBSLR5QxT+s9jE4w1E4OdBgfbRweP1g2XNUo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770217269789711.30163259478; Wed, 4 Feb 2026 07:01:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vneN1-00056V-8M; Wed, 04 Feb 2026 10:00:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vneMz-00055z-UM for qemu-devel@nongnu.org; Wed, 04 Feb 2026 10:00:41 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vneMy-0005N8-9i for qemu-devel@nongnu.org; Wed, 04 Feb 2026 10:00:41 -0500 Received: from mail.maildlp.com (unknown [172.18.224.83]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4f5k6F2mzFzJ46ZW; Wed, 4 Feb 2026 22:59:49 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id 8DF5A40086; Wed, 4 Feb 2026 23:00:38 +0800 (CST) Received: from a2303103017.china.huawei.com (10.47.68.30) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Feb 2026 15:00:37 +0000 To: CC: , , , , , , , , , , , , , , Subject: [PATCH v2 1/2] hw/cxl: Use HPA in cxl_cfmws_find_device() rather than offset in window. Date: Wed, 4 Feb 2026 15:00:00 +0000 Message-ID: <20260204150002.669-2-alireza.sanaee@huawei.com> X-Mailer: git-send-email 2.51.0.windows.2 In-Reply-To: <20260204150002.669-1-alireza.sanaee@huawei.com> References: <20260204150002.669-1-alireza.sanaee@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.47.68.30] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=alireza.sanaee@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alireza Sanaee From: Alireza Sanaee via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770217273622154100 Content-Type: text/plain; charset="utf-8" This function will shortly be used to help find if there is a route to a device, serving an HPA, under a particular fixed memory window. Rather than having that new use case subtract the base address in the caller, only to add it again in cxl_cfmws_find_device(), push the responsibility for calculating the HPA to the caller. This also reduces the inconsistency in the meaning of the hwaddr addr parameter between this function and the calls made within it that access the HDM decoders that operating on HPA. Signed-off-by: Alireza Sanaee Tested-by: Gregory Price --- hw/cxl/cxl-host.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index f3479b1991..9633b01abf 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -168,8 +168,6 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow = *fw, hwaddr addr) bool target_found; PCIDevice *rp, *d; =20 - /* Address is relative to memory region. Convert to HPA */ - addr +=3D fw->base; =20 rb_index =3D (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_target= s; hb =3D PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl_host_bridge); @@ -254,7 +252,7 @@ static MemTxResult cxl_read_cfmws(void *opaque, hwaddr = addr, uint64_t *data, CXLFixedWindow *fw =3D opaque; PCIDevice *d; =20 - d =3D cxl_cfmws_find_device(fw, addr); + d =3D cxl_cfmws_find_device(fw, addr + fw->base, true); if (d =3D=3D NULL) { *data =3D 0; /* Reads to invalid address return poison */ @@ -271,7 +269,7 @@ static MemTxResult cxl_write_cfmws(void *opaque, hwaddr= addr, CXLFixedWindow *fw =3D opaque; PCIDevice *d; =20 - d =3D cxl_cfmws_find_device(fw, addr); + d =3D cxl_cfmws_find_device(fw, addr + fw->base, true); if (d =3D=3D NULL) { /* Writes to invalid address are silent */ return MEMTX_OK; --=20 2.43.0 From nobody Mon Feb 9 06:08:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 4 Feb 2026 23:01:10 +0800 (CST) Received: from a2303103017.china.huawei.com (10.47.68.30) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Feb 2026 15:01:10 +0000 To: CC: , , , , , , , , , , , , , , Subject: [PATCH v2 2/2] hw/cxl: Add a performant (and correct) path for the non interleaved cases Date: Wed, 4 Feb 2026 15:00:01 +0000 Message-ID: <20260204150002.669-3-alireza.sanaee@huawei.com> X-Mailer: git-send-email 2.51.0.windows.2 In-Reply-To: <20260204150002.669-1-alireza.sanaee@huawei.com> References: <20260204150002.669-1-alireza.sanaee@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.47.68.30] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=alireza.sanaee@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alireza Sanaee From: Alireza Sanaee via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770217299056158500 Content-Type: text/plain; charset="utf-8" The CXL address to device decoding logic is complex because of the need to correctly decode fine grained interleave. The current implementation prevents use with KVM where executed instructions may reside in that memory and gives very slow performance even in TCG. In many real cases non interleaved memory configurations are useful and for those we can use a more conventional memory region alias allowing similar performance to other memory in the system. Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Signed-off-by: Alireza Sanaee Tested-by: Gregory Price --- hw/cxl/cxl-component-utils.c | 8 ++ hw/cxl/cxl-host.c | 197 ++++++++++++++++++++++++++++++++++- hw/mem/cxl_type3.c | 4 + include/hw/cxl/cxl.h | 1 + include/hw/cxl/cxl_device.h | 1 + 5 files changed, 206 insertions(+), 5 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index d36162e91b..d459d04b6d 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -142,6 +142,14 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cs= tate, hwaddr offset, value =3D FIELD_DP32(value, CXL_HDM_DECODER0_CTRL, COMMITTED, 0); } stl_le_p((uint8_t *)cache_mem + offset, value); + + if (should_commit) { + cfmws_update_non_interleaved(true); + } + + if (should_uncommit) { + cfmws_update_non_interleaved(false); + } } =20 static void bi_handler(CXLComponentState *cxl_cstate, hwaddr offset, diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c index 9633b01abf..1fcfe01164 100644 --- a/hw/cxl/cxl-host.c +++ b/hw/cxl/cxl-host.c @@ -104,7 +104,7 @@ void cxl_fmws_link_targets(Error **errp) } =20 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr, - uint8_t *target) + uint8_t *target, bool *interleaved) { int hdm_inc =3D R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_L= O; unsigned int hdm_count; @@ -138,6 +138,11 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, h= waddr addr, found =3D true; ig_enc =3D FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG); iw_enc =3D FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW); + + if (interleaved) { + *interleaved =3D iw_enc !=3D 0; + } + target_idx =3D (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc); =20 if (target_idx < 4) { @@ -157,7 +162,8 @@ static bool cxl_hdm_find_target(uint32_t *cache_mem, hw= addr addr, return found; } =20 -static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr) +static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr, + bool allow_interleave) { CXLComponentState *hb_cstate, *usp_cstate; PCIHostState *hb; @@ -165,9 +171,12 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow= *fw, hwaddr addr) int rb_index; uint32_t *cache_mem; uint8_t target; - bool target_found; + bool target_found, interleaved; PCIDevice *rp, *d; =20 + if ((fw->num_targets > 1) && !allow_interleave) { + return NULL; + } =20 rb_index =3D (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_target= s; hb =3D PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl_host_bridge); @@ -188,11 +197,16 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindo= w *fw, hwaddr addr) =20 cache_mem =3D hb_cstate->crb.cache_mem_registers; =20 - target_found =3D cxl_hdm_find_target(cache_mem, addr, &target); + target_found =3D cxl_hdm_find_target(cache_mem, addr, &target, + &interleaved); if (!target_found) { return NULL; } =20 + if (interleaved && !allow_interleave) { + return NULL; + } + rp =3D pcie_find_port_by_pn(hb->bus, target); if (!rp) { return NULL; @@ -224,11 +238,15 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindo= w *fw, hwaddr addr) =20 cache_mem =3D usp_cstate->crb.cache_mem_registers; =20 - target_found =3D cxl_hdm_find_target(cache_mem, addr, &target); + target_found =3D cxl_hdm_find_target(cache_mem, addr, &target, &interl= eaved); if (!target_found) { return NULL; } =20 + if (interleaved && !allow_interleave) { + return NULL; + } + d =3D pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target); if (!d) { return NULL; @@ -246,6 +264,175 @@ static PCIDevice *cxl_cfmws_find_device(CXLFixedWindo= w *fw, hwaddr addr) return d; } =20 +typedef struct CXLDirectPTState { + CXLType3Dev *ct3d; + hwaddr decoder_base; + hwaddr decoder_size; + hwaddr dpa_base; + unsigned int hdm_decoder_idx; + bool commit; +} CXLDirectPTState; + +static void cxl_fmws_direct_passthrough_setup(CXLDirectPTState *state, + CXLFixedWindow *fw) +{ + CXLType3Dev *ct3d =3D state->ct3d; + MemoryRegion *mr =3D NULL; + uint64_t vmr_size =3D 0, pmr_size =3D 0, offset =3D 0; + MemoryRegion *direct_mr; + + if (ct3d->hostvmem) { + MemoryRegion *vmr =3D host_memory_backend_get_memory(ct3d->hostvme= m); + + vmr_size =3D memory_region_size(vmr); + if (state->dpa_base < vmr_size) { + mr =3D vmr; + offset =3D state->dpa_base; + } + } + if (!mr && ct3d->hostpmem) { + MemoryRegion *pmr =3D host_memory_backend_get_memory(ct3d->hostpme= m); + + pmr_size =3D memory_region_size(pmr); + if (state->dpa_base - vmr_size < pmr_size) { + mr =3D pmr; + offset =3D state->dpa_base - vmr_size; + } + } + if (!mr) { + return; + } + + direct_mr =3D &ct3d->direct_mr[state->hdm_decoder_idx]; + if (memory_region_is_mapped(direct_mr)) { + return; + } + + memory_region_init_alias(direct_mr, OBJECT(ct3d), "direct-mapping", mr, + offset, state->decoder_size); + memory_region_add_subregion(&fw->mr, + state->decoder_base - fw->base, direct_mr); +} + +static void cxl_fmws_direct_passthrough_teardown(CXLDirectPTState *state, + CXLFixedWindow *fw) +{ + CXLType3Dev *ct3d =3D state->ct3d; + MemoryRegion *direct_mr =3D &ct3d->direct_mr[state->hdm_decoder_idx]; + + if (memory_region_is_mapped(direct_mr)) { + memory_region_del_subregion(&fw->mr, direct_mr); + } +} + +static int cxl_fmws_direct_passthrough(Object *obj, void *opaque) +{ + CXLDirectPTState *state =3D opaque; + CXLFixedWindow *fw; + + if (!object_dynamic_cast(obj, TYPE_CXL_FMW)) { + return 0; + } + + fw =3D CXL_FMW(obj); + + /* Verify not interleaved */ + if (!cxl_cfmws_find_device(fw, state->decoder_base, false)) { + return 0; + } + + if (state->commit) { + cxl_fmws_direct_passthrough_setup(state, fw); + } else { + cxl_fmws_direct_passthrough_teardown(state, fw); + } + + return 0; +} + +static int update_non_interleaved(Object *obj, void *opaque) +{ + const int hdm_inc =3D R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_= BASE_LO; + bool commit =3D *(bool *)opaque; + CXLType3Dev *ct3d; + uint32_t *cache_mem; + unsigned int hdm_count, i; + uint32_t cap; + uint64_t dpa_base =3D 0; + + if (!object_dynamic_cast(obj, TYPE_CXL_TYPE3)) { + return 0; + } + + ct3d =3D CXL_TYPE3(obj); + cache_mem =3D ct3d->cxl_cstate.crb.cache_mem_registers; + cap =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER_CAPABILITY); + hdm_count =3D cxl_decoder_count_dec(FIELD_EX32(cap, + CXL_HDM_DECODER_CAPABILIT= Y, + DECODER_COUNT)); + /* + * Walk the decoders and find any committed with iw set to 0 + * (non interleaved). + */ + for (i =3D 0; i < hdm_count; i++) { + uint64_t decoder_base, decoder_size, skip; + uint32_t hdm_ctrl, low, high; + int iw, committed; + + hdm_ctrl =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + i * hd= m_inc); + committed =3D FIELD_EX32(hdm_ctrl, CXL_HDM_DECODER0_CTRL, COMMITTE= D); + if (commit ^ committed) { + return 0; + } + + low =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_DPA_SKIP_LO + + i * hdm_inc); + high =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_DPA_SKIP_HI + + i * hdm_inc); + skip =3D ((uint64_t)high << 32) | (low & 0xf0000000); + dpa_base +=3D skip; + + low =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_= inc); + high =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + i * hdm= _inc); + decoder_size =3D ((uint64_t)high << 32) | (low & 0xf0000000); + + low =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + i * hdm_= inc); + high =3D ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + i * hdm= _inc); + decoder_base =3D ((uint64_t)high << 32) | (low & 0xf0000000); + + iw =3D FIELD_EX32(hdm_ctrl, CXL_HDM_DECODER0_CTRL, IW); + + if (iw =3D=3D 0) { + CXLDirectPTState state =3D { + .ct3d =3D ct3d, + .decoder_base =3D decoder_base, + .decoder_size =3D decoder_size, + .dpa_base =3D dpa_base, + .hdm_decoder_idx =3D i, + .commit =3D commit, + }; + + object_child_foreach_recursive(object_get_root(), + cxl_fmws_direct_passthrough, &s= tate); + } + dpa_base +=3D decoder_size / cxl_interleave_ways_dec(iw, &error_fa= tal); + } + + return 0; +} + +bool cfmws_update_non_interleaved(bool commit) +{ + /* + * Walk endpoints to find committed decoders then check if they are not + * interleaved (but path is fully set up). + */ + object_child_foreach_recursive(object_get_root(), + update_non_interleaved, &commit); + + return false; +} + static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *dat= a, unsigned size, MemTxAttrs attrs) { diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 3f09c589ae..a95f6a4014 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -427,6 +427,8 @@ static void hdm_decoder_commit(CXLType3Dev *ct3d, int w= hich) ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); =20 stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl); + + cfmws_update_non_interleaved(true); } =20 static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int which) @@ -442,6 +444,8 @@ static void hdm_decoder_uncommit(CXLType3Dev *ct3d, int= which) ctrl =3D FIELD_DP32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED, 0); =20 stl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + which * hdm_inc, ctrl); + + cfmws_update_non_interleaved(false); } =20 static int ct3d_qmp_uncor_err_to_cxl(CxlUncorErrorType qmp_err) diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 998f495a98..931f5680bd 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -71,4 +71,5 @@ CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp= ); typedef struct CXLDownstreamPort CXLDownstreamPort; DECLARE_INSTANCE_CHECKER(CXLDownstreamPort, CXL_DSP, TYPE_CXL_DSP) =20 +bool cfmws_update_non_interleaved(bool commit); #endif diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 393f312217..d295469301 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -712,6 +712,7 @@ struct CXLType3Dev { uint64_t sn; =20 /* State */ + MemoryRegion direct_mr[CXL_HDM_DECODER_COUNT]; AddressSpace hostvmem_as; AddressSpace hostpmem_as; CXLComponentState cxl_cstate; --=20 2.43.0