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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1770211972; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vR2fBcORYdmt1YPsf7yFFS0kUNSb0702Te0uJ25zGIo=; b=Jno1SCmo2e8MtkQZegN/PsE8AxhyxHWLKfAcUgZItS5qTz4WJ7YXsNTqggN0EQu+s/MaNj LIeyrMAfyrLPoj6MwpN8F7htpq+EroTSvbzRIGEqPqHhS5OzIle94UnshJ6ez0tQE8GYKf 3Wmjk2SyzQ2dMdmOAYga4MiryIovP9w= X-MC-Unique: d7zoEFN8NiGZbBCnsVrEWQ-1 X-Mimecast-MFC-AGG-ID: d7zoEFN8NiGZbBCnsVrEWQ_1770211970 From: Cornelia Huck To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Eric Auger , Sebastian Ott , Jonathan Cameron , Alireza Sanaee , Cornelia Huck Subject: [PATCH v2 1/3] arm: handle demuxed ID registers Date: Wed, 4 Feb 2026 14:32:27 +0100 Message-ID: <20260204133229.297061-2-cohuck@redhat.com> In-Reply-To: <20260204133229.297061-1-cohuck@redhat.com> References: <20260204133229.297061-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" For some registers, we do not have a single ID register, but actually an array of values (e.g. CCSIDR_EL1, where the actual value is determined by whatever CSSELR_EL1 points to.) If we want to avoid using a different way to handle registers like that for every instance, we should provide some kind of infrastructure. Therefore, add accessors {GET,SET}_IDREG_DEMUX that are similar to the accessors we already use for regular ID registers. Tested-by: Alireza Sanaee Reviewed-by: Sebastian Ott Signed-off-by: Cornelia Huck --- target/arm/cpu-sysregs.h | 13 +++++++++++++ target/arm/cpu.h | 20 ++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h index 7877a3b06a8e..911f54bc8a4f 100644 --- a/target/arm/cpu-sysregs.h +++ b/target/arm/cpu-sysregs.h @@ -35,6 +35,19 @@ typedef enum ARMSysRegs { =20 #undef DEF =20 +/* ID registers that vary based upon another register */ +typedef enum ARMIDRegisterDemuxIdx { + NUM_ID_DEMUX_IDX, +} ARMIDRegisterDemuxIdx; + +/* + * Number of register variants per demuxed register, trying to accommodate + * possible use cases. + * CCSIDR_EL1 currently needs 7*2, could be 7 more with FEAT_MTE2, in which + * case we would need to bump this number. + */ +#define ID_DEMUX_ARRAYLEN 16 + extern const uint32_t id_register_sysreg[NUM_ID_IDX]; =20 int get_sysreg_idx(ARMSysRegs sysreg); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 21fee5e840b7..f9d51c0fc187 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -906,6 +906,25 @@ typedef struct { i_->idregs[REG ## _EL1_IDX]; \ }) =20 +#define SET_IDREG_DEMUX(ISAR, REG, INDEX, VALUE) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs_demux[REG ## _EL1_DEMUX_IDX][INDEX] =3D VALUE; \ + }) + +#define GET_IDREG_DEMUX(ISAR, REG, INDEX) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs_demux[REG ## _EL1_DEMUX_IDX][INDEX]; \ + }) + +#define COPY_IDREG_DEMUX(ISAR, REG, FROM_INDEX, TO_INDEX) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs_demux[REG ## _EL1_DEMUX_IDX][TO_INDEX] =3D \ + i_->idregs_demux[REG ## _EL1_DEMUX_IDX][FROM_INDEX]; \ + }) + /** * ARMCPU: * @env: #CPUARMState @@ -1084,6 +1103,7 @@ struct ArchCPU { uint32_t dbgdevid1; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; + uint64_t idregs_demux[NUM_ID_DEMUX_IDX][ID_DEMUX_ARRAYLEN]; } isar; uint64_t midr; uint32_t revidr; --=20 2.52.0