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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1770211972; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vR2fBcORYdmt1YPsf7yFFS0kUNSb0702Te0uJ25zGIo=; b=Jno1SCmo2e8MtkQZegN/PsE8AxhyxHWLKfAcUgZItS5qTz4WJ7YXsNTqggN0EQu+s/MaNj LIeyrMAfyrLPoj6MwpN8F7htpq+EroTSvbzRIGEqPqHhS5OzIle94UnshJ6ez0tQE8GYKf 3Wmjk2SyzQ2dMdmOAYga4MiryIovP9w= X-MC-Unique: d7zoEFN8NiGZbBCnsVrEWQ-1 X-Mimecast-MFC-AGG-ID: d7zoEFN8NiGZbBCnsVrEWQ_1770211970 From: Cornelia Huck To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Eric Auger , Sebastian Ott , Jonathan Cameron , Alireza Sanaee , Cornelia Huck Subject: [PATCH v2 1/3] arm: handle demuxed ID registers Date: Wed, 4 Feb 2026 14:32:27 +0100 Message-ID: <20260204133229.297061-2-cohuck@redhat.com> In-Reply-To: <20260204133229.297061-1-cohuck@redhat.com> References: <20260204133229.297061-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" For some registers, we do not have a single ID register, but actually an array of values (e.g. CCSIDR_EL1, where the actual value is determined by whatever CSSELR_EL1 points to.) If we want to avoid using a different way to handle registers like that for every instance, we should provide some kind of infrastructure. Therefore, add accessors {GET,SET}_IDREG_DEMUX that are similar to the accessors we already use for regular ID registers. Tested-by: Alireza Sanaee Reviewed-by: Sebastian Ott Signed-off-by: Cornelia Huck --- target/arm/cpu-sysregs.h | 13 +++++++++++++ target/arm/cpu.h | 20 ++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h index 7877a3b06a8e..911f54bc8a4f 100644 --- a/target/arm/cpu-sysregs.h +++ b/target/arm/cpu-sysregs.h @@ -35,6 +35,19 @@ typedef enum ARMSysRegs { =20 #undef DEF =20 +/* ID registers that vary based upon another register */ +typedef enum ARMIDRegisterDemuxIdx { + NUM_ID_DEMUX_IDX, +} ARMIDRegisterDemuxIdx; + +/* + * Number of register variants per demuxed register, trying to accommodate + * possible use cases. + * CCSIDR_EL1 currently needs 7*2, could be 7 more with FEAT_MTE2, in which + * case we would need to bump this number. + */ +#define ID_DEMUX_ARRAYLEN 16 + extern const uint32_t id_register_sysreg[NUM_ID_IDX]; =20 int get_sysreg_idx(ARMSysRegs sysreg); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 21fee5e840b7..f9d51c0fc187 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -906,6 +906,25 @@ typedef struct { i_->idregs[REG ## _EL1_IDX]; \ }) =20 +#define SET_IDREG_DEMUX(ISAR, REG, INDEX, VALUE) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs_demux[REG ## _EL1_DEMUX_IDX][INDEX] =3D VALUE; \ + }) + +#define GET_IDREG_DEMUX(ISAR, REG, INDEX) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs_demux[REG ## _EL1_DEMUX_IDX][INDEX]; \ + }) + +#define COPY_IDREG_DEMUX(ISAR, REG, FROM_INDEX, TO_INDEX) \ + ({ \ + ARMISARegisters *i_ =3D (ISAR); \ + i_->idregs_demux[REG ## _EL1_DEMUX_IDX][TO_INDEX] =3D \ + i_->idregs_demux[REG ## _EL1_DEMUX_IDX][FROM_INDEX]; \ + }) + /** * ARMCPU: * @env: #CPUARMState @@ -1084,6 +1103,7 @@ struct ArchCPU { uint32_t dbgdevid1; uint64_t reset_pmcr_el0; uint64_t idregs[NUM_ID_IDX]; + uint64_t idregs_demux[NUM_ID_DEMUX_IDX][ID_DEMUX_ARRAYLEN]; } isar; uint64_t midr; uint32_t revidr; --=20 2.52.0 From nobody Sat Feb 7 05:49:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=ZjSAeh4YPvHvfvlNNtZXcaM5jvXJlBHLzCZadYw8D0I=; b=Z9Kun0WbOjRe4zF1GrAYTPTzLVbffIYvtxjn6KqdUtt7qtUH/LZcHytcY6SGmAoqKbrF0A vWJvBjzqiGm6zJ3XATIw+4ULXpBCWasUc5gpX2DU6dHLcnMTOk3T96RRInwNYCrmJwCiK2 7TvULODSSXOV4DoVIdhsyNBNttNpZac= X-MC-Unique: ixHyDq8iOVSNlxlb9UJt6g-1 X-Mimecast-MFC-AGG-ID: ixHyDq8iOVSNlxlb9UJt6g_1770211972 From: Cornelia Huck To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Eric Auger , Sebastian Ott , Jonathan Cameron , Alireza Sanaee , Cornelia Huck Subject: [PATCH v2 2/3] arm: handle CCSIDR_EL1 as a demuxed register Date: Wed, 4 Feb 2026 14:32:28 +0100 Message-ID: <20260204133229.297061-3-cohuck@redhat.com> In-Reply-To: <20260204133229.297061-1-cohuck@redhat.com> References: <20260204133229.297061-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1770212030086154100 Content-Type: text/plain; charset="utf-8" Move handling of CCSIDR_EL1 over to the new *_IDREG_DEMUX infrastructure. Tested-by: Alireza Sanaee Reviewed-by: Sebastian Ott Signed-off-by: Cornelia Huck --- hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu-sysregs.h | 1 + target/arm/cpu-sysregs.h.inc | 1 + target/arm/cpu.h | 6 ---- target/arm/cpu64.c | 12 ++++---- target/arm/helper.c | 2 +- target/arm/tcg/cpu32.c | 32 +++++++++---------- target/arm/tcg/cpu64.c | 60 ++++++++++++++++++------------------ 8 files changed, 56 insertions(+), 60 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 28b34e99446f..271d16692910 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1337,7 +1337,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) case 0xd80: /* CSSIDR */ { int idx =3D cpu->env.v7m.csselr[attrs.secure] & R_V7M_CSSELR_INDEX= _MASK; - return cpu->ccsidr[idx]; + return GET_IDREG_DEMUX(&cpu->isar, CCSIDR, idx); } case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h index 911f54bc8a4f..ec04174d4a99 100644 --- a/target/arm/cpu-sysregs.h +++ b/target/arm/cpu-sysregs.h @@ -37,6 +37,7 @@ typedef enum ARMSysRegs { =20 /* ID registers that vary based upon another register */ typedef enum ARMIDRegisterDemuxIdx { + CCSIDR_EL1_DEMUX_IDX, NUM_ID_DEMUX_IDX, } ARMIDRegisterDemuxIdx; =20 diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 3d1ed40f0439..ed466ffb7318 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -37,6 +37,7 @@ DEF(MVFR2_EL1, 3, 0, 0, 3, 2) DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) DEF(ID_DFR1_EL1, 3, 0, 0, 3, 5) DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) +DEF(CCSIDR_EL1, 3, 1, 0, 0, 0) DEF(CLIDR_EL1, 3, 1, 0, 0, 1) DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) DEF(CTR_EL0, 3, 3, 0, 0, 1) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f9d51c0fc187..b26922ea4298 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1113,10 +1113,6 @@ struct ArchCPU { uint64_t pmceid0; uint64_t pmceid1; uint64_t mp_affinity; /* MP ID without feature bits */ - /* The elements of this array are the CCSIDR values for each cache, - * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. - */ - uint64_t ccsidr[16]; uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; @@ -2107,8 +2103,6 @@ FIELD(MFAR, FPA, 12, 40) FIELD(MFAR, NSE, 62, 1) FIELD(MFAR, NS, 63, 1) =20 -QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); - /* If adding a feature bit which corresponds to a Linux ELF * HWCAP bit, remember to update the feature-bit-to-hwcap * mapping in linux-user/elfload.c:get_elf_hwcap(). diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4dfc03973e17..798769a42bd3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -684,11 +684,11 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.reset_pmcr_el0 =3D 0x41013000; SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 32 * KiB, 7)); /* 48KB L1 icache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, = 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, = 64, 48 * KiB, 2)); /* 2048KB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16,= 64, 2 * MiB, 7)); set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; @@ -746,11 +746,11 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.reset_pmcr_el0 =3D 0x41033000; SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 32 * KiB, 7)); /* 32KB L1 icache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, = 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, = 64, 32 * KiB, 2)); /* 1024KB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16,= 64, 1 * MiB, 7)); set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; diff --git a/target/arm/helper.c b/target/arm/helper.c index e86ceb130ce9..f1c771461589 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -875,7 +875,7 @@ static uint64_t ccsidr_read(CPUARMState *env, const ARM= CPRegInfo *ri) uint32_t index =3D A32_BANKED_REG_GET(env, csselr, ri->secure & ARM_CP_SECSTATE_S); =20 - return cpu->ccsidr[index]; + return GET_IDREG_DEMUX(&cpu->isar, CCSIDR, index); } =20 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 0b0bc96bac22..75b627f609f5 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -372,9 +372,9 @@ static void cortex_a8_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x15141000; SET_IDREG(isar, CLIDR, (1 << 27) | (2 << 24) | 3); - cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ - cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ - cpu->ccsidr[2] =3D 0xf0000000; /* No L2 icache. */ + SET_IDREG_DEMUX(isar, CCSIDR, 0, 0xe007e01a); /* 16k L1 dcache. */ + SET_IDREG_DEMUX(isar, CCSIDR, 1, 0x2007e01a); /* 16k L1 icache. */ + SET_IDREG_DEMUX(isar, CCSIDR, 2, 0xf0000000); /* No L2 icache. */ cpu->reset_auxcr =3D 2; cpu->isar.reset_pmcr_el0 =3D 0x41002000; define_arm_cp_regs(cpu, cortexa8_cp_reginfo); @@ -448,8 +448,8 @@ static void cortex_a9_initfn(Object *obj) SET_IDREG(isar, ID_ISAR4, 0x00111142); cpu->isar.dbgdidr =3D 0x35141000; SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 3); - cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ - cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ + SET_IDREG_DEMUX(isar, CCSIDR, 0, 0xe00fe019); /* 16k L1 dcache. */ + SET_IDREG_DEMUX(isar, CCSIDR, 1, 0x200fe019); /* 16k L1 icache. */ cpu->isar.reset_pmcr_el0 =3D 0x41093000; define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } @@ -520,9 +520,9 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x1; SET_IDREG(isar, CLIDR, 0x0a200023); - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + SET_IDREG_DEMUX(isar, CCSIDR, 0, 0x701fe00a); /* 32K L1 dcache */ + SET_IDREG_DEMUX(isar, CCSIDR, 1, 0x201fe00a); /* 32K L1 icache */ + SET_IDREG_DEMUX(isar, CCSIDR, 2, 0x711fe07a); /* 4096K L2 unified cach= e */ cpu->isar.reset_pmcr_el0 =3D 0x41072000; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ } @@ -568,9 +568,9 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.dbgdevid =3D 0x01110f13; cpu->isar.dbgdevid1 =3D 0x0; SET_IDREG(isar, CLIDR, 0x0a200023); - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + SET_IDREG_DEMUX(isar, CCSIDR, 0, 0x701fe00a); /* 32K L1 dcache */ + SET_IDREG_DEMUX(isar, CCSIDR, 1, 0x201fe00a); /* 32K L1 icache */ + SET_IDREG_DEMUX(isar, CCSIDR, 2, 0x711fe07a); /* 4096K L2 unified cach= e */ cpu->isar.reset_pmcr_el0 =3D 0x410F3000; define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } @@ -759,8 +759,8 @@ static void cortex_r52_initfn(Object *obj) SET_IDREG(isar, ID_ISAR5, 0x00010001); cpu->isar.dbgdidr =3D 0x77168000; SET_IDREG(isar, CLIDR, (1 << 27) | (1 << 24) | 0x3); - cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ + SET_IDREG_DEMUX(isar, CCSIDR, 0, 0x700fe01a); /* 32KB L1 dcache */ + SET_IDREG_DEMUX(isar, CCSIDR, 1, 0x201fe00a); /* 32KB L1 icache */ =20 cpu->pmsav7_dregion =3D 16; cpu->pmsav8r_hdregion =3D 16; @@ -853,9 +853,9 @@ static void arm_max_initfn(Object *obj) SET_IDREG(isar, ID_ISAR6, 0); cpu->isar.reset_pmcr_el0 =3D 0x41013000; SET_IDREG(isar, CLIDR, 0x0a200023); - cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ - cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + SET_IDREG_DEMUX(isar, CCSIDR, 0, 0x701fe00a); /* 32KB L1 dcache */ + SET_IDREG_DEMUX(isar, CCSIDR, 1, 0x201fe012); /* 48KB L1 icache */ + SET_IDREG_DEMUX(isar, CCSIDR, 2, 0x70ffe07a); /* 2048KB L2 cache */ define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 aa32_max_features(cpu); diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index fa80e48d2beb..3634af5dabf5 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -82,11 +82,11 @@ static void aarch64_a35_initfn(Object *obj) =20 /* From B2.29 Cache ID registers */ /* 32KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 32 * KiB, 7)); /* 32KB L1 icache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 32 * KiB, 2)); /* 512KB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB= , 7); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16,= 64, 512 * KiB, 7)); =20 /* From B3.5 VGIC Type register */ cpu->gic_num_lrs =3D 4; @@ -250,11 +250,11 @@ static void aarch64_a55_initfn(Object *obj) =20 /* From B2.23 CCSIDR_EL1 */ /* 32KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 32 * KiB, 7)); /* 32KB L1 icache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 32 * KiB, 2)); /* 512KB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB= , 7); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16,= 64, 512 * KiB, 7)); =20 /* From B2.96 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -320,11 +320,11 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.reset_pmcr_el0 =3D 0x41023000; SET_IDREG(isar, CLIDR, 0x0a200023); /* 32KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 32 * KiB, 7)); /* 48KB L1 dcache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, = 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, = 64, 48 * KiB, 2)); /* 1MB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16,= 64, 1 * MiB, 7)); set_dczid_bs(cpu, 4); /* 64 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; @@ -383,11 +383,11 @@ static void aarch64_a76_initfn(Object *obj) =20 /* From B2.18 CCSIDR_EL1 */ /* 64KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 64 * KiB, 2)); /* 512KB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB,= 7); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, = 64, 512 * KiB, 7)); =20 /* From B2.93 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -455,11 +455,11 @@ static void aarch64_a78ae_initfn(Object *obj) =20 /* From 3.2.33 CCSIDR_EL1 */ /* 64KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 64 * KiB, 2)); /* 512KB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB,= 7); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, = 64, 512 * KiB, 7)); =20 /* From 3.2.118 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -512,11 +512,11 @@ static void aarch64_a64fx_initfn(Object *obj) SET_IDREG(isar, ID_AA64ZFR0, 0x0000000000000000); SET_IDREG(isar, CLIDR, 0x0000000080000023); /* 64KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 256, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB,= 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 256, 64 * KiB, 2)); /* 8MB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB,= 7); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 16,= 256, 8 * MiB, 7)); set_dczid_bs(cpu, 6); /* 256 bytes */ cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; @@ -704,11 +704,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj) =20 /* From B2.23 CCSIDR_EL1 */ /* 64KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 64 * KiB, 7)); /* 64KB L1 icache */ - cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + SET_IDREG_DEMUX(isar, CCSIDR, 1, make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, = 64, 64 * KiB, 2)); /* 1MB L2 dcache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7= ); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, = 64, 1 * MiB, 7)); =20 /* From B2.98 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -792,11 +792,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj) * L3: No L3 (this matches the CLIDR_EL1 value). */ /* 64KB L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0= ); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 6= 4, 64 * KiB, 0)); /* 64KB L1 icache */ - cpu->ccsidr[1] =3D cpu->ccsidr[0]; + COPY_IDREG_DEMUX(isar, CCSIDR, 0, 1); /* 1MB L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 6= 4, 1 * MiB, 0)); =20 /* From 3.2.115 SCTLR_EL3 */ cpu->reset_sctlr =3D 0x30c50838; @@ -1034,11 +1034,11 @@ static void aarch64_a710_initfn(Object *obj) * L2: 8-way set associative 64 byte line size, total either 256K or 5= 12K. */ /* L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0= ); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 6= 4, 64 * KiB, 0)); /* L1 icache */ - cpu->ccsidr[1] =3D cpu->ccsidr[0]; + COPY_IDREG_DEMUX(isar, CCSIDR, 0, 1); /* L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, = 0); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 6= 4, 512 * KiB, 0)); =20 /* FIXME: Not documented -- copied from neoverse-v1 */ cpu->reset_sctlr =3D 0x30c50838; @@ -1136,11 +1136,11 @@ static void aarch64_neoverse_n2_initfn(Object *obj) * L2: 8-way set associative 64 byte line size, total either 512K or 1= 024K. */ /* L1 dcache */ - cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0= ); + SET_IDREG_DEMUX(isar, CCSIDR, 0, make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 6= 4, 64 * KiB, 0)); /* L1 icache */ - cpu->ccsidr[1] =3D cpu->ccsidr[0]; + COPY_IDREG_DEMUX(isar, CCSIDR, 0, 1); /* L2 cache */ - cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, = 0); + SET_IDREG_DEMUX(isar, CCSIDR, 2, make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 6= 4, 512 * KiB, 0)); /* FIXME: Not documented -- copied from neoverse-v1 */ cpu->reset_sctlr =3D 0x30c50838; =20 --=20 2.52.0 From nobody Sat Feb 7 05:49:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=E+syS+GxUclP8EdbREjab5UTXYUS0sMyMOX4XUbJwMA=; b=flCm5EFFHXEua1aLaxtYPnZ7LKDaWi1HIhh+L05MpLu/rYRYHJLh4t0m49llrh8HvwSNV6 7CIZXlDqY+KyVmP6Eik6v/AUikX399Zpk5oX0RTCPGb6rXMv/tdituis3n8b/6HEGzAuCI mhtmIWyCKHeUibXk57SJkMmwOpu0ttc= X-MC-Unique: MD2oCXt4O7mJ1j5dv-XLhA-1 X-Mimecast-MFC-AGG-ID: MD2oCXt4O7mJ1j5dv-XLhA_1770211975 From: Cornelia Huck To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Eric Auger , Sebastian Ott , Jonathan Cameron , Alireza Sanaee , Cornelia Huck Subject: [PATCH v2 3/3] arm/kvm: get demuxed ID registers from kvm Date: Wed, 4 Feb 2026 14:32:29 +0100 Message-ID: <20260204133229.297061-4-cohuck@redhat.com> In-Reply-To: <20260204133229.297061-1-cohuck@redhat.com> References: <20260204133229.297061-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1770212007085158500 Content-Type: text/plain; charset="utf-8" We now have the infrastructure in place to get and save demuxed ID registers from kvm. Use it to get the values that kvm emulates for CCSIDR_EL1. Tested-by: Alireza Sanaee Reviewed-by: Sebastian Ott Signed-off-by: Cornelia Huck --- target/arm/kvm.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 0828e8b87bac..9ed51969f075 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -243,6 +243,33 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures= *ahcf, return ret; } =20 +static int get_host_cpu_reg_demux(int fd, ARMHostCPUFeatures *ahcf, + ARMIDRegisterIdx index, int subindex) +{ + + struct kvm_one_reg one_reg =3D { + .id =3D KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX, + }; + ARMIDRegisterDemuxIdx demux_index; + + switch (index) { + case CCSIDR_EL1_IDX: + if (subindex < 14) { + one_reg.id |=3D KVM_REG_ARM_DEMUX_ID_CCSIDR | subindex; + } else { + return -EINVAL; + } + demux_index =3D CCSIDR_EL1_DEMUX_IDX; + break; + default: + return -EINVAL; + } + one_reg.addr =3D (uintptr_t)&ahcf->isar.idregs_demux[demux_index][subi= ndex]; + + return ioctl(fd, KVM_GET_ONE_REG, &one_reg); + +} + static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and @@ -256,6 +283,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFea= tures *ahcf) bool pmu_supported =3D false; uint64_t features =3D 0; int err; + int i; =20 /* * target =3D -1 informs kvm_arm_create_scratch_host_vcpu() @@ -416,6 +444,11 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFe= atures *ahcf) */ err |=3D get_host_cpu_reg(fd, ahcf, ID_AA64ZFR0_EL1_IDX); } + /* grab demuxed registers */ + for (i =3D 0; i < 14; i++) { + /* KVM only allows 0..13 */ + err |=3D get_host_cpu_reg_demux(fd, ahcf, CCSIDR_EL1_IDX, i); + } } =20 kvm_arm_destroy_scratch_host_vcpu(fdarray); --=20 2.52.0