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Wed, 04 Feb 2026 05:13:58 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell , Pierrick Bouvier , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PATCH v2] target/arm: implement FEAT_E2H0 Date: Wed, 4 Feb 2026 13:13:53 +0000 Message-ID: <20260204131353.2977855-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770210866656158500 FEAT_E2H0 is a formalisation of the existing behaviour of HCR_EL2.E2H being programmable to switch between EL2 host mode and the "traditional" nVHE EL2 mode. This implies at some point we might want to model CPUs without FEAT_E2H0 which will always have EL2 host mode enabled. There are two values to represent no E2H0 systems of which 0b1110 will make HCR_EL2.NV1 RES0 for FEAT_NV systems. For FEAT_NV2 the NV1 bit is always valid. Message-ID: <20260130181648.628364-1-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Mohamed Mediouni --- v2 - new helper and properly handling NV1 --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 12 ++++++++++++ target/arm/helper.c | 16 +++++++++++++--- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index e0d5f9886e1..7787691853e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -54,6 +54,7 @@ the following architecture extensions: - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) +- FEAT_E2H0 (Programming of HCR_EL2.E2H) - FEAT_EBF16 (AArch64 Extended BFloat16 instructions) - FEAT_ECV (Enhanced Counter Virtualization) - FEAT_EL0 (Support for execution at EL0) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e0b7a45b7bd..78ff761ae06 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -347,6 +347,7 @@ FIELD(ID_AA64MMFR3, ADERR, 56, 4) FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) =20 FIELD(ID_AA64MMFR4, ASID2, 8, 4) +FIELD(ID_AA64MMFR4, E2H0, 24, 4) =20 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) @@ -1378,6 +1379,17 @@ static inline bool isar_feature_aa64_asid2(const ARM= ISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) !=3D 0; } =20 +static inline bool isar_feature_aa64_e2h0(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, E2H0) =3D=3D 0; +} + +static inline bool isar_feature_aa64_noe2h0_and_nv1_res0(const ARMISARegis= ters *id) +{ + /* 0b1110 is not permitted unless we have FEAT_NV */ + return isar_feature_aa64_nv(id) && FIELD_EX64_IDREG(id, ID_AA64MMFR4, = E2H0) =3D=3D 0b1110; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 390ea32c218..c3f4054a0b0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3776,7 +3776,8 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) } =20 if (arm_feature(env, ARM_FEATURE_AARCH64)) { - if (cpu_isar_feature(aa64_vh, cpu)) { + if (cpu_isar_feature(aa64_vh, cpu) && + cpu_isar_feature(aa64_e2h0, cpu)) { valid_mask |=3D HCR_E2H; } if (cpu_isar_feature(aa64_ras, cpu)) { @@ -3801,10 +3802,13 @@ static void do_hcr_write(CPUARMState *env, uint64_t= value, uint64_t valid_mask) valid_mask |=3D HCR_GPF; } if (cpu_isar_feature(aa64_nv, cpu)) { - valid_mask |=3D HCR_NV | HCR_NV1 | HCR_AT; + valid_mask |=3D HCR_NV | HCR_AT; + if (!cpu_isar_feature(aa64_noe2h0_and_nv1_res0, cpu)) { + valid_mask |=3D HCR_NV1; + } } if (cpu_isar_feature(aa64_nv2, cpu)) { - valid_mask |=3D HCR_NV2; + valid_mask |=3D HCR_NV1 | HCR_NV2; } } =20 @@ -3823,6 +3827,12 @@ static void do_hcr_write(CPUARMState *env, uint64_t = value, uint64_t valid_mask) value |=3D HCR_RW; } =20 + /* Strictly E2H is RES1 unless FEAT_E2H0 relaxes the requirement */ + if (arm_feature(env, ARM_FEATURE_AARCH64) && + !cpu_isar_feature(aa64_e2h0, cpu)) { + value |=3D HCR_E2H; + } + /* * These bits change the MMU setup: * HCR_VM enables stage 2 translation --=20 2.47.3