From nobody Sat Feb 7 07:11:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770207371; cv=none; d=zohomail.com; s=zohoarc; b=CJn06IiXn6Y+6YyIKqwYwCZq8873N1sTkXohoTtCGKxiK9eN66rZQ0zC90vlzTEqnvf34TlIB9RLRPPAWcUeHcrgriyu3lVlpbLguOEyMat0Od2/k6OIZP/diNEcOKbX+Sm7nhRhkQ5d++KjHBM5lC8y5DpufDJnB6GGK1aASVI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770207371; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=mio0cWlqyYfFr6QxbaopJDSJ+1HZI5kFWMdVqrh74+c=; b=hL+iuXOkyrLcT8N2XDLfWWgXX/SFVQv9ysdi6Me3sYafakm/kZYgavvMimiM0bmLuoEtNfdTMUSY1c3waA16KUYPrROGEQqC95e1ri/RER+XNNJBamAwEJ/iaS3f8PV0dvUvl7GHFS3MHSaC7wxXo0P0HwtMhF3HNQoVHMZZCY0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770207371770576.6271333287036; Wed, 4 Feb 2026 04:16:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnbnO-0000Rz-8N; Wed, 04 Feb 2026 07:15:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnbnK-0000ME-BY for qemu-devel@nongnu.org; Wed, 04 Feb 2026 07:15:42 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnbnH-00089K-Dn for qemu-devel@nongnu.org; Wed, 04 Feb 2026 07:15:42 -0500 Received: from mail.maildlp.com (unknown [172.18.224.107]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4f5fRc4zf4zHnGgv; Wed, 4 Feb 2026 20:14:36 +0800 (CST) Received: from dubpeml500005.china.huawei.com (unknown [7.214.145.207]) by mail.maildlp.com (Postfix) with ESMTPS id F216040584; Wed, 4 Feb 2026 20:15:37 +0800 (CST) Received: from SecurePC-101-06.huawei.com (10.122.19.247) by dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 4 Feb 2026 12:15:36 +0000 To: Michael Tsirkin , , Davidlohr Bueso CC: , , Ravi Shankar , Marcel Apfelbaum , Markus Armbruster , Michael Roth Subject: [PATCH qemu v6 6/7] hw/cxl: Support type3 HDM-DB Date: Wed, 4 Feb 2026 12:12:14 +0000 Message-ID: <20260204121215.68897-7-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260204121215.68897-1-Jonathan.Cameron@huawei.com> References: <20260204121215.68897-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml500012.china.huawei.com (7.191.174.4) To dubpeml500005.china.huawei.com (7.214.145.207) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770207372548158500 Content-Type: text/plain; charset="utf-8" From: Davidlohr Bueso Add basic plumbing for memory expander devices that support Back Invalidation. This introduces a 'hdm-db=3Don|off' parameter and exposes the relevant BI RT/Decoder component cachemem registers. Some noteworthy properties: - Devices require enabling Flit mode across the CXL topology. - Explicit BI-ID commit is required. - HDM decoder support both host and dev coherency models. Tested-by: Dongjoo Seo Signed-off-by: Davidlohr Bueso Signed-off-by: Jonathan Cameron --- v6: Initialize type variable to avoid a false compiler warning from some versions of gcc. (Michael Tsirkin) --- docs/system/devices/cxl.rst | 23 +++++ include/hw/cxl/cxl_component.h | 54 ++++++++++- include/hw/cxl/cxl_device.h | 3 + hw/cxl/cxl-component-utils.c | 142 ++++++++++++++++++++++++++-- hw/mem/cxl_type3.c | 9 +- hw/pci-bridge/cxl_downstream.c | 2 +- hw/pci-bridge/cxl_root_port.c | 3 +- hw/pci-bridge/cxl_upstream.c | 2 +- hw/pci-bridge/pci_expander_bridge.c | 2 +- 9 files changed, 225 insertions(+), 15 deletions(-) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index ca15a0da1c1d..9d0771cdfd73 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -384,6 +384,29 @@ An example of 4 devices below a switch suitable for 1,= 2 or 4 way interleave:: -device cxl-type3,bus=3Dswport3,persistent-memdev=3Dcxl-mem3,lsa=3Dcxl-l= sa3,id=3Dcxl-pmem3,sn=3D0x4 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k =20 +An example of 4 type3 devices with volatile memory below a switch. Two of = the devices +use HDM-DB for coherence, which requires operating in Flit mode:: + + qemu-system-x86_64 -M q35,cxl=3Don -m 4G,maxmem=3D8G,slots=3D8 -smp 4 \ + ... + -object memory-backend-ram,id=3Dcxl-mem0,share=3Don,size=3D256M \ + -object memory-backend-ram,id=3Dcxl-mem1,share=3Don,size=3D256M \ + -object memory-backend-ram,id=3Dcxl-mem2,share=3Don,size=3D256M \ + -object memory-backend-ram,id=3Dcxl-mem3,share=3Don,size=3D256M \ + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port0,chassis=3D0,slot=3D0= \ + -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Droot_port1,chassis=3D0,slot=3D1= \ + -device cxl-upstream,bus=3Droot_port0,id=3Dus0,x-256b-flit=3Don \ + -device cxl-downstream,port=3D0,bus=3Dus0,id=3Dswport0,chassis=3D0,slot= =3D4 \ + -device cxl-type3,bus=3Dswport0,volatile-memdev=3Dcxl-mem0,id=3Dcxl-mem0= ,sn=3D0x1,x-256b-flit=3Don,hdm-db=3Don \ + -device cxl-downstream,port=3D1,bus=3Dus0,id=3Dswport1,chassis=3D0,slot= =3D5 \ + -device cxl-type3,bus=3Dswport1,volatile-memdev=3Dcxl-mem1,id=3Dcxl-mem1= ,sn=3D0x2,x-256b-flit=3Don,hdm-db=3Don \ + -device cxl-downstream,port=3D2,bus=3Dus0,id=3Dswport2,chassis=3D0,slot= =3D6 \ + -device cxl-type3,bus=3Dswport2,volatile-memdev=3Dcxl-mem2,id=3Dcxl-mem2= ,sn=3D0x3 \ + -device cxl-downstream,port=3D3,bus=3Dus0,id=3Dswport3,chassis=3D0,slot= =3D7 \ + -device cxl-type3,bus=3Dswport3,volatile-memdev=3Dcxl-mem3,id=3Dcxl-mem3= ,sn=3D0x4 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k + A simple arm/virt example featuring a single direct connected CXL Type 3 Volatile Memory device:: =20 diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 1f167d3ef79b..ffc82202206c 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -67,6 +67,8 @@ CXLx_CAPABILITY_HEADER(LINK, 2) CXLx_CAPABILITY_HEADER(HDM, 3) CXLx_CAPABILITY_HEADER(EXTSEC, 4) CXLx_CAPABILITY_HEADER(SNOOP, 5) +CXLx_CAPABILITY_HEADER(BI_RT, 6) +CXLx_CAPABILITY_HEADER(BI_DECODER, 7) =20 /* * Capability structures contain the actual registers that the CXL compone= nt @@ -211,10 +213,55 @@ HDM_DECODER_INIT(3); (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) #define CXL_SNOOP_REGISTERS_SIZE 0x8 =20 -QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + - CXL_SNOOP_REGISTERS_SIZE) >=3D 0x1000, +#define CXL_BI_RT_CAP_VERSION 1 +#define CXL_BI_RT_REGISTERS_OFFSET \ + (CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) +#define CXL_BI_RT_REGISTERS_SIZE 0xC + +REG32(CXL_BI_RT_CAPABILITY, CXL_BI_RT_REGISTERS_OFFSET) + FIELD(CXL_BI_RT_CAPABILITY, EXPLICIT_COMMIT, 0, 1) +REG32(CXL_BI_RT_CTRL, CXL_BI_RT_REGISTERS_OFFSET + 0x4) + FIELD(CXL_BI_RT_CTRL, COMMIT, 0, 1) +REG32(CXL_BI_RT_STATUS, CXL_BI_RT_REGISTERS_OFFSET + 0x8) + FIELD(CXL_BI_RT_STATUS, COMMITTED, 0, 1) + FIELD(CXL_BI_RT_STATUS, ERR_NOT_COMMITTED, 1, 1) + FIELD(CXL_BI_RT_STATUS, COMMIT_TMO_SCALE, 8, 4) + FIELD(CXL_BI_RT_STATUS, COMMIT_TMO_BASE, 12, 4) + +/* CXL r3.2 8.2.4.27 - CXL BI Decoder Capability Structure */ +#define CXL_BI_DECODER_CAP_VERSION 1 +#define CXL_BI_DECODER_REGISTERS_OFFSET \ + (CXL_BI_RT_REGISTERS_OFFSET + CXL_BI_RT_REGISTERS_SIZE) +#define CXL_BI_DECODER_REGISTERS_SIZE 0xC + +REG32(CXL_BI_DECODER_CAPABILITY, CXL_BI_DECODER_REGISTERS_OFFSET) + FIELD(CXL_BI_DECODER_CAPABILITY, HDM_D, 0, 1) + FIELD(CXL_BI_DECODER_CAPABILITY, EXPLICIT_COMMIT, 1, 1) +REG32(CXL_BI_DECODER_CTRL, CXL_BI_DECODER_REGISTERS_OFFSET + 0x4) + FIELD(CXL_BI_DECODER_CTRL, BI_FW, 0, 1) + FIELD(CXL_BI_DECODER_CTRL, BI_ENABLE, 1, 1) + FIELD(CXL_BI_DECODER_CTRL, COMMIT, 2, 1) +REG32(CXL_BI_DECODER_STATUS, CXL_BI_DECODER_REGISTERS_OFFSET + 0x8) + FIELD(CXL_BI_DECODER_STATUS, COMMITTED, 0, 1) + FIELD(CXL_BI_DECODER_STATUS, ERR_NOT_COMMITTED, 1, 1) + FIELD(CXL_BI_DECODER_STATUS, COMMIT_TMO_SCALE, 8, 4) + FIELD(CXL_BI_DECODER_STATUS, COMMIT_TMO_BASE, 12, 4) + +QEMU_BUILD_BUG_MSG((CXL_BI_DECODER_REGISTERS_OFFSET + + CXL_BI_DECODER_REGISTERS_SIZE) >=3D 0x1000, "No space for registers"); =20 +/* track BI explicit commit handling for route table and decoder */ +enum { + CXL_BISTATE_RT =3D 0, + CXL_BISTATE_DECODER, + CXL_BISTATE_MAX +}; + +typedef struct bi_state { + uint64_t last_commit; /* last 0->1 transition */ +} BIState; + typedef struct component_registers { /* * Main memory region to be registered with QEMU core. @@ -259,6 +306,7 @@ typedef struct cxl_component { }; =20 CDATObject cdat; + BIState bi_state[CXL_BISTATE_MAX]; } CXLComponentState; =20 void cxl_component_register_block_init(Object *obj, @@ -266,7 +314,7 @@ void cxl_component_register_block_init(Object *obj, const char *type); void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, - enum reg_type type); + enum reg_type type, bool bi); =20 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, enum reg_type cxl_dev_type, uint16_t lengt= h, diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 7d9236db8c85..393f3122173b 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -770,6 +770,9 @@ struct CXLType3Dev { CXLMemSparingReadAttrs rank_sparing_attrs; CXLMemSparingWriteAttrs rank_sparing_wr_attrs; =20 + /* BI flows */ + bool hdmdb; + struct dynamic_capacity { HostMemoryBackend *host_dc; AddressSpace host_dc_as; diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 91770f103a85..a7d36e1128c2 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -71,10 +71,40 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hw= addr offset, case 4: if (cregs->special_ops && cregs->special_ops->read) { return cregs->special_ops->read(cxl_cstate, offset, 4); - } else { - QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) !=3D 4); - return cregs->cache_mem_registers[offset / 4]; } + + QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) !=3D 4); + + if (offset =3D=3D A_CXL_BI_RT_STATUS || + offset =3D=3D A_CXL_BI_DECODER_STATUS) { + int type; + uint64_t started; + + type =3D (offset =3D=3D A_CXL_BI_RT_STATUS) ? + CXL_BISTATE_RT : CXL_BISTATE_DECODER; + started =3D cxl_cstate->bi_state[type].last_commit; + + if (started) { + uint32_t *cache_mem =3D cregs->cache_mem_registers; + uint32_t val =3D cache_mem[offset / 4]; + uint64_t now; + int set; + + now =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); + /* arbitrary 100 ms to do the commit */ + set =3D !!(now >=3D started + 100); + + if (offset =3D=3D A_CXL_BI_RT_STATUS) { + val =3D FIELD_DP32(val, CXL_BI_RT_STATUS, COMMITTED, s= et); + } else { + val =3D FIELD_DP32(val, CXL_BI_DECODER_STATUS, COMMITT= ED, + set); + } + stl_le_p((uint8_t *)cache_mem + offset, val); + } + } + + return cregs->cache_mem_registers[offset / 4]; case 8: qemu_log_mask(LOG_UNIMP, "CXL 8 byte cache mem registers not implemented\n"); @@ -118,6 +148,47 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cs= tate, hwaddr offset, stl_le_p((uint8_t *)cache_mem + offset, value); } =20 +static void bi_handler(CXLComponentState *cxl_cstate, hwaddr offset, + uint32_t value) +{ + ComponentRegisters *cregs =3D &cxl_cstate->crb; + uint32_t sts, *cache_mem =3D cregs->cache_mem_registers; + bool to_commit =3D false; + int type =3D 0; /* Unused value - work around for compiler warning */ + + switch (offset) { + case A_CXL_BI_RT_CTRL: + to_commit =3D FIELD_EX32(value, CXL_BI_RT_CTRL, COMMIT); + if (to_commit) { + sts =3D cxl_cache_mem_read_reg(cxl_cstate, + R_CXL_BI_RT_STATUS, 4); + sts =3D FIELD_DP32(sts, CXL_BI_RT_STATUS, COMMITTED, 0); + stl_le_p((uint8_t *)cache_mem + R_CXL_BI_RT_STATUS, sts); + type =3D CXL_BISTATE_RT; + } + break; + case A_CXL_BI_DECODER_CTRL: + to_commit =3D FIELD_EX32(value, CXL_BI_DECODER_CTRL, COMMIT); + if (to_commit) { + sts =3D cxl_cache_mem_read_reg(cxl_cstate, + R_CXL_BI_DECODER_STATUS, 4); + sts =3D FIELD_DP32(sts, CXL_BI_DECODER_STATUS, COMMITTED, 0); + stl_le_p((uint8_t *)cache_mem + R_CXL_BI_DECODER_STATUS, sts); + type =3D CXL_BISTATE_DECODER; + } + break; + default: + break; + } + + if (to_commit) { + cxl_cstate->bi_state[type].last_commit =3D + qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); + } + + stl_le_p((uint8_t *)cache_mem + offset, value); +} + static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t = value, unsigned size) { @@ -141,6 +212,9 @@ static void cxl_cache_mem_write_reg(void *opaque, hwadd= r offset, uint64_t value, if (offset >=3D A_CXL_HDM_DECODER_CAPABILITY && offset <=3D A_CXL_HDM_DECODER3_TARGET_LIST_HI) { dumb_hdm_handler(cxl_cstate, offset, value); + } else if (offset =3D=3D A_CXL_BI_RT_CTRL || + offset =3D=3D A_CXL_BI_DECODER_CTRL) { + bi_handler(cxl_cstate, offset, value); } else { cregs->cache_mem_registers[offset / 4] =3D value; } @@ -230,7 +304,7 @@ static void ras_init_common(uint32_t *reg_state, uint32= _t *write_msk) } =20 static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk, - enum reg_type type) + enum reg_type type, bool bi) { int decoder_count =3D CXL_HDM_DECODER_COUNT; int hdm_inc =3D R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_L= O; @@ -255,7 +329,9 @@ static void hdm_init_common(uint32_t *reg_state, uint32= _t *write_msk, UIO_DECODER_COUNT, 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CA= P, 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, - SUPPORTED_COHERENCY_MODEL, 0); /* Unknown */ + SUPPORTED_COHERENCY_MODEL, + /* host+dev or Unknown */ + type =3D=3D CXL2_TYPE3_DEVICE && bi ? 3 : 0); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 0); write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] =3D 0x3; @@ -278,9 +354,43 @@ static void hdm_init_common(uint32_t *reg_state, uint3= 2_t *write_msk, } } =20 +static void bi_rt_init_common(uint32_t *reg_state, uint32_t *write_msk) +{ + /* switch usp must commit the new BI-ID, timeout of 2secs */ + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_CAPABILITY, EXPLICIT_COMMIT, 1); + + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_CTRL, COMMIT, 0); + write_msk[R_CXL_BI_RT_CTRL] =3D 0x1; + + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_STATUS, COMMITTED, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_STATUS, ERR_NOT_COMMITTED, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_STATUS, COMMIT_TMO_SCALE, 0x6); + ARRAY_FIELD_DP32(reg_state, CXL_BI_RT_STATUS, COMMIT_TMO_BASE, 0x2); +} + +static void bi_decoder_init_common(uint32_t *reg_state, uint32_t *write_ms= k, + enum reg_type type) +{ + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CAPABILITY, HDM_D, 0); + /* switch dsp must commit the new BI-ID, timeout of 2secs */ + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CAPABILITY, EXPLICIT_COMMIT, + (type !=3D CXL2_ROOT_PORT && type !=3D CXL2_TYPE3_DEV= ICE)); + + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CTRL, BI_FW, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CTRL, BI_ENABLE, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_CTRL, COMMIT, 0); + write_msk[R_CXL_BI_DECODER_CTRL] =3D 0x7; + + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_STATUS, COMMITTED, 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_STATUS, ERR_NOT_COMMITTED, = 0); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_STATUS, COMMIT_TMO_SCALE, 0= x6); + ARRAY_FIELD_DP32(reg_state, CXL_BI_DECODER_STATUS, COMMIT_TMO_BASE, 0x= 2); +} + void cxl_component_register_init_common(uint32_t *reg_state, uint32_t *write_msk, - enum reg_type type) + enum reg_type type, + bool bi) { int caps =3D 0; =20 @@ -320,7 +430,7 @@ void cxl_component_register_init_common(uint32_t *reg_s= tate, case CXL2_LOGICAL_DEVICE: /* + HDM */ init_cap_reg(HDM, 5, 1); - hdm_init_common(reg_state, write_msk, type); + hdm_init_common(reg_state, write_msk, type, bi); /* fallthrough */ case CXL2_DOWNSTREAM_PORT: case CXL2_DEVICE: @@ -335,6 +445,24 @@ void cxl_component_register_init_common(uint32_t *reg_= state, abort(); } =20 + /* back invalidate */ + if (bi) { + switch (type) { + case CXL2_UPSTREAM_PORT: + init_cap_reg(BI_RT, 11, CXL_BI_RT_CAP_VERSION); + bi_rt_init_common(reg_state, write_msk); + break; + case CXL2_ROOT_PORT: + case CXL2_DOWNSTREAM_PORT: + case CXL2_TYPE3_DEVICE: + init_cap_reg(BI_DECODER, 12, CXL_BI_DECODER_CAP_VERSION); + bi_decoder_init_common(reg_state, write_msk, type); + break; + default: + break; + } + } + ARRAY_FIELD_DP32(reg_state, CXL_CAPABILITY_HEADER, ARRAY_SIZE, caps); #undef init_cap_reg } diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 3c7ecd8c48bc..3f09c589ae58 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -748,6 +748,11 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error = **errp) return false; } =20 + if (!ct3d->flitmode && ct3d->hdmdb) { + error_setg(errp, "hdm-db requires operating in 256b flit"); + return false; + } + if (ct3d->hostvmem) { MemoryRegion *vmr; char *v_name; @@ -1317,7 +1322,8 @@ static void ct3d_reset(DeviceState *dev) =20 pcie_cap_fill_link_ep_usp(PCI_DEVICE(dev), ct3d->width, ct3d->speed, ct3d->flitmode); - cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DE= VICE); + cxl_component_register_init_common(reg_state, write_msk, + CXL2_TYPE3_DEVICE, ct3d->hdmdb); cxl_device_register_init_t3(ct3d, CXL_T3_MSIX_MBOX); =20 /* @@ -1356,6 +1362,7 @@ static const Property ct3_props[] =3D { DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLType3Dev, width, PCIE_LINK_WIDTH_16), DEFINE_PROP_BOOL("x-256b-flit", CXLType3Dev, flitmode, false), + DEFINE_PROP_BOOL("hdm-db", CXLType3Dev, hdmdb, false), }; =20 static uint64_t get_lsa_size(CXLType3Dev *ct3d) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 64086d8ec2f2..320818a8f1ce 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -39,7 +39,7 @@ static void latch_registers(CXLDownstreamPort *dsp) uint32_t *write_msk =3D dsp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 cxl_component_register_init_common(reg_state, write_msk, - CXL2_DOWNSTREAM_PORT); + CXL2_DOWNSTREAM_PORT, true); } =20 /* TODO: Look at sharing this code across all CXL port types */ diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 5641048084a4..e2093ac39ee6 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -101,7 +101,8 @@ static void latch_registers(CXLRootPort *crp) uint32_t *reg_state =3D crp->cxl_cstate.crb.cache_mem_registers; uint32_t *write_msk =3D crp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 - cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_POR= T); + cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_POR= T, + true); } =20 static void build_dvsecs(PCIDevice *d, CXLComponentState *cxl) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index c352d11dc7b7..fb8d19539c9f 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -90,7 +90,7 @@ static void latch_registers(CXLUpstreamPort *usp) uint32_t *write_msk =3D usp->cxl_cstate.crb.cache_mem_regs_write_mask; =20 cxl_component_register_init_common(reg_state, write_msk, - CXL2_UPSTREAM_PORT); + CXL2_UPSTREAM_PORT, usp->flitmode); ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, = 8); } =20 diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index b6e2eb796951..11623a5666f6 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -300,7 +300,7 @@ static void pxb_cxl_dev_reset(DeviceState *dev) uint32_t *write_msk =3D cxl_cstate->crb.cache_mem_regs_write_mask; int dsp_count =3D 0; =20 - cxl_component_register_init_common(reg_state, write_msk, CXL2_RC); + cxl_component_register_init_common(reg_state, write_msk, CXL2_RC, fals= e); /* * The CXL specification allows for host bridges with no HDM decoders * if they only have a single root port. --=20 2.51.0