From nobody Sun Feb 8 22:07:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1770201302; cv=none; d=zohomail.com; s=zohoarc; b=fCKfMDg9Vf1pSdClDsR/3NjgbGYm8b2jAtYX1EtrMNzm9AlP2DWAWpimw3agX+GILCrtmoBOxrooO02tUwk4O6Qjq8ytwUKuKo0BnvmiiB2i/JhTEraUDPk3jDRnPyzPf0325jz+CCZKjzgqM+vI4YwMfpksVA/mSdQ7ZCziajU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770201302; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0eFcpqgjedIMkoHQ51JuwO3iS8I5PR9YBXqb5Ny/aGI=; b=d8Ki4+b0QC9MdgDHTgbSteB5GnGWQmwDlRoPe/cR0acM4OMyj7GmuwJBPgQxPWxtRuYpjLzjMZAMKfqrDMezhonVOXkzmK2vEEKYszKTnHhssUoXVMibIQvYlMZqFt3U4+6iuezmTbD1zfFSP0bOBpJeuqxLnVhsex5cT4NWIKc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770201302831518.3168715982079; Wed, 4 Feb 2026 02:35:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnaCr-0003yE-4D; Wed, 04 Feb 2026 05:33:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnaCA-0002iP-MF for qemu-devel@nongnu.org; Wed, 04 Feb 2026 05:33:15 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnaC8-0004E7-FF for qemu-devel@nongnu.org; Wed, 04 Feb 2026 05:33:13 -0500 Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-226-a0XDDQ4NNqu5hnwAB9v-Iw-1; Wed, 04 Feb 2026 05:33:08 -0500 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 92CA51800473; Wed, 4 Feb 2026 10:33:07 +0000 (UTC) Received: from corto.redhat.com (unknown [10.45.224.44]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C2D3D18003F6; Wed, 4 Feb 2026 10:33:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1770201191; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0eFcpqgjedIMkoHQ51JuwO3iS8I5PR9YBXqb5Ny/aGI=; b=cd2H5Bxz+or6pafbX+2UC91Q0Zh7MQsQRvnIOjyY8sbs5hWJYFAS/1Cqv04ZlvAmrR2KnP ucmSs2Gy1GPiXzbMAbyW6e84O6iPNATDbK/LxfBn0WPYXnmF3+ojXsBWYJpC/7eQeskgb8 pMA5GgaAz2ley/WubFy0znbDFyPmAmk= X-MC-Unique: a0XDDQ4NNqu5hnwAB9v-Iw-1 X-Mimecast-MFC-AGG-ID: a0XDDQ4NNqu5hnwAB9v-Iw_1770201187 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Kane Chen , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nabih Estefan Subject: [PULL 41/45] hw/arm/aspeed: Model AST1700 I3C block as unimplemented device Date: Wed, 4 Feb 2026 11:31:32 +0100 Message-ID: <20260204103136.1795455-42-clg@redhat.com> In-Reply-To: <20260204103136.1795455-1-clg@redhat.com> References: <20260204103136.1795455-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1770201304435158500 From: Kane Chen AST1700 exposes more I3C buses than the current dummy I3C model provides. When Linux probes the I3C devices on AST1700 this mismatch can trigger a kernel panic. Model the I3C block as an unimplemented device to make the missing functionality explicit and avoid unexpected side effects. This wires up the I3C interrupt lines for the IO expanders and adds the corresponding device entries for the AST1700 model. No functional I3C emulation is provided yet; this only prevents crashes and documents the missing piece. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Tested-by: Nabih Estefan Link: https://lore.kernel.org/qemu-devel/20260204082113.3955407-19-kane_che= n@aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_ast1700.h | 3 +++ include/hw/arm/aspeed_soc.h | 2 ++ hw/arm/aspeed_ast1700.c | 15 +++++++++++++++ hw/arm/aspeed_ast27x0.c | 18 ++++++++++++++++-- 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/aspeed_ast1700.h b/include/hw/arm/aspeed_ast170= 0.h index b5cb0a901086..f7bd4e8650ba 100644 --- a/include/hw/arm/aspeed_ast1700.h +++ b/include/hw/arm/aspeed_ast1700.h @@ -19,6 +19,7 @@ #include "hw/ssi/aspeed_smc.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/char/serial-mm.h" +#include "hw/misc/unimp.h" =20 #define AST1700_SGPIO_NUM 2 #define AST1700_WDT_NUM 9 @@ -46,6 +47,8 @@ struct AspeedAST1700SoCState { AspeedI2CState i2c; AspeedPWMState pwm; AspeedWDTState wdt[AST1700_WDT_NUM]; + + UnimplementedDeviceState i3c; }; =20 #endif /* ASPEED_AST1700_H */ diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 4ea252104137..b185b0418678 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -294,6 +294,8 @@ enum { ASPEED_DEV_IOEXP1_I2C, ASPEED_DEV_IOEXP0_INTCIO, ASPEED_DEV_IOEXP1_INTCIO, + ASPEED_DEV_IOEXP0_I3C, + ASPEED_DEV_IOEXP1_I3C, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/hw/arm/aspeed_ast1700.c b/hw/arm/aspeed_ast1700.c index 174186964eb6..e90302c11bcd 100644 --- a/hw/arm/aspeed_ast1700.c +++ b/hw/arm/aspeed_ast1700.c @@ -15,6 +15,7 @@ =20 #define AST2700_SOC_LTPI_SIZE 0x01000000 #define AST1700_SOC_SRAM_SIZE 0x00040000 +#define AST1700_SOC_I3C_SIZE 0x00010000 =20 enum { ASPEED_AST1700_DEV_SPI0, @@ -26,6 +27,7 @@ enum { ASPEED_AST1700_DEV_SGPIOM0, ASPEED_AST1700_DEV_SGPIOM1, ASPEED_AST1700_DEV_I2C, + ASPEED_AST1700_DEV_I3C, ASPEED_AST1700_DEV_UART12, ASPEED_AST1700_DEV_LTPI_CTRL, ASPEED_AST1700_DEV_WDT, @@ -42,6 +44,7 @@ static const hwaddr aspeed_ast1700_io_memmap[] =3D { [ASPEED_AST1700_DEV_SGPIOM0] =3D 0x00C0C000, [ASPEED_AST1700_DEV_SGPIOM1] =3D 0x00C0D000, [ASPEED_AST1700_DEV_I2C] =3D 0x00C0F000, + [ASPEED_AST1700_DEV_I3C] =3D 0x00C20000, [ASPEED_AST1700_DEV_UART12] =3D 0x00C33B00, [ASPEED_AST1700_DEV_LTPI_CTRL] =3D 0x00C34000, [ASPEED_AST1700_DEV_WDT] =3D 0x00C37000, @@ -178,6 +181,14 @@ static void aspeed_ast1700_realize(DeviceState *dev, E= rror **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->wdt[i]),= 0)); } =20 + /* I3C */ + qdev_prop_set_string(DEVICE(&s->i3c), "name", "ioexp-i3c"); + qdev_prop_set_uint64(DEVICE(&s->i3c), "size", AST1700_SOC_I3C_SIZE); + sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp); + memory_region_add_subregion_overlap(&s->iomem, + aspeed_ast1700_io_memmap[ASPEED_AST1700_DEV_I3C], + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->i3c), 0), + -1000); } =20 static void aspeed_ast1700_instance_init(Object *obj) @@ -227,6 +238,10 @@ static void aspeed_ast1700_instance_init(Object *obj) &s->wdt[i], "aspeed.wdt-ast2700"); } =20 + /* I3C */ + object_initialize_child(obj, "ioexp-i3c", &s->i3c, + TYPE_UNIMPLEMENTED_DEVICE); + return; } =20 diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 8242258df442..d3b305fa7a1a 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -158,7 +158,9 @@ static const int aspeed_soc_ast2700a1_irqmap[] =3D { [ASPEED_DEV_PECI] =3D 197, [ASPEED_DEV_SDHCI] =3D 197, [ASPEED_DEV_IOEXP0_I2C] =3D 198, + [ASPEED_DEV_IOEXP0_I3C] =3D 199, [ASPEED_DEV_IOEXP1_I2C] =3D 200, + [ASPEED_DEV_IOEXP1_I3C] =3D 201, }; =20 /* GICINT 192 */ @@ -221,12 +223,24 @@ static const int ast2700_gic198_intcmap[] =3D { [ASPEED_DEV_IOEXP0_I2C] =3D 0, /* 0 - 15 */ }; =20 +/* Primary AST1700 Interrupts */ +/* A1: GINTC 199 */ +static const int ast2700_gic199_intcmap[] =3D { + [ASPEED_DEV_IOEXP0_I3C] =3D 0, /* 0 - 15 */ +}; + /* Secondary AST1700 Interrupts */ /* A1: GINTC 200 */ static const int ast2700_gic200_intcmap[] =3D { [ASPEED_DEV_IOEXP1_I2C] =3D 0, /* 0 - 15 */ }; =20 +/* Secondary AST1700 Interrupts */ +/* A1: GINTC 201 */ +static const int ast2700_gic201_intcmap[] =3D { + [ASPEED_DEV_IOEXP1_I3C] =3D 0, /* 0 - 15 */ +}; + /* GICINT 192 ~ 201 */ struct gic_intc_irq_info { int irq; @@ -243,9 +257,9 @@ static const struct gic_intc_irq_info ast2700_gic_intcm= ap[] =3D { {196, 1, 4, ast2700_gic196_intcmap}, {197, 1, 5, ast2700_gic197_intcmap}, {198, 2, 0, ast2700_gic198_intcmap}, - {199, 1, 7, NULL}, + {199, 2, 1, ast2700_gic199_intcmap}, {200, 3, 0, ast2700_gic200_intcmap}, - {201, 1, 9, NULL}, + {201, 3, 1, ast2700_gic201_intcmap}, }; =20 static qemu_irq aspeed_soc_ast2700_get_irq(AspeedSoCState *s, int dev) --=20 2.52.0