From nobody Mon Feb 9 00:26:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=aspeedtech.com); dmarc=pass(p=quarantine dis=none) header.from=aspeedtech.com ARC-Seal: i=2; a=rsa-sha256; t=1770193584; cv=pass; d=zohomail.com; s=zohoarc; b=OCYc8YHYnpCN/Fxq9eLCfLJ7A0be7I1jmIVvEsieh3gbqT7RrRO9YzmadQdlu2wOh+tBhbabTK2vGU0sJvzHonQY9e3Yo6xIbKckRFR2JHdbqV4RB4tE8NOd7BK4mPDmIii6/9dpOANIYrdf58YAvz7AX6+3WmcfSF1XEhlfP1o= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770193584; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xanY8lWWj1o9pHV4DaF+bwhx77T/jfPF1cnYyg/dbTU=; b=EoR9Uhwf1ZpYm9EhzzhuqC4/FXcV3OmAiqwuTVS1/ey4D9sZPLUEcGjcjTIjDyi0HzO4TJ+A4bHrZSy71lznAQP0gzduhTGm37b6lRv9Amv/OZLfvtVNMrMyWHdjUEQsetiQjXZlAMoKPC8nPRcVKSvKRO9LTc02H4oVVg98OCs= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=aspeedtech.com); dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770193583582907.9335011646855; Wed, 4 Feb 2026 00:26:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnY8n-0002OZ-HI; Wed, 04 Feb 2026 03:21:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnY8l-0002O4-CN; Wed, 04 Feb 2026 03:21:35 -0500 Received: from mail-japanwestazlp170120003.outbound.protection.outlook.com ([2a01:111:f403:c406::3] helo=OS8PR02CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnY8j-0003UH-Jw; Wed, 04 Feb 2026 03:21:35 -0500 Received: from SI6PR06MB7631.apcprd06.prod.outlook.com (2603:1096:4:239::11) by PUZPR06MB5586.apcprd06.prod.outlook.com (2603:1096:301:e8::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.16; Wed, 4 Feb 2026 08:21:22 +0000 Received: from SI6PR06MB7631.apcprd06.prod.outlook.com ([fe80::afe5:a3f1:b435:e43c]) by SI6PR06MB7631.apcprd06.prod.outlook.com ([fe80::afe5:a3f1:b435:e43c%4]) with mapi id 15.20.9587.010; Wed, 4 Feb 2026 08:21:22 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=xiUG0b8sVT3fwP6VlA0RkmEtwEk4yHKyRNg+/ZTvH2vpOIEOLRlxbOAvn10+4F3qx0spYBwftf+TbV+eBeNuDLJ1v5qEyggtwISBfQjB82gNwaVLj+zjjlJPcch300h6DAnTwQafOPCzR1e0wBqBt5rNqmFKydgipeGk7n7Ckcn1jLsdaZQhWZHbRg69qpQ6jQfYBI9DW4CTM91zME5VmYE2UAZckDFzsd7BZMlr1q4OACO9lneEwj6c0m5kVfFwyyvAjP6waR0gDd0OREfDsHynZR5XNEsDl9Kn3BWi53iFvxa6hmmKjQhtVJVR6f1IvhtiAGwu7+oKHT581RgQuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xanY8lWWj1o9pHV4DaF+bwhx77T/jfPF1cnYyg/dbTU=; b=U2fNuGQXYVcmUpY2vTYhOkLqjqsmLDAW4QmaVIGyD5FTUq8G0BjWJ7N5s6JIMGYC+4FzsmPtllV/L2ssdQ1bvAuURTlWT8+i3moU6JD0V0CrVAPhFCvLOuO+aKYxmSsHK8g1CTVWL7E6l/QVwo/5gl3UDd2yypzvM1ioKBueb9lJWyqynWV0envDMUNg8pkGqVt1wBS0AurXfokZZ0+3ER6z3bFLCFkJYORuX6pJX4lvuaJqb46I5ppfbPqipBWbOL2GmHjOuyXzE/bQrtNWUwMPGyb09uuhQK4Vz7FgcrWbyKnnI65waXbXgUaXuHY0xeOZKwDLTrDwUw05p0hTtw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=aspeedtech.com; dmarc=pass action=none header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xanY8lWWj1o9pHV4DaF+bwhx77T/jfPF1cnYyg/dbTU=; b=aTmgkVx2bK2DMnzeOzuPyJClUnFnipbsnTTZ06LeS4L2sGou3UGCM8Mu86GluOnPNqBpyt8RDh56Hvpx/JnCOyQwmy9yP8/kwvfs1dSjdMBtAprgK1KSGVnmNmrwfNai/8Wzaks8EmKpg/O1Z64vk0Aa6j5TkMHmqEsba9JY1YTZVqlxUkoNLapzNy6P7tIWhcNlhl7dHs0IkyyH19VRNsv4B5+yC/tbceGWvZJ676LoQkm5GD5/RjRYThtFOMBFdaElk6k8ho8AHTWmSV+dEmLZudC0NzEpCvaRPjrANKZ6lx3EYT0w0UtCjrFhpNy7WQYAVfyKlivV2vaMXVFhkQ== From: Kane Chen To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Troy Lee , "kaneluno1@gmail.com" , Kane Chen Subject: [PATCH v7 06/22] hw/arm/aspeed: Integrate interrupt controller for AST1700 Thread-Topic: [PATCH v7 06/22] hw/arm/aspeed: Integrate interrupt controller for AST1700 Thread-Index: AQHcla8/itGmu5FPUUeTNpv6WhfoGg== Date: Wed, 4 Feb 2026 08:21:22 +0000 Message-ID: <20260204082113.3955407-7-kane_chen@aspeedtech.com> References: <20260204082113.3955407-1-kane_chen@aspeedtech.com> In-Reply-To: <20260204082113.3955407-1-kane_chen@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SI6PR06MB7631:EE_|PUZPR06MB5586:EE_ x-ms-office365-filtering-correlation-id: fa7478cd-fa22-4c4c-0f19-08de63c661ad x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|366016|1800799024|376014|38070700021; x-microsoft-antispam-message-info: =?iso-8859-1?Q?OT7Op5Wx7MODfuUyP6WAU54P4LqdNWIRH+gPLxa61qgqEoStfKkhkWeKzf?= =?iso-8859-1?Q?zCR545sPchmKHDdqCFbM+VFKrq7BFJNw4SBkbwWqyn8js8jrJTXhYqeJZz?= =?iso-8859-1?Q?iArHOaF3+DjNMCLyf42ULXz4cgOXQJPBY+h9UVQ/hVjA67YCE4oNb2fBKV?= =?iso-8859-1?Q?zxHEvFRPnpYgT7hxAWWDRLUGT5TW2VKlESNBax3n+eE2XQyLk2xplAkwKl?= =?iso-8859-1?Q?O7ld2iwutCqOqW3ywozHNMibbIDBH1bdb4Ne4xiOG25LJY9TWzwZ1JQAd/?= =?iso-8859-1?Q?pFcDTipcx8MLhxAMXXj+3p24cmbKTdiWxK9uj33x97hSBJt4zs/3x/wpQ0?= =?iso-8859-1?Q?H1SP+CImHpZye9/LQFcGCf0wrAgb/9WwzIF3C+3H4O8cD3oRQf3AxTXQU7?= =?iso-8859-1?Q?GMrCbzXypuDBIi5PpMyNbfKQ3JWI9WR+mugi4l2folpKlinb6zARhYf/Eo?= =?iso-8859-1?Q?o/US8GC6/BOI4JoTHKHhQ1sIGOgicbb2KpH3joMJK2smv4M/Mj16YJY5F2?= =?iso-8859-1?Q?vf1KCozW/eqaSHewbR4NhK1dgIgJP2Eof5Yv8rKQkTYD1IBI2/TpOkOFBN?= =?iso-8859-1?Q?n5ZzO6hMHyE+q/RUN3N1ar4TeFgN/oorIdz4N9WZPgvlotL0yc9eRZer5n?= =?iso-8859-1?Q?8fGAQhW6gRDAs2Fma3p6j7E/Db9nqyW37OE0oDWOfhx1IOSTD8iPJOzwcQ?= =?iso-8859-1?Q?ZIBtnrieTHJvuG3/aOxLljQA4skSRNe+k+3oEE4TRZLLYKr49JkEBILDNm?= =?iso-8859-1?Q?WOxeR0302cK+qJx1jPwHSnQvx5TOxVzpHpy9gZuFqzI2Ivw9IImG2QIdGF?= =?iso-8859-1?Q?VwroG6w+FsFpsH/w+ZGwETe9GofID+wNPpZowxkuqZHwT/fWkGVv8TLPil?= =?iso-8859-1?Q?CoB1qWTYA8VKNtKnzVXBXmNB86txCXwLgOCndPiBASaiuHO4E29EEPvNfm?= =?iso-8859-1?Q?vtbzlTi/D+4qF4yW8cnyW/0nmZMgemHVCGB5oL1cZfjyfpK/cySwj/1iWa?= =?iso-8859-1?Q?RviCuvxfCvcP1kecbDPUX93xqv8ZC4ss07wfSIPXnZCgEBAF2rX0dNBIdc?= =?iso-8859-1?Q?Ge51oN+7jVLdXjGdfGZsos3YNp4jDGOF98ZuV3b/2WTOakT3IuCn/dO8Yg?= =?iso-8859-1?Q?KIlFw0dGZva2o472i0l0/m67+KWhkgvrmoBdehiSwXT5k89ZyYCjv7o726?= =?iso-8859-1?Q?J1KOkKBRkDDzlYR1ktjp8FQihS1Ers9razddnG/ONRAcofPrk44THvjUt7?= =?iso-8859-1?Q?2J6TcwLtr3G1IaQN+gnIToVrBp5KbtGYyYiMWEtzxiHM5K0XXuhq2OPbol?= =?iso-8859-1?Q?8y20PFL2HTciuG8hy+syeiA3ebrCgPcC/QYBRKJi9sjgp0uFAV4H7hOxvz?= =?iso-8859-1?Q?WlCGGBwp6tIm2IoZOAIYXZDvx4Tq/3Y4F5CyKjEaH4XOWp5mBPrEgUHPqm?= =?iso-8859-1?Q?O5aNjiVPLsohKtBwdr2b1dG+r6rh9M4iQTbV4ZehHblVJtJUiJvB2AwiVy?= =?iso-8859-1?Q?DbB83tXA9hfkNbUkSZDTyv2XUXjqiSDJ6821wVlWtSjOBwV9cNeIoaZgAP?= =?iso-8859-1?Q?Jd/imnt2o75SwI/XpTf6OiGca3pEwJs39whl0Gx+7gqHmAZ6ThLuE69G0D?= =?iso-8859-1?Q?NTwjEQS6SPodjEXxT//gIYfQic7F/kigiNOdExuh7q368BtSu5F0gsTXj4?= =?iso-8859-1?Q?gidDguWBv9lnCl0rD2k=3D?= x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SI6PR06MB7631.apcprd06.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(366016)(1800799024)(376014)(38070700021); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?Q?sIo+T6m1qO7P6PhkEQmAc4FKVJC50oetoZdddriGW0s5NtU5WGA0Z2Dza4?= =?iso-8859-1?Q?WUG4nUDAOmA5Aq72KuKNEZkKpvQ1yFeOcMdG/B8DohpkMZaQkabZgA9D8T?= =?iso-8859-1?Q?8d49+Rufl2MkW2/v3JySl6+CPTRXRiDSBwsGOJdHoNYou6e5K4hHXNcWaW?= =?iso-8859-1?Q?aiWp8bTDWBxc9w1sQIIVyzdMZ1uaUY4OTqbk2K27F4NLYTH738d/6jUkm3?= =?iso-8859-1?Q?4hfVXmEOmGC/uY6uexGPabWYCjY0/jMJKu43drhVdKCT2ZNx9v3pc5+jtb?= =?iso-8859-1?Q?weeX1ByqqMn8DnIaxNiXMuji0qYG8ZDH0G6S95/jeaOj2y+iGfIoRGsDBX?= =?iso-8859-1?Q?x1kZ4LVBYrRmckch2AK3bjC8giq/58Y5xWctnR5tIXsk3Bzz9u1Ew6VFB7?= =?iso-8859-1?Q?2/7fofsOh8WhveLkynqDrYzfEu4MopIbA18pEqAYKKil0b0VIyN/xfuXLp?= =?iso-8859-1?Q?AOVL6e6XtJ2ltT1/H+5xVAZQ53JI5mH4CE0nvuBqHhuSsMtuCt8+bzKtpe?= =?iso-8859-1?Q?HmUrTeJeU3SSWH1Bt+jsIaE8nlTd1vwqqsa8GatSsyO6fmdpiOyF1yLL2u?= =?iso-8859-1?Q?dpAikh+fz/X4je1zCnKs/6GIYVnn1hDo2YhGDBo2fbMwuSfmh/czbmxkkV?= =?iso-8859-1?Q?Wl/L7y+k/V1QwwGlaT1P47xgLby/cYjJtODvreIcxbFGVFOllhLGjCgFtO?= =?iso-8859-1?Q?NHf9pOZu91h3IEdZvObrlf+mZ9zUEHDgdyXxv0/JTsrzoEYbGncoqxkiL9?= =?iso-8859-1?Q?QwZxCROjJ/W3WM4+KcBCOYgWpOfD1+UlFTESur+8RvK0FPE+f2jxXXRjld?= =?iso-8859-1?Q?1rsKcLyMSezu3NWOqK0KW3CmWLvb0e3mvDFMDyaut14OI9mx8M87tXQscM?= =?iso-8859-1?Q?KsCpxwOoKxPdH6N6mg8X/lmjR9eVw9aOWCox3GDE6vYSFnlgaOazVrZMpY?= =?iso-8859-1?Q?wrLU/OVuTLzCyxoHFmN9xRUwP4SxGUtbgW0uDoZjsE4z8vhcc04tlSmXGQ?= =?iso-8859-1?Q?LY88sCVsZ9xEBXLO7ylIme/KM+WAA6NYzJAXrBXMbKsJlC2kFzYjJBunvu?= =?iso-8859-1?Q?6TACrBPd2i88q3c7yF3Tu5sgkv5kEHjTUNBGMZnTRD9WnhD9fSepUUOYoF?= =?iso-8859-1?Q?ltFnU/Tsl9x8QsX1SNNYuspCNIKxocN6gzQ5eTvTTfi3fH7hq47G2QGaLv?= =?iso-8859-1?Q?oQRXtu+tKgFhVzp4DAJvvcHmOspYXBBhTiQxeHylucK74Tlc2l5BaquAEQ?= =?iso-8859-1?Q?dCenGjW/UViJVnXReM9VF6Mmm3s04UpElAEE4nTTAbw8OICR6XmkjqJlzk?= =?iso-8859-1?Q?XCM4vuZoxdLee05Od9zZe+osKDjfniKbwvXiB8Txqzt5G5up4Yeq3kb/LD?= =?iso-8859-1?Q?HNMvgg12tm1OIt2mD5v82hiaRDNPXM0YPpJzgLIiZdcJsDw9vdTDA6ypIe?= =?iso-8859-1?Q?PupR8XNXEnk2e5QSw6ovMNz7c33FvrMnA7sjLuWg9YkyxnIL19xaGDMAUv?= =?iso-8859-1?Q?V2tdmN96WTHdk4jt+sTOJVkZioZOrt0QnkHoKdsEHGm1kg6H+vlxtnmzvg?= =?iso-8859-1?Q?s70FmP/zAocDJeNZmuvGek4wYECDMCQMsf5dx42KY2vhLjAnyuIn1NiSSL?= =?iso-8859-1?Q?yu8afbwJF5gPJv5be+Rk+WqQVs/YI5wlxKboM9kuN6ZNGaBxcCykmt0NvF?= =?iso-8859-1?Q?50hJj+WxS3G9v6EeE9gqrmYer72g9vlTrjbifYuXrOsguq4UDqAdRJB6nb?= =?iso-8859-1?Q?s5yzkRkjcHjvR0tRXEP13874aNMciAxrhrFLyHzDqj+QC2Cpkjdegx04N8?= =?iso-8859-1?Q?1fc86+95Xw=3D=3D?= Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SI6PR06MB7631.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fa7478cd-fa22-4c4c-0f19-08de63c661ad X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Feb 2026 08:21:22.5969 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2c4MinHUymTmftUIX2l0pae4cID9VdQGjCJ39IgtL8LpYuWc2KzkrFIwZ7xV8hLfDaQDNDFj7upRB6vX7aT+jrgyeOgzG2X8mCTeOP3GA90= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB5586 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c406::3; envelope-from=kane_chen@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @aspeedtech.com) X-ZM-MESSAGEID: 1770193585662158500 Content-Type: text/plain; charset="utf-8" Connect the AST1700 interrupt lines to the GIC in AST27X0, enabling the propagation of AST1700-originated interrupts to the host SoC. This patch does not implement interrupt sources in AST1700 itself, only the wiring into AST27X0. Signed-off-by: Kane-Chen-AS Reviewed-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 6 +++- include/hw/intc/aspeed_intc.h | 2 ++ hw/arm/aspeed_ast27x0.c | 37 +++++++++++++++++++++ hw/intc/aspeed_intc.c | 60 +++++++++++++++++++++++++++++++++++ 4 files changed, 104 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index f19bab3457..b051d0eb3a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -58,6 +58,7 @@ #define ASPEED_UARTS_NUM 13 #define ASPEED_JTAG_NUM 2 #define ASPEED_PCIE_NUM 3 +#define ASPEED_INTC_NUM 2 #define ASPEED_IOEXP_NUM 2 =20 struct AspeedSoCState { @@ -146,7 +147,8 @@ struct Aspeed27x0SoCState { AspeedSoCState parent; =20 ARMCPU cpu[ASPEED_CPUS_NUM]; - AspeedINTCState intc[2]; + AspeedINTCState intc[ASPEED_INTC_NUM]; + AspeedINTCState intcioexp[ASPEED_IOEXP_NUM]; GICv3State gic; MemoryRegion dram_empty; }; @@ -288,6 +290,8 @@ enum { ASPEED_DEV_LTPI_CTRL2, ASPEED_DEV_LTPI_IO0, ASPEED_DEV_LTPI_IO1, + ASPEED_DEV_IOEXP0_INTCIO, + ASPEED_DEV_IOEXP1_INTCIO, }; =20 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types); diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h index 5d10268fff..b25ef4a464 100644 --- a/include/hw/intc/aspeed_intc.h +++ b/include/hw/intc/aspeed_intc.h @@ -15,6 +15,8 @@ #define TYPE_ASPEED_INTC "aspeed.intc" #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700" #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700" +#define TYPE_ASPEED_2700_INTCIOEXP1 TYPE_ASPEED_INTC "-ast2700-ioexp1" +#define TYPE_ASPEED_2700_INTCIOEXP2 TYPE_ASPEED_INTC "-ast2700-ioexp2" #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp" #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp" #define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp" diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index a05112e2b0..d9866c2c3b 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -91,7 +91,9 @@ static const hwaddr aspeed_soc_ast2700_memmap[] =3D { [ASPEED_DEV_LTPI_CTRL2] =3D 0x14C35000, [ASPEED_DEV_WDT] =3D 0x14C37000, [ASPEED_DEV_LTPI_IO0] =3D 0x30000000, + [ASPEED_DEV_IOEXP0_INTCIO] =3D 0x30C18000, [ASPEED_DEV_LTPI_IO1] =3D 0x50000000, + [ASPEED_DEV_IOEXP1_INTCIO] =3D 0x50C18000, [ASPEED_DEV_PCIE_MMIO0] =3D 0x60000000, [ASPEED_DEV_PCIE_MMIO1] =3D 0x80000000, [ASPEED_DEV_PCIE_MMIO2] =3D 0xA0000000, @@ -446,6 +448,10 @@ static void aspeed_soc_ast2700_init(Object *obj) object_initialize_child(obj, "intc", &a->intc[0], TYPE_ASPEED_2700_INT= C); object_initialize_child(obj, "intcio", &a->intc[1], TYPE_ASPEED_2700_INTCIO); + object_initialize_child(obj, "intc-ioexp0", &a->intcioexp[0], + TYPE_ASPEED_2700_INTCIOEXP1); + object_initialize_child(obj, "intc-ioexp1", &a->intcioexp[1], + TYPE_ASPEED_2700_INTCIOEXP2); =20 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); object_initialize_child(obj, "adc", &s->adc, typename); @@ -690,6 +696,22 @@ static void aspeed_soc_ast2700_realize(DeviceState *de= v, Error **errp) aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intc[1]), 0, sc->memmap[ASPEED_DEV_INTCIO]); =20 + /* INTCIOEXP0 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[0]), errp)) { + return; + } + + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[0]), 0, + sc->memmap[ASPEED_DEV_IOEXP0_INTCIO]); + + /* INTCIOEXP1 */ + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intcioexp[1]), errp)) { + return; + } + + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&a->intcioexp[1]), 0, + sc->memmap[ASPEED_DEV_IOEXP1_INTCIO]); + /* irq sources -> orgates -> INTC */ for (i =3D 0; i < ic->num_inpins; i++) { qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0, @@ -1006,6 +1028,21 @@ static void aspeed_soc_ast2700_realize(DeviceState *= dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioexp[i]), 0, sc->memmap[ASPEED_DEV_LTPI_IO0 + i]); + + icio =3D ASPEED_INTC_GET_CLASS(&a->intcioexp[i]); + /* INTC_IOEXP internal: orgate[i] -> input[i] */ + for (int j =3D 0; j < icio->num_inpins; j++) { + irq =3D qdev_get_gpio_in(DEVICE(&a->intcioexp[i]), j); + qdev_connect_gpio_out(DEVICE(&a->intcioexp[i].orgates[j]), 0, + irq); + } + + /* INTC_IOEXP output[i] -> INTC0.orgate[0].input[i] */ + for (int j =3D 0; j < icio->num_outpins; j++) { + irq =3D qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), j); + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intcioexp[i]), j, + irq); + } } =20 aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->dpmcu), diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c index 77fae39205..52f2f946d5 100644 --- a/hw/intc/aspeed_intc.c +++ b/hw/intc/aspeed_intc.c @@ -793,6 +793,64 @@ static const TypeInfo aspeed_2700_intc_info =3D { .class_init =3D aspeed_2700_intc_class_init, }; =20 +static AspeedINTCIRQ aspeed_2700_intcioexp2_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 8, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 9, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp2_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP2 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp2_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp2_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp2_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP2, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp2_class_init, +}; + +static AspeedINTCIRQ aspeed_2700_intcioexp1_irqs[ASPEED_INTC_MAX_INPINS] = =3D { + {0, 6, 1, R_GICINT192_EN, R_GICINT192_STATUS}, + {1, 7, 1, R_GICINT193_EN, R_GICINT193_STATUS}, +}; + +static void aspeed_2700_intcioexp1_class_init(ObjectClass *klass, + const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedINTCClass *aic =3D ASPEED_INTC_CLASS(klass); + + dc->desc =3D "ASPEED 2700 IOEXP1 INTC Controller"; + aic->num_lines =3D 32; + aic->num_inpins =3D 2; + aic->num_outpins =3D 10; + aic->mem_size =3D 0x400; + aic->nr_regs =3D 0x58 >> 2; + aic->reg_offset =3D 0x100; + aic->reg_ops =3D &aspeed_intcio_ops; + aic->irq_table =3D aspeed_2700_intcioexp1_irqs; + aic->irq_table_count =3D ARRAY_SIZE(aspeed_2700_intcioexp1_irqs); +} + +static const TypeInfo aspeed_2700_intcioexp1_info =3D { + .name =3D TYPE_ASPEED_2700_INTCIOEXP1, + .parent =3D TYPE_ASPEED_INTC, + .class_init =3D aspeed_2700_intcioexp1_class_init, +}; + static AspeedINTCIRQ aspeed_2700_intcio_irqs[ASPEED_INTC_MAX_INPINS] =3D { {0, 0, 1, R_GICINT192_EN, R_GICINT192_STATUS}, {1, 1, 1, R_GICINT193_EN, R_GICINT193_STATUS}, @@ -950,6 +1008,8 @@ static void aspeed_intc_register_types(void) type_register_static(&aspeed_intc_info); type_register_static(&aspeed_2700_intc_info); type_register_static(&aspeed_2700_intcio_info); + type_register_static(&aspeed_2700_intcioexp1_info); + type_register_static(&aspeed_2700_intcioexp2_info); type_register_static(&aspeed_2700ssp_intc_info); type_register_static(&aspeed_2700ssp_intcio_info); type_register_static(&aspeed_2700tsp_intc_info); --=20 2.43.0