From nobody Tue Feb 10 21:59:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770193125808931.1723392212942; Wed, 4 Feb 2026 00:18:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnY5r-0008F3-9s; Wed, 04 Feb 2026 03:18:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnY5Z-0008Bo-AD for qemu-devel@nongnu.org; Wed, 04 Feb 2026 03:18:19 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnY5W-000312-Hb for qemu-devel@nongnu.org; Wed, 04 Feb 2026 03:18:16 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxHMPAAINpt60PAA--.50317S3; Wed, 04 Feb 2026 16:18:08 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJAx38K8AINpop0_AA--.52833S4; Wed, 04 Feb 2026 16:18:07 +0800 (CST) From: Bibo Mao To: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v4 2/5] target/loongarch: Add default cpucfg3 with LA464 CPU Date: Wed, 4 Feb 2026 16:18:00 +0800 Message-Id: <20260204081803.1414452-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20260204081803.1414452-1-maobibo@loongson.cn> References: <20260204081803.1414452-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJAx38K8AINpop0_AA--.52833S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770193130631154100 Content-Type: text/plain; charset="utf-8" The features shown in cpucfg3 mostly are relative with cache capability, QEMU does not support cache emulation and discard these features. However it will be better if it is the same with host machine. Here add default cpucfg3 feature information with LA464 CPU. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 24c8df1e37..c6787901e2 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -321,6 +321,22 @@ static void loongarch_la464_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG2, LAM, 1); env->cpucfg[2] =3D data; =20 + data =3D 0; + data =3D FIELD_DP32(data, CPUCFG3, CCDMA, 1); + data =3D FIELD_DP32(data, CPUCFG3, UCACC, 1); + data =3D FIELD_DP32(data, CPUCFG3, LLEXC, 1); + data =3D FIELD_DP32(data, CPUCFG3, SCDLY, 1); + data =3D FIELD_DP32(data, CPUCFG3, LLDBAR, 1); + data =3D FIELD_DP32(data, CPUCFG3, ITLBHMC, 1); + data =3D FIELD_DP32(data, CPUCFG3, ICHMC, 1); + data =3D FIELD_DP32(data, CPUCFG3, SPW_LVL, 4); + data =3D FIELD_DP32(data, CPUCFG3, SPW_HP_HF, 1); + if (kvm_enabled()) { + data =3D FIELD_DP32(data, CPUCFG3, RVA, 1); + data =3D FIELD_DP32(data, CPUCFG3, RVAMAX, 7); + } + env->cpucfg[3] =3D data; + env->cpucfg[4] =3D 100 * 1000 * 1000; /* Crystal frequency */ =20 data =3D 0; --=20 2.39.3