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Tue, 03 Feb 2026 21:18:06 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou , Alistair Francis Subject: [PATCH v3 01/19] target/riscv: rvv: Fix NOP_UU_B vs2 width Date: Wed, 4 Feb 2026 13:17:37 +0800 Message-ID: <20260204051756.667397-2-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260204051756.667397-1-max.chou@sifive.com> References: <20260204051756.667397-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=max.chou@sifive.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1770182391552158500 Content-Type: text/plain; charset="utf-8" Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 5aea553814..ec0ea4c143 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4972,7 +4972,7 @@ GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v, 4) =20 /* Narrowing Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ -#define NOP_UU_B uint8_t, uint16_t, uint32_t +#define NOP_UU_B uint8_t, uint16_t, uint16_t #define NOP_UU_H uint16_t, uint32_t, uint32_t #define NOP_UU_W uint32_t, uint64_t, uint64_t /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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This commit introduces [float16|bfloat16|float32|float64|float128]_nan_is_snan that determine if a NaN is signaling. Suggested-by: Richard Henderson Signed-off-by: Max Chou Reviewed-by: Chao Liu Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 176 ++++++++++++++------------------- 1 file changed, 72 insertions(+), 104 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ba4fa08b7b..7d2515c1fa 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -227,42 +227,26 @@ floatx80 floatx80_default_inf(bool zSign, float_statu= s *status) } =20 /*------------------------------------------------------------------------= ---- -| Returns 1 if the half-precision floating-point value `a' is a quiet -| NaN; otherwise returns 0. +| Determine if a float16 NaN is signaling NaN. *-------------------------------------------------------------------------= ---*/ =20 -bool float16_is_quiet_nan(float16 a_, float_status *status) +static bool float16_nan_is_snan(float16 a, float_status *status) { if (no_signaling_nans(status)) { - return float16_is_any_nan(a_); - } else { - uint16_t a =3D float16_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); - } else { - - return ((a >> 9) & 0x3F) =3D=3D 0x3F; - } + return false; } + bool frac_msb_is_one =3D (a >> 9) & 1; + return frac_msb_is_one =3D=3D snan_bit_is_one(status); } =20 /*------------------------------------------------------------------------= ---- -| Returns 1 if the bfloat16 value `a' is a quiet +| Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. *-------------------------------------------------------------------------= ---*/ =20 -bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) +bool float16_is_quiet_nan(float16 a_, float_status *status) { - if (no_signaling_nans(status)) { - return bfloat16_is_any_nan(a_); - } else { - uint16_t a =3D a_; - if (snan_bit_is_one(status)) { - return (((a >> 6) & 0x1FF) =3D=3D 0x1FE) && (a & 0x3F); - } else { - return ((a >> 6) & 0x1FF) =3D=3D 0x1FF; - } - } + return float16_is_any_nan(a_) && !float16_nan_is_snan(a_, status); } =20 /*------------------------------------------------------------------------= ---- @@ -271,36 +255,52 @@ bool bfloat16_is_quiet_nan(bfloat16 a_, float_status = *status) *-------------------------------------------------------------------------= ---*/ =20 bool float16_is_signaling_nan(float16 a_, float_status *status) +{ + return float16_is_any_nan(a_) && float16_nan_is_snan(a_, status); +} + +/*------------------------------------------------------------------------= ---- +| Determine if a bfloat16 NaN is signaling NaN. +*-------------------------------------------------------------------------= ---*/ + +static bool bfloat16_nan_is_snan(bfloat16 a, float_status *status) { if (no_signaling_nans(status)) { - return 0; - } else { - uint16_t a =3D float16_val(a_); - if (snan_bit_is_one(status)) { - return ((a >> 9) & 0x3F) =3D=3D 0x3F; - } else { - return (((a >> 9) & 0x3F) =3D=3D 0x3E) && (a & 0x1FF); - } + return false; } + bool frac_msb_is_one =3D (a >> 6) & 1; + return frac_msb_is_one =3D=3D snan_bit_is_one(status); } =20 /*------------------------------------------------------------------------= ---- -| Returns 1 if the bfloat16 value `a' is a signaling -| NaN; otherwise returns 0. +| Returns 1 if the bfloat16 value `a' is a quiet NaN; otherwise returns 0. +*-------------------------------------------------------------------------= ---*/ + +bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status) +{ + return bfloat16_is_any_nan(a_) && !bfloat16_nan_is_snan(a_, status); +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the bfloat16 value `a' is a signaling NaN; otherwise return= s 0. *-------------------------------------------------------------------------= ---*/ =20 bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status) +{ + return bfloat16_is_any_nan(a_) && bfloat16_nan_is_snan(a_, status); +} + +/*------------------------------------------------------------------------= ---- +| Determine if a float32 NaN is signaling NaN. +*-------------------------------------------------------------------------= ---*/ + +static bool float32_nan_is_snan(float32 a, float_status *status) { if (no_signaling_nans(status)) { - return 0; - } else { - uint16_t a =3D a_; - if (snan_bit_is_one(status)) { - return ((a >> 6) & 0x1FF) =3D=3D 0x1FF; - } else { - return (((a >> 6) & 0x1FF) =3D=3D 0x1FE) && (a & 0x3F); - } + return false; } + bool frac_msb_is_one =3D (a >> 22) & 1; + return frac_msb_is_one =3D=3D snan_bit_is_one(status); } =20 /*------------------------------------------------------------------------= ---- @@ -310,16 +310,7 @@ bool bfloat16_is_signaling_nan(bfloat16 a_, float_stat= us *status) =20 bool float32_is_quiet_nan(float32 a_, float_status *status) { - if (no_signaling_nans(status)) { - return float32_is_any_nan(a_); - } else { - uint32_t a =3D float32_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); - } else { - return ((uint32_t)(a << 1) >=3D 0xFF800000); - } - } + return float32_is_any_nan(a_) && !float32_nan_is_snan(a_, status); } =20 /*------------------------------------------------------------------------= ---- @@ -328,17 +319,21 @@ bool float32_is_quiet_nan(float32 a_, float_status *s= tatus) *-------------------------------------------------------------------------= ---*/ =20 bool float32_is_signaling_nan(float32 a_, float_status *status) +{ + return float32_is_any_nan(a_) && float32_nan_is_snan(a_, status); +} + +/*------------------------------------------------------------------------= ---- +| Determine if a float64 NaN is signaling NaN. +*-------------------------------------------------------------------------= ---*/ + +static bool float64_nan_is_snan(float64 a, float_status *status) { if (no_signaling_nans(status)) { - return 0; - } else { - uint32_t a =3D float32_val(a_); - if (snan_bit_is_one(status)) { - return ((uint32_t)(a << 1) >=3D 0xFF800000); - } else { - return (((a >> 22) & 0x1FF) =3D=3D 0x1FE) && (a & 0x003FFFFF); - } + return false; } + bool frac_msb_is_one =3D (a >> 51) & 1; + return frac_msb_is_one =3D=3D snan_bit_is_one(status); } =20 /*------------------------------------------------------------------------= ---- @@ -348,17 +343,7 @@ bool float32_is_signaling_nan(float32 a_, float_status= *status) =20 bool float64_is_quiet_nan(float64 a_, float_status *status) { - if (no_signaling_nans(status)) { - return float64_is_any_nan(a_); - } else { - uint64_t a =3D float64_val(a_); - if (snan_bit_is_one(status)) { - return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) - && (a & 0x0007FFFFFFFFFFFFULL); - } else { - return ((a << 1) >=3D 0xFFF0000000000000ULL); - } - } + return float64_is_any_nan(a_) && !float64_nan_is_snan(a_, status); } =20 /*------------------------------------------------------------------------= ---- @@ -368,17 +353,7 @@ bool float64_is_quiet_nan(float64 a_, float_status *st= atus) =20 bool float64_is_signaling_nan(float64 a_, float_status *status) { - if (no_signaling_nans(status)) { - return 0; - } else { - uint64_t a =3D float64_val(a_); - if (snan_bit_is_one(status)) { - return ((a << 1) >=3D 0xFFF0000000000000ULL); - } else { - return (((a >> 51) & 0xFFF) =3D=3D 0xFFE) - && (a & UINT64_C(0x0007FFFFFFFFFFFF)); - } - } + return float64_is_any_nan(a_) && float64_nan_is_snan(a_, status); } =20 /*------------------------------------------------------------------------= ---- @@ -444,6 +419,19 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status= *status) return a; } =20 +/*------------------------------------------------------------------------= ---- +| Determine if a float128 NaN is signaling NaN. +*-------------------------------------------------------------------------= ---*/ + +static bool float128_nan_is_snan(float128 a, float_status *status) +{ + if (no_signaling_nans(status)) { + return false; + } + bool frac_msb_is_one =3D (a.high >> 47) & 1; + return frac_msb_is_one =3D=3D snan_bit_is_one(status); +} + /*------------------------------------------------------------------------= ---- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -451,17 +439,7 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status= *status) =20 bool float128_is_quiet_nan(float128 a, float_status *status) { - if (no_signaling_nans(status)) { - return float128_is_any_nan(a); - } else { - if (snan_bit_is_one(status)) { - return (((a.high >> 47) & 0xFFFF) =3D=3D 0xFFFE) - && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); - } else { - return ((a.high << 1) >=3D 0xFFFF000000000000ULL) - && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); - } - } + return float128_is_any_nan(a) && !float128_nan_is_snan(a, status); } =20 /*------------------------------------------------------------------------= ---- @@ -471,15 +449,5 @@ bool float128_is_quiet_nan(float128 a, float_status *s= tatus) =20 bool float128_is_signaling_nan(float128 a, float_status *status) { - if (no_signaling_nans(status)) { - return 0; - } else { - if (snan_bit_is_one(status)) { - return ((a.high << 1) >=3D 0xFFFF000000000000ULL) - && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); - } else { - return (((a.high >> 47) & 0xFFFF) =3D=3D 0xFFFE) - && (a.low || (a.high & UINT64_C(0x00007FFFFFFFFFFF))); - } - } + return float128_is_any_nan(a) && float128_nan_is_snan(a, status); } --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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This commit introduces floatx80_nan_is_snan helper function that determine if a NaN is signaling and change the return type of floatx80_is_[signaling|quiet]_nan to bool. Suggested-by: Richard Henderson Signed-off-by: Max Chou Reviewed-by: Chao Liu Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 55 +++++++++++++--------------------- include/fpu/softfloat.h | 4 +-- 2 files changed, 22 insertions(+), 37 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 7d2515c1fa..9ed968c79b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -357,53 +357,38 @@ bool float64_is_signaling_nan(float64 a_, float_statu= s *status) } =20 /*------------------------------------------------------------------------= ---- -| Returns 1 if the extended double-precision floating-point value `a' is a -| quiet NaN; otherwise returns 0. This slightly differs from the same -| function for other types as floatx80 has an explicit bit. +| Determine if a floatx80 NaN is signaling NaN. +| The MSB of frac differs from the same function for other types as floatx= 80 +| has an explicit bit. *-------------------------------------------------------------------------= ---*/ =20 -int floatx80_is_quiet_nan(floatx80 a, float_status *status) +static bool floatx80_nan_is_snan(floatx80 a, float_status *status) { if (no_signaling_nans(status)) { - return floatx80_is_any_nan(a); - } else { - if (snan_bit_is_one(status)) { - uint64_t aLow; - - aLow =3D a.low & ~0x4000000000000000ULL; - return ((a.high & 0x7FFF) =3D=3D 0x7FFF) - && (aLow << 1) - && (a.low =3D=3D aLow); - } else { - return ((a.high & 0x7FFF) =3D=3D 0x7FFF) - && (UINT64_C(0x8000000000000000) <=3D ((uint64_t)(a.low <<= 1))); - } + return false; } + bool frac_msb_is_one =3D (a.low >> 62) & 1; + return frac_msb_is_one =3D=3D snan_bit_is_one(status); } =20 /*------------------------------------------------------------------------= ---- | Returns 1 if the extended double-precision floating-point value `a' is a -| signaling NaN; otherwise returns 0. This slightly differs from the same -| function for other types as floatx80 has an explicit bit. +| quiet NaN; otherwise returns 0. *-------------------------------------------------------------------------= ---*/ =20 -int floatx80_is_signaling_nan(floatx80 a, float_status *status) +bool floatx80_is_quiet_nan(floatx80 a, float_status *status) { - if (no_signaling_nans(status)) { - return 0; - } else { - if (snan_bit_is_one(status)) { - return ((a.high & 0x7FFF) =3D=3D 0x7FFF) - && ((a.low << 1) >=3D 0x8000000000000000ULL); - } else { - uint64_t aLow; - - aLow =3D a.low & ~UINT64_C(0x4000000000000000); - return ((a.high & 0x7FFF) =3D=3D 0x7FFF) - && (uint64_t)(aLow << 1) - && (a.low =3D=3D aLow); - } - } + return floatx80_is_any_nan(a) && !floatx80_nan_is_snan(a, status); +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the extended double-precision floating-point value `a' is a +| signaling NaN; otherwise returns 0. +*-------------------------------------------------------------------------= ---*/ + +bool floatx80_is_signaling_nan(floatx80 a, float_status *status) +{ + return floatx80_is_any_nan(a) && floatx80_nan_is_snan(a, status); } =20 /*------------------------------------------------------------------------= ---- diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index c18ab2cb60..ac6a392375 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -978,8 +978,8 @@ floatx80 floatx80_rem(floatx80, floatx80, float_status = *status); floatx80 floatx80_sqrt(floatx80, float_status *status); FloatRelation floatx80_compare(floatx80, floatx80, float_status *status); FloatRelation floatx80_compare_quiet(floatx80, floatx80, float_status *sta= tus); -int floatx80_is_quiet_nan(floatx80, float_status *status); -int floatx80_is_signaling_nan(floatx80, float_status *status); +bool floatx80_is_quiet_nan(floatx80, float_status *status); +bool floatx80_is_signaling_nan(floatx80, float_status *status); floatx80 floatx80_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); =20 --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182410; cv=none; d=zohomail.com; s=zohoarc; b=koUc8bxdgJbaCj0pGCKm9DnXznhb8GpsgahpkB01z6NdXdB2XLsJTersgkoGsuLz2xephqe0Ie0tcCfSji6CKkOE6gyfgDZhh+j6ju1wHRnrxJlTPj2kPBCFpIxp/mbtInt5ynmsMzfuDAhdAEDsMa3a43H/7yyfCOdJQRCkzLA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182410; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=I/dvFpuAgHW9LatoJl8ikUFTHhk3Jg3flnJ8ORHZmgw=; b=WEaeuj5dZhGnMOUuW52EC7UQf4GfO0yU9T0tKpRdeLRiMJuhhKscx0VaIrZ/QdyxunHHIqky+LrD5SIGF/VIq0yl0CjMLaAuIiQnOELW1pq8+3YShUTHoT+cf4kS9+7sonbIrk8JbgJ9u8Zj5pSEqp/xoF3hAP1i7gpww2OSV+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182410638898.2974062203426; Tue, 3 Feb 2026 21:20:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVHP-0007Ql-Qb; Wed, 04 Feb 2026 00:18:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHO-0007QO-8Z for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:18 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHM-0007y3-O3 for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:18 -0500 Received: by mail-pj1-x1029.google.com with SMTP id 98e67ed59e1d1-34c708702dfso3488690a91.1 for ; Tue, 03 Feb 2026 21:18:16 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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The helper functions for FPATAN, FYL2XP1, and FYL2X incorrectly check for signaling NaN before checking for invalid encodings. This causes pseudo-NaNs to be treated as valid signaling NaNs and silenced, rather than being rejected as unsupported formats. Reorder the checks to test floatx80_invalid_encoding before floatx80_is_signaling_nan, matching the correct behavior already implemented in helper_fscale. Signed-off-by: Max Chou Reviewed-by: Chao Liu Reviewed-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index b3b23823fd..37c83ded38 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -1377,16 +1377,16 @@ void helper_fpatan(CPUX86State *env) int32_t arg1_exp =3D extractFloatx80Exp(ST1); bool arg1_sign =3D extractFloatx80Sign(ST1); =20 - if (floatx80_is_signaling_nan(ST0, &env->fp_status)) { + if (floatx80_invalid_encoding(ST0, &env->fp_status) || + floatx80_invalid_encoding(ST1, &env->fp_status)) { + float_raise(float_flag_invalid, &env->fp_status); + ST1 =3D floatx80_default_nan(&env->fp_status); + } else if (floatx80_is_signaling_nan(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 =3D floatx80_silence_nan(ST0, &env->fp_status); } else if (floatx80_is_signaling_nan(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 =3D floatx80_silence_nan(ST1, &env->fp_status); - } else if (floatx80_invalid_encoding(ST0, &env->fp_status) || - floatx80_invalid_encoding(ST1, &env->fp_status)) { - float_raise(float_flag_invalid, &env->fp_status); - ST1 =3D floatx80_default_nan(&env->fp_status); } else if (floatx80_is_any_nan(ST0)) { ST1 =3D ST0; } else if (floatx80_is_any_nan(ST1)) { @@ -2061,16 +2061,16 @@ void helper_fyl2xp1(CPUX86State *env) int32_t arg1_exp =3D extractFloatx80Exp(ST1); bool arg1_sign =3D extractFloatx80Sign(ST1); =20 - if (floatx80_is_signaling_nan(ST0, &env->fp_status)) { + if (floatx80_invalid_encoding(ST0, &env->fp_status) || + floatx80_invalid_encoding(ST1, &env->fp_status)) { + float_raise(float_flag_invalid, &env->fp_status); + ST1 =3D floatx80_default_nan(&env->fp_status); + } else if (floatx80_is_signaling_nan(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 =3D floatx80_silence_nan(ST0, &env->fp_status); } else if (floatx80_is_signaling_nan(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 =3D floatx80_silence_nan(ST1, &env->fp_status); - } else if (floatx80_invalid_encoding(ST0, &env->fp_status) || - floatx80_invalid_encoding(ST1, &env->fp_status)) { - float_raise(float_flag_invalid, &env->fp_status); - ST1 =3D floatx80_default_nan(&env->fp_status); } else if (floatx80_is_any_nan(ST0)) { ST1 =3D ST0; } else if (floatx80_is_any_nan(ST1)) { @@ -2159,16 +2159,16 @@ void helper_fyl2x(CPUX86State *env) int32_t arg1_exp =3D extractFloatx80Exp(ST1); bool arg1_sign =3D extractFloatx80Sign(ST1); =20 - if (floatx80_is_signaling_nan(ST0, &env->fp_status)) { + if (floatx80_invalid_encoding(ST0, &env->fp_status) || + floatx80_invalid_encoding(ST1, &env->fp_status)) { + float_raise(float_flag_invalid, &env->fp_status); + ST1 =3D floatx80_default_nan(&env->fp_status); + } else if (floatx80_is_signaling_nan(ST0, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 =3D floatx80_silence_nan(ST0, &env->fp_status); } else if (floatx80_is_signaling_nan(ST1, &env->fp_status)) { float_raise(float_flag_invalid, &env->fp_status); ST1 =3D floatx80_silence_nan(ST1, &env->fp_status); - } else if (floatx80_invalid_encoding(ST0, &env->fp_status) || - floatx80_invalid_encoding(ST1, &env->fp_status)) { - float_raise(float_flag_invalid, &env->fp_status); - ST1 =3D floatx80_default_nan(&env->fp_status); } else if (floatx80_is_any_nan(ST0)) { ST1 =3D ST0; } else if (floatx80_is_any_nan(ST1)) { --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182357; cv=none; d=zohomail.com; s=zohoarc; b=YRxCDwq7RJG77ROv5ykJD5WQnJS4cEtM3OEwKZlwxjJyUZ1/0teDTBdG+41w1JfYReYUZk34qMSEEeW+wFi7ZwEY9t1iqCFuUZU/ZkgfzbYtXxO3xFupAfjowpQBm1T2aqbPBjeSKytRWP9fgP4vXu/QHB/Ui94eNNTMt7YMrcM= ARC-Message-Signature: i=1; a=rsa-sha256; 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According to the definition in OFP8 spec, the conversion from a wider format infinity depends on the saturation mode defined in the spec. Signed-off-by: Max Chou Reviewed-by: Chao Liu --- fpu/softfloat-parts.c.inc | 159 +++++++++++++++++++++------ fpu/softfloat-specialize.c.inc | 62 +++++++++++ fpu/softfloat.c | 191 +++++++++++++++++++++++++++++++-- include/fpu/softfloat-types.h | 12 +++ include/fpu/softfloat.h | 81 ++++++++++++++ 5 files changed, 467 insertions(+), 38 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index 5e0438fc0b..eee7daae4d 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -227,11 +227,28 @@ static void partsN(canonicalize)(FloatPartsN *p, floa= t_status *status, p->exp =3D fmt->frac_shift - fmt->exp_bias - shift + !has_pseudo_denormals; } - } else if (likely(p->exp < fmt->exp_max) || fmt->arm_althp) { + } else if (likely(p->exp < fmt->exp_max)) { p->cls =3D float_class_normal; p->exp -=3D fmt->exp_bias; frac_shl(p, fmt->frac_shift); p->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + } else if (fmt->limited_nan) { + /* + * Formats with limited NaN encodings (E4M3, E2M1, ARM Alt HP). + */ + frac_shl(p, fmt->frac_shift); + p->frac_hi |=3D DECOMPOSED_IMPLICIT_BIT; + if (fmt->normal_frac_max =3D=3D NORMAL_FRAC_MAX_ALL || + p->frac_hi <=3D fmt->normal_frac_max) { + p->cls =3D float_class_normal; + p->exp -=3D fmt->exp_bias; + } else { + if (parts_is_snan_frac(p->frac_hi, status)) { + p->cls =3D float_class_snan; + } else { + p->cls =3D float_class_qnan; + } + } } else if (likely(frac_eqz(p))) { p->cls =3D float_class_inf; } else { @@ -241,14 +258,39 @@ static void partsN(canonicalize)(FloatPartsN *p, floa= t_status *status, } } =20 +/* + * Set FloatPartsN to the maximum normal value for the given format. + * - IEEE formats (!no_infinity): exp =3D exp_max - 1, frac =3D all ones + * - Limited NaN formats (E4M3): exp =3D exp_max, frac =3D normal_frac_max + * - No NaN/InF formats (E2M1, ARM AHP): exp =3D exp_max, frac =3D all ones + */ +static void partsN(set_max_normal)(FloatPartsN *p, const FloatFmt *fmt) +{ + if (!fmt->no_infinity) { + p->exp =3D fmt->exp_max - 1; + frac_allones(p); + } else if (fmt->normal_frac_max !=3D NORMAL_FRAC_MAX_ALL) { + p->exp =3D fmt->exp_max; + frac_clear(p); + p->frac_hi =3D fmt->normal_frac_max; + } else { + p->exp =3D fmt->exp_max; + frac_allones(p); + } +} + /* * Round and uncanonicalize a floating-point number by parts. There * are FRAC_SHIFT bits that may require rounding at the bottom of the * fraction; these bits will be removed. The exponent will be biased * by EXP_BIAS and must be bounded by [EXP_MAX-1, 0]. + * + * The saturate parameter controls saturation behavior for formats that + * support it (OCP FP8 E4M3/E5M2). When true, overflow produces max normal + * instead of infinity (E5M2) or NaN (E4M3). */ static void partsN(uncanon_normal)(FloatPartsN *p, float_status *s, - const FloatFmt *fmt) + const FloatFmt *fmt, bool saturate) { const int exp_max =3D fmt->exp_max; const int frac_shift =3D fmt->frac_shift; @@ -256,8 +298,8 @@ static void partsN(uncanon_normal)(FloatPartsN *p, floa= t_status *s, const uint64_t frac_lsb =3D round_mask + 1; const uint64_t frac_lsbm1 =3D round_mask ^ (round_mask >> 1); const uint64_t roundeven_mask =3D round_mask | frac_lsb; + bool overflow_norm =3D saturate; uint64_t inc; - bool overflow_norm =3D false; int exp, flags =3D 0; =20 switch (s->float_rounding_mode) { @@ -313,30 +355,64 @@ static void partsN(uncanon_normal)(FloatPartsN *p, fl= oat_status *s, } p->frac_lo &=3D ~round_mask; } + p->exp =3D exp; =20 - if (fmt->arm_althp) { - /* ARM Alt HP eschews Inf and NaN for a wider exponent. */ - if (unlikely(exp > exp_max)) { - /* Overflow. Return the maximum normal. */ - flags =3D float_flag_invalid; - exp =3D exp_max; - frac_allones(p); - p->frac_lo &=3D ~round_mask; + /* + * Unified overflow handling based on format capabilities. + * 1. Format has infinity -> overflow to infinity (or saturate) + * 2. Format has NaN but no infinity -> overflow to NaN (or satura= te) + * 3. Format has neither -> always saturate + */ + if (!fmt->no_infinity) { + if (unlikely(exp >=3D exp_max)) { + flags |=3D float_flag_overflow; + if (s->rebias_overflow) { + exp -=3D fmt->exp_re_bias; + } else if (overflow_norm) { + flags |=3D float_flag_inexact; + parts_set_max_normal(p, fmt); + exp =3D p->exp; + p->frac_lo &=3D ~round_mask; + } else { + flags |=3D float_flag_inexact; + p->cls =3D float_class_inf; + exp =3D exp_max; + frac_clear(p); + } } - } else if (unlikely(exp >=3D exp_max)) { - flags |=3D float_flag_overflow; - if (s->rebias_overflow) { - exp -=3D fmt->exp_re_bias; - } else if (overflow_norm) { + } else if (fmt_has_nan_encoding(fmt)) { + bool is_overflow =3D (exp > exp_max) || + (exp =3D=3D exp_max && + p->frac_hi > fmt->normal_frac_max); + + if (unlikely(is_overflow)) { + flags |=3D float_flag_overflow; flags |=3D float_flag_inexact; - exp =3D exp_max - 1; - frac_allones(p); + + if (overflow_norm) { + parts_set_max_normal(p, fmt); + exp =3D p->exp; + } else { + uint8_t dnan =3D s->default_nan_pattern; + p->cls =3D float_class_qnan; + p->sign =3D dnan >> 7; + exp =3D exp_max; + frac_allones(p); + } + } + } else { + if (unlikely(exp > exp_max)) { + if (fmt->overflow_raises_invalid) { + /* ARM Alt HP: raise Invalid, not Overflow */ + flags =3D float_flag_invalid; + } else { + flags |=3D float_flag_overflow; + flags |=3D float_flag_inexact; + } + + parts_set_max_normal(p, fmt); + exp =3D p->exp; p->frac_lo &=3D ~round_mask; - } else { - flags |=3D float_flag_inexact; - p->cls =3D float_class_inf; - exp =3D exp_max; - frac_clear(p); } } frac_shr(p, frac_shift); @@ -422,11 +498,11 @@ static void partsN(uncanon_normal)(FloatPartsN *p, fl= oat_status *s, float_raise(flags, s); } =20 -static void partsN(uncanon)(FloatPartsN *p, float_status *s, - const FloatFmt *fmt) +static void partsN(uncanon_sat)(FloatPartsN *p, float_status *s, + const FloatFmt *fmt, bool saturate) { if (likely(is_anynorm(p->cls))) { - parts_uncanon_normal(p, s, fmt); + parts_uncanon_normal(p, s, fmt, saturate); } else { switch (p->cls) { case float_class_zero: @@ -434,13 +510,30 @@ static void partsN(uncanon)(FloatPartsN *p, float_sta= tus *s, frac_clear(p); return; case float_class_inf: - g_assert(!fmt->arm_althp); - p->exp =3D fmt->exp_max; - frac_clear(p); + /* + * Unified infinity handling using format capabilities. + * Formats with no_infinity must convert infinity to something= else + */ + if (!fmt->no_infinity) { + p->exp =3D fmt->exp_max; + frac_clear(p); + } else if (fmt_has_nan_encoding(fmt)) { + if (saturate) { + parts_set_max_normal(p, fmt); + } else { + uint8_t dnan =3D s->default_nan_pattern; + p->cls =3D float_class_qnan; + p->sign =3D dnan >> 7; + p->exp =3D fmt->exp_max; + frac_allones(p); + } + } else { + parts_set_max_normal(p, fmt); + } return; case float_class_qnan: case float_class_snan: - g_assert(!fmt->arm_althp); + g_assert(fmt_has_nan_encoding(fmt)); p->exp =3D fmt->exp_max; frac_shr(p, fmt->frac_shift); return; @@ -451,6 +544,12 @@ static void partsN(uncanon)(FloatPartsN *p, float_stat= us *s, } } =20 +static void partsN(uncanon)(FloatPartsN *p, float_status *s, + const FloatFmt *fmt) +{ + partsN(uncanon_sat)(p, s, fmt, false); +} + /* * Returns the result of adding or subtracting the values of the * floating-point values `a' and `b'. The operation is performed diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9ed968c79b..40c574283f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -226,6 +226,68 @@ floatx80 floatx80_default_inf(bool zSign, float_status= *status) return packFloatx80(zSign, 0x7fff, z ? 0 : (1ULL << 63)); } =20 +/*------------------------------------------------------------------------= ---- +| Determine if a OCP FP8 E4M3 NaN is signaling NaN. +| E4M3 has only one NaN encoding, so classification is policy-based. +*-------------------------------------------------------------------------= ---*/ + +static bool float8_e4m3_nan_is_snan(float8_e4m3 a, float_status *status) +{ + if (no_signaling_nans(status)) { + return false; + } + return snan_bit_is_one(status); +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the OCP FP8 E4M3 value `a' is a quiet NaN; otherwise return= s 0. +*-------------------------------------------------------------------------= ---*/ + +bool float8_e4m3_is_quiet_nan(float8_e4m3 a_, float_status *status) +{ + return float8_e4m3_is_any_nan(a_) && !float8_e4m3_nan_is_snan(a_, stat= us); +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the OCP FP8 E4M3 value `a' is a signaling NaN; otherwise 0. +*-------------------------------------------------------------------------= ---*/ + +bool float8_e4m3_is_signaling_nan(float8_e4m3 a_, float_status *status) +{ + return float8_e4m3_is_any_nan(a_) && float8_e4m3_nan_is_snan(a_, statu= s); +} + +/*------------------------------------------------------------------------= ---- +| Determine if a OCP FP8 E5M2 NaN is signaling NaN. +*-------------------------------------------------------------------------= ---*/ + +static bool float8_e5m2_nan_is_snan(float8_e5m2 a, float_status *status) +{ + if (no_signaling_nans(status)) { + return false; + } + bool frac_msb_is_one =3D (a >> 1) & 1; + return frac_msb_is_one =3D=3D snan_bit_is_one(status); +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the OCP FP8 E5M2 value `a' is a quiet NaN; otherwise return= s 0. +*-------------------------------------------------------------------------= ---*/ + +bool float8_e5m2_is_quiet_nan(float8_e5m2 a_, float_status *status) +{ + return float8_e5m2_is_any_nan(a_) && !float8_e5m2_nan_is_snan(a_, stat= us); +} + +/*------------------------------------------------------------------------= ---- +| Returns 1 if the OCP FP8 E5M2 value `a' is a signaling NaN; otherwise 0. +*-------------------------------------------------------------------------= ---*/ + +bool float8_e5m2_is_signaling_nan(float8_e5m2 a_, float_status *status) +{ + return float8_e5m2_is_any_nan(a_) && float8_e5m2_nan_is_snan(a_, statu= s); +} + /*------------------------------------------------------------------------= ---- | Determine if a float16 NaN is signaling NaN. *-------------------------------------------------------------------------= ---*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8094358c2e..533f96dcda 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -522,6 +522,13 @@ typedef struct { #define DECOMPOSED_BINARY_POINT 63 #define DECOMPOSED_IMPLICIT_BIT (1ull << DECOMPOSED_BINARY_POINT) =20 +/* + * Sentinel value for normal_frac_max indicating "all fraction values at + * exp_max are normal" (i.e., the format has no NaN encoding at exp_max). + * Used by E2M1 and ARM Alternative Half Precision formats. + */ +#define NORMAL_FRAC_MAX_ALL 0 + /* Structure holding all of the relevant parameters for a format. * exp_size: the size of the exponent field * exp_bias: the offset applied to the exponent field @@ -542,11 +549,39 @@ typedef struct { int exp_max; int frac_size; int frac_shift; - bool arm_althp; bool has_explicit_bit; uint64_t round_mask; + /* + * Format capability flags: + * no_infinity: Format has no infinity encoding. When true, exp=3Dexp_= max + * with frac=3D0 is NOT infinity - it's either NaN or max normal. + * + * limited_nan: Format has limited or no NaN patterns. When combined + * with normal_frac_max, determines NaN encoding capability: + * - limited_nan=3Dfalse: Standard IEEE NaN (exp=3Dexp_max, frac!=3D= 0) + * - limited_nan=3Dtrue && normal_frac_max!=3D0: Limited NaN (E4M3) + * - limited_nan=3Dtrue && normal_frac_max=3D=3D0: No NaN encoding (= AHP, E2M1) + * + * overflow_raises_invalid: Raise Invalid (not Overflow) exception. + * ARM Alt HP uses this to signal overflow as an invalid operation. + * + * normal_frac_max: For formats with limited_nan, the maximum fraction + * value (after normalization shift, including implicit bit) that is + * still considered normal at exp=3Dexp_max. + * Use NORMAL_FRAC_MAX_ALL (0) to indicate all frac values at exp_max + * are normal (E2M1, ARM Alt HP), which also implies no NaN encoding. + */ + bool no_infinity; + bool limited_nan; + bool overflow_raises_invalid; + uint64_t normal_frac_max; } FloatFmt; =20 +static inline bool fmt_has_nan_encoding(const FloatFmt *fmt) +{ + return !fmt->limited_nan || fmt->normal_frac_max !=3D NORMAL_FRAC_MAX_= ALL; +} + /* Expand fields based on the size of exponent and fraction */ #define FLOAT_PARAMS_(E) \ .exp_size =3D E, \ @@ -560,13 +595,27 @@ typedef struct { .frac_shift =3D (-F - 1) & 63, \ .round_mask =3D (1ull << ((-F - 1) & 63)) - 1 =20 +static const FloatFmt float8_e4m3_params =3D { + FLOAT_PARAMS(4, 3), + .no_infinity =3D true, + .limited_nan =3D true, + .normal_frac_max =3D 0xE000000000000000ULL, +}; + +static const FloatFmt float8_e5m2_params =3D { + FLOAT_PARAMS(5, 2), +}; + static const FloatFmt float16_params =3D { FLOAT_PARAMS(5, 10) }; =20 static const FloatFmt float16_params_ahp =3D { FLOAT_PARAMS(5, 10), - .arm_althp =3D true + .no_infinity =3D true, + .limited_nan =3D true, + .overflow_raises_invalid =3D true, + .normal_frac_max =3D NORMAL_FRAC_MAX_ALL, }; =20 static const FloatFmt bfloat16_params =3D { @@ -614,6 +663,16 @@ static void unpack_raw64(FloatParts64 *r, const FloatF= mt *fmt, uint64_t raw) }; } =20 +static void QEMU_FLATTEN float8_e4m3_unpack_raw(FloatParts64 *p, float8_e4= m3 f) +{ + unpack_raw64(p, &float8_e4m3_params, f); +} + +static void QEMU_FLATTEN float8_e5m2_unpack_raw(FloatParts64 *p, float8_e5= m2 f) +{ + unpack_raw64(p, &float8_e5m2_params, f); +} + static void QEMU_FLATTEN float16_unpack_raw(FloatParts64 *p, float16 f) { unpack_raw64(p, &float16_params, f); @@ -671,6 +730,16 @@ static uint64_t pack_raw64(const FloatParts64 *p, cons= t FloatFmt *fmt) return ret; } =20 +static float8_e4m3 QEMU_FLATTEN float8_e4m3_pack_raw(const FloatParts64 *p) +{ + return make_float8_e4m3(pack_raw64(p, &float8_e4m3_params)); +} + +static float8_e5m2 QEMU_FLATTEN float8_e5m2_pack_raw(const FloatParts64 *p) +{ + return make_float8_e5m2(pack_raw64(p, &float8_e5m2_params)); +} + static float16 QEMU_FLATTEN float16_pack_raw(const FloatParts64 *p) { return make_float16(pack_raw64(p, &float16_params)); @@ -758,12 +827,26 @@ static void parts128_canonicalize(FloatParts128 *p, f= loat_status *status, PARTS_GENERIC_64_128(canonicalize, A)(A, S, F) =20 static void parts64_uncanon_normal(FloatParts64 *p, float_status *status, - const FloatFmt *fmt); + const FloatFmt *fmt, bool saturate); static void parts128_uncanon_normal(FloatParts128 *p, float_status *status, - const FloatFmt *fmt); + const FloatFmt *fmt, bool saturate); + +#define parts_uncanon_normal(A, S, F, SAT) \ + PARTS_GENERIC_64_128(uncanon_normal, A)(A, S, F, SAT) =20 -#define parts_uncanon_normal(A, S, F) \ - PARTS_GENERIC_64_128(uncanon_normal, A)(A, S, F) +static void parts64_uncanon_sat(FloatParts64 *p, float_status *status, + const FloatFmt *fmt, bool saturate); +static void parts128_uncanon_sat(FloatParts128 *p, float_status *status, + const FloatFmt *fmt, bool saturate); + +#define parts_uncanon_sat(A, S, F, SAT) \ + PARTS_GENERIC_64_128(uncanon_sat, A)(A, S, F, SAT) + +static void parts64_set_max_normal(FloatParts64 *p, const FloatFmt *fmt); +static void parts128_set_max_normal(FloatParts128 *p, const FloatFmt *fmt); + +#define parts_set_max_normal(P, F) \ + PARTS_GENERIC_64_128(set_max_normal, P)(P, F) =20 static void parts64_uncanon(FloatParts64 *p, float_status *status, const FloatFmt *fmt); @@ -1662,6 +1745,20 @@ static const uint16_t rsqrt_tab[128] =3D { * Pack/unpack routines with a specific FloatFmt. */ =20 +static void float8_e4m3_unpack_canonical(FloatParts64 *p, float8_e4m3 f, + float_status *s) +{ + float8_e4m3_unpack_raw(p, f); + parts_canonicalize(p, s, &float8_e4m3_params); +} + +static void float8_e5m2_unpack_canonical(FloatParts64 *p, float8_e5m2 f, + float_status *s) +{ + float8_e5m2_unpack_raw(p, f); + parts_canonicalize(p, s, &float8_e5m2_params); +} + static void float16a_unpack_canonical(FloatParts64 *p, float16 f, float_status *s, const FloatFmt *par= ams) { @@ -1682,6 +1779,24 @@ static void bfloat16_unpack_canonical(FloatParts64 *= p, bfloat16 f, parts_canonicalize(p, s, &bfloat16_params); } =20 +static float8_e4m3 float8_e4m3_round_pack_canonical(FloatParts64 *p, + float_status *status, + const FloatFmt *params, + const bool saturate) +{ + parts_uncanon_sat(p, status, params, saturate); + return float8_e4m3_pack_raw(p); +} + +static float8_e5m2 float8_e5m2_round_pack_canonical(FloatParts64 *p, + float_status *status, + const FloatFmt *params, + const bool saturate) +{ + parts_uncanon_sat(p, status, params, saturate); + return float8_e5m2_pack_raw(p); +} + static float16 float16a_round_pack_canonical(FloatParts64 *p, float_status *s, const FloatFmt *params) @@ -1838,7 +1953,7 @@ static floatx80 floatx80_round_pack_canonical(FloatPa= rts128 *p, case float_class_normal: case float_class_denormal: if (s->floatx80_rounding_precision =3D=3D floatx80_precision_x) { - parts_uncanon_normal(p, s, fmt); + parts_uncanon_normal(p, s, fmt, false); frac =3D p->frac_hi; exp =3D p->exp; } else { @@ -1847,7 +1962,7 @@ static floatx80 floatx80_round_pack_canonical(FloatPa= rts128 *p, p64.sign =3D p->sign; p64.exp =3D p->exp; frac_truncjam(&p64, p); - parts_uncanon_normal(&p64, s, fmt); + parts_uncanon_normal(&p64, s, fmt, false); frac =3D p64.frac; exp =3D p64.exp; } @@ -2823,6 +2938,66 @@ static void parts_float_to_float_widen(FloatParts128= *a, FloatParts64 *b, } } =20 +bfloat16 float8_e4m3_to_bfloat16(float8_e4m3 a, float_status *s) +{ + FloatParts64 p; + + float8_e4m3_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + + return bfloat16_round_pack_canonical(&p, s); +} + +bfloat16 float8_e5m2_to_bfloat16(float8_e5m2 a, float_status *s) +{ + FloatParts64 p; + + float8_e5m2_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + + return bfloat16_round_pack_canonical(&p, s); +} + +float8_e4m3 bfloat16_to_float8_e4m3(bfloat16 a, bool saturate, float_statu= s *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float8_e4m3_round_pack_canonical(&p, s, &float8_e4m3_params, + saturate); +} + +float8_e5m2 bfloat16_to_float8_e5m2(bfloat16 a, bool saturate, float_statu= s *s) +{ + FloatParts64 p; + + bfloat16_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float8_e5m2_round_pack_canonical(&p, s, &float8_e5m2_params, + saturate); +} + +float8_e4m3 float32_to_float8_e4m3(float32 a, bool saturate, float_status = *s) +{ + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float8_e4m3_round_pack_canonical(&p, s, &float8_e4m3_params, + saturate); +} + +float8_e5m2 float32_to_float8_e5m2(float32 a, bool saturate, float_status = *s) +{ + FloatParts64 p; + + float32_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + return float8_e5m2_round_pack_canonical(&p, s, &float8_e5m2_params, + saturate); +} + float32 float16_to_float32(float16 a, bool ieee, float_status *s) { const FloatFmt *fmt16 =3D ieee ? &float16_params : &float16_params_ahp; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8f82fdfc97..b781bf10b7 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -119,6 +119,18 @@ typedef struct { */ typedef uint16_t bfloat16; =20 +/* + * Software OCP(Open Compute Project) floating point types + */ +typedef uint8_t float8_e4m3; +typedef uint8_t float8_e5m2; +#define float8_e4m3_val(x) (x) +#define float8_e5m2_val(x) (x) +#define make_float8_e4m3(x) (x) +#define make_float8_e5m2(x) (x) +#define const_float8_e4m3(x) (x) +#define const_float8_e5m2(x) (x) + /* * Software IEC/IEEE floating-point underflow tininess-detection mode. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index ac6a392375..7abbf92b7e 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -189,6 +189,87 @@ float128 int128_to_float128(Int128, float_status *stat= us); float128 uint64_to_float128(uint64_t, float_status *status); float128 uint128_to_float128(Int128, float_status *status); =20 +/*------------------------------------------------------------------------= ---- +| Software OCP conversion routines. +*-------------------------------------------------------------------------= ---*/ + +bfloat16 float8_e4m3_to_bfloat16(float8_e4m3, float_status *status); +bfloat16 float8_e5m2_to_bfloat16(float8_e5m2, float_status *status); +float8_e4m3 bfloat16_to_float8_e4m3(bfloat16, bool saturate, float_status = *status); +float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, bool saturate, float_status = *status); +float8_e4m3 float32_to_float8_e4m3(float32, bool saturate, float_status *s= tatus); +float8_e5m2 float32_to_float8_e5m2(float32, bool saturate, float_status *s= tatus); + +/*------------------------------------------------------------------------= ---- +| Software OCP operations. +*-------------------------------------------------------------------------= ---*/ + +bool float8_e4m3_is_quiet_nan(float8_e4m3, float_status *status); +bool float8_e4m3_is_signaling_nan(float8_e4m3, float_status *status); +bool float8_e5m2_is_quiet_nan(float8_e5m2, float_status *status); +bool float8_e5m2_is_signaling_nan(float8_e5m2, float_status *status); + +static inline bool float8_e4m3_is_any_nan(float8_e4m3 a) +{ + return ((float8_e4m3_val(a) & ~0x80) =3D=3D 0x7f); +} + +static inline bool float8_e5m2_is_any_nan(float8_e5m2 a) +{ + return ((float8_e5m2_val(a) & ~0x80) > 0x7c); +} + +static inline bool float8_e4m3_is_neg(float8_e4m3 a) +{ + return float8_e4m3_val(a) >> 7; +} + +static inline bool float8_e5m2_is_neg(float8_e5m2 a) +{ + return float8_e5m2_val(a) >> 7; +} + +static inline bool float8_e4m3_is_infinity(float8_e4m3 a) +{ + return false; +} + +static inline bool float8_e5m2_is_infinity(float8_e5m2 a) +{ + return (float8_e5m2_val(a) & 0x7f) =3D=3D 0x7c; +} + +static inline bool float8_e4m3_is_zero(float8_e4m3 a) +{ + return (float8_e4m3_val(a) & 0x7f) =3D=3D 0; +} + +static inline bool float8_e5m2_is_zero(float8_e5m2 a) +{ + return (float8_e5m2_val(a) & 0x7f) =3D=3D 0; +} + +static inline bool float8_e4m3_is_zero_or_denormal(float8_e4m3 a) +{ + return (float8_e4m3_val(a) & 0x78) =3D=3D 0; +} + +static inline bool float8_e5m2_is_zero_or_denormal(float8_e5m2 a) +{ + return (float8_e5m2_val(a) & 0x7c) =3D=3D 0; +} + +static inline bool float8_e4m3_is_normal(float8_e4m3 a) +{ + uint8_t em =3D float8_e4m3_val(a) & 0x7f; + return em >=3D 0x8 && em <=3D 0x7e; +} + +static inline bool float8_e5m2_is_normal(float8_e5m2 a) +{ + return (((float8_e5m2_val(a) >> 2) + 1) & 0x1f) >=3D 2; +} + /*------------------------------------------------------------------------= ---- | Software half-precision conversion routines. *-------------------------------------------------------------------------= ---*/ --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Max Chou Reviewed-by: Chao Liu --- fpu/softfloat.c | 29 +++++++++++++++++++++++ include/fpu/softfloat-types.h | 5 ++++ include/fpu/softfloat.h | 43 +++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 533f96dcda..96845e86df 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -595,6 +595,13 @@ static inline bool fmt_has_nan_encoding(const FloatFmt= *fmt) .frac_shift =3D (-F - 1) & 63, \ .round_mask =3D (1ull << ((-F - 1) & 63)) - 1 =20 +static const FloatFmt float4_e2m1_params =3D { + FLOAT_PARAMS(2, 1), + .no_infinity =3D true, + .limited_nan =3D true, + .normal_frac_max =3D NORMAL_FRAC_MAX_ALL, +}; + static const FloatFmt float8_e4m3_params =3D { FLOAT_PARAMS(4, 3), .no_infinity =3D true, @@ -663,6 +670,11 @@ static void unpack_raw64(FloatParts64 *r, const FloatF= mt *fmt, uint64_t raw) }; } =20 +static void QEMU_FLATTEN float4_e2m1_unpack_raw(FloatParts64 *p, float4_e2= m1 f) +{ + unpack_raw64(p, &float4_e2m1_params, f); +} + static void QEMU_FLATTEN float8_e4m3_unpack_raw(FloatParts64 *p, float8_e4= m3 f) { unpack_raw64(p, &float8_e4m3_params, f); @@ -1745,6 +1757,13 @@ static const uint16_t rsqrt_tab[128] =3D { * Pack/unpack routines with a specific FloatFmt. */ =20 +static void float4_e2m1_unpack_canonical(FloatParts64 *p, float4_e2m1 f, + float_status *s) +{ + float4_e2m1_unpack_raw(p, f); + parts_canonicalize(p, s, &float4_e2m1_params); +} + static void float8_e4m3_unpack_canonical(FloatParts64 *p, float8_e4m3 f, float_status *s) { @@ -2938,6 +2957,16 @@ static void parts_float_to_float_widen(FloatParts128= *a, FloatParts64 *b, } } =20 +float8_e4m3 float4_e2m1_to_float8_e4m3(float4_e2m1 a, float_status *s) +{ + FloatParts64 p; + + float4_e2m1_unpack_canonical(&p, a, s); + parts_float_to_float(&p, s); + + return float8_e4m3_round_pack_canonical(&p, s, &float8_e4m3_params, fa= lse); +} + bfloat16 float8_e4m3_to_bfloat16(float8_e4m3 a, float_status *s) { FloatParts64 p; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index b781bf10b7..f8cadffff4 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -131,6 +131,11 @@ typedef uint8_t float8_e5m2; #define const_float8_e4m3(x) (x) #define const_float8_e5m2(x) (x) =20 +typedef uint8_t float4_e2m1; +#define float4_e2m1_val(x) ((x) & 0xf) +#define make_float4_e2m1(x) ((x) & 0xf) +#define const_float4_e2m1(x) ((x) & 0xf) + /* * Software IEC/IEEE floating-point underflow tininess-detection mode. */ diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 7abbf92b7e..888efed288 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -200,6 +200,8 @@ float8_e5m2 bfloat16_to_float8_e5m2(bfloat16, bool satu= rate, float_status *statu float8_e4m3 float32_to_float8_e4m3(float32, bool saturate, float_status *s= tatus); float8_e5m2 float32_to_float8_e5m2(float32, bool saturate, float_status *s= tatus); =20 +float8_e4m3 float4_e2m1_to_float8_e4m3(float4_e2m1, float_status *status); + /*------------------------------------------------------------------------= ---- | Software OCP operations. *-------------------------------------------------------------------------= ---*/ @@ -270,6 +272,47 @@ static inline bool float8_e5m2_is_normal(float8_e5m2 a) return (((float8_e5m2_val(a) >> 2) + 1) & 0x1f) >=3D 2; } =20 +static inline bool float4_e2m1_is_quiet_nan(float4_e2m1 a, float_status *s= tatus) +{ + return false; +} + +static inline bool float4_e2m1_is_signaling_nan(float4_e2m1 a, float_statu= s *status) +{ + return false; +} + +static inline bool float4_e2m1_is_any_nan(float4_e2m1 a) +{ + return false; +} + +static inline bool float4_e2m1_is_neg(float4_e2m1 a) +{ + return float4_e2m1_val(a) >> 3; +} + +static inline bool float4_e2m1_is_infinity(float4_e2m1 a) +{ + return false; +} + +static inline bool float4_e2m1_is_zero(float4_e2m1 a) +{ + return (float4_e2m1_val(a) & 0x7) =3D=3D 0; +} + +static inline bool float4_e2m1_is_zero_or_denormal(float4_e2m1 a) +{ + return (float4_e2m1_val(a) & 0x6) =3D=3D 0; +} + +static inline bool float4_e2m1_is_normal(float4_e2m1 a) +{ + uint8_t em =3D float4_e2m1_val(a) & 0x7; + return em >=3D 0x2 && em <=3D 0x7; +} + /*------------------------------------------------------------------------= ---- | Software half-precision conversion routines. *-------------------------------------------------------------------------= ---*/ --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/tcg/tcg-cpu.c | 5 +++++ target/riscv/vector_helper.c | 3 ++- 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bd17f61d7b..d6ce51ef5e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvfofp8min, PRIV_VERSION_1_12_0, ext_zvfofp8min), ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn), diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 3696f02ee0..59302894af 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -104,6 +104,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_zvfofp8min) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) BOOL_FIELD(ext_smctr) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 378b298886..ba89436f13 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -710,6 +710,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + if (cpu->cfg.ext_zvfofp8min && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfofp8min extension depends on Zve32f extension= "); + return; + } + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { error_setg(errp, "Zvfh extensions requires Zfhmin extension"); return; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ec0ea4c143..ee5a1e595b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -38,7 +38,8 @@ static target_ulong vtype_reserved(CPURISCVState *env, ta= rget_ulong vtype) int xlen =3D riscv_cpu_xlen(env); target_ulong reserved =3D 0; =20 - if (riscv_cpu_cfg(env)->ext_zvfbfa) { + if (riscv_cpu_cfg(env)->ext_zvfbfa || + riscv_cpu_cfg(env)->ext_zvfofp8min) { reserved =3D vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, xlen - 1 - R_VTYPE_RESERVED_SHI= FT); } else { --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182344; cv=none; d=zohomail.com; s=zohoarc; b=QYewku7TsvW7uGX7emaDCQTYNm8+aJJ4eLl1yvc0igY8zZ9GQohJuZgLPqhlxP5fePKeufZfXxeQjx4GUma82Qa0Qe2zewkq00EvWejU55yJn+WS8DwY6Jx0B8KTVdArqJqEYBM9l9CvOeMHG13JsrzONsrgFYsZEl0aURSOXdc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182344; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0PAMSHiK5VxvAyBb7t1SnwzGu3eBjt9q5jInjPFmz0c=; b=lksVQl0wBzRYtjPk8CLNj8EnezzN+zBy49GgbZexO1Bff+Jnq0aJ269E379sDzklL2exP5oYzZ4r9WgsoAgBH/0CMCoT89QHWTNJQ6Yqc/4VLOeHgAot8zPZOeyO1z7pdxzZcHUlUq1PCiWWw/PCzEzGUfhh7ns/mB5SnT4zKm0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182344598228.6980680720062; Tue, 3 Feb 2026 21:19:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVHm-0007YS-4K; Wed, 04 Feb 2026 00:18:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHb-0007XU-Op for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:32 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHa-00080U-Cm for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:31 -0500 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-34ab8e0df53so5359497a91.3 for ; Tue, 03 Feb 2026 21:18:30 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/cpu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d6ce51ef5e..36fddce5bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2507,6 +2507,15 @@ static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED =3D { }, }; =20 +static RISCVCPUImpliedExtsRule ZVFOFP8MIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfofp8min), + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + static RISCVCPUImpliedExtsRule ZVKN_IMPLIED =3D { .ext =3D CPU_CFG_OFFSET(ext_zvkn), .implied_multi_exts =3D { @@ -2635,8 +2644,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, - &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, - &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVFOFP8MIN_IMPLIED, + &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, &SSCTR_IMPLIED, NULL --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182396; cv=none; d=zohomail.com; s=zohoarc; b=lObKswEedCqOM0G8W5Jk9pL6hB7jhEPqnXZXQ49sP0JtUq42MVbQiOn3D5DG1rbACUs47vGqWVPaU+YHAlMiCUgwSQ7WPv0c89LyMVRq5BUl6vZw1wC/TJ0Q1mutUb2vNtTTmxvMJhWUdL9bWGgyk2eBPv7NIpGiUns9GU2pSTA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182396; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=63sWoJLOOtd8lWo8QXyMTRA67VQwKXCg87mJb8KQGqM=; b=FK+B9b7GDuutrE6yRRjHCm2NBpC6E+R63OHDaY7/WjAiPd2q7zgCIgl7GWQ2rVQaXD1QuCDWoCGvNlWZM7va5VmKeq6HWAUUx7Wq9Vl9Y8xRo41rE275J1xwz8plNEPyR+l0Uc81dbrfpU0tNJM4sCBIDFYMwI7vfHz4lRc1WfA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182396243889.3166507046169; Tue, 3 Feb 2026 21:19:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVHu-0007iQ-Kt; Wed, 04 Feb 2026 00:18:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHi-0007YR-Tz for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:39 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHd-00080u-Ba for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:36 -0500 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-34c868b197eso4697230a91.2 for ; Tue, 03 Feb 2026 21:18:32 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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And the VTYPE.altfmt field is used to select the OFP8 format. * altfmt =3D 0: OFP8.e4m3 to BF16 * altfmt =3D 1: OFP8.e5m2 to BF16 Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/helper.h | 12 +++ target/riscv/insn_trans/trans_rvbf16.c.inc | 16 +++- target/riscv/vector_helper.c | 97 ++++++++++++++++++++++ 3 files changed, 121 insertions(+), 4 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index eb0a488ba8..356c24d9fb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1247,6 +1247,18 @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, = env, i32) DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32) =20 +/* OFP8 functions */ +DEF_HELPER_5(vfwcvtbf16_f_f_v_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvtbf16_f_f_v_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_f_f_w_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_f_f_w_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_sat_f_f_w_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvtbf16_sat_f_f_w_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32) + /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn= _trans/trans_rvbf16.c.inc index 6cfda03d2e..9aafd4d2ef 100644 --- a/target/riscv/insn_trans/trans_rvbf16.c.inc +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc @@ -92,11 +92,20 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, a= rg_vfncvtbf16_f_f_w *a) static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v= *a) { REQUIRE_FPU; - REQUIRE_ZVFBFMIN(ctx); =20 - if (opfv_widen_check(ctx, a) && (ctx->sew =3D=3D MO_16)) { + if (opfv_widen_check(ctx, a) && + ((ctx->sew =3D=3D MO_16 && ctx->cfg_ptr->ext_zvfbfmin) || + (ctx->sew =3D=3D MO_8 && ctx->cfg_ptr->ext_zvfofp8min))) { + gen_helper_gvec_3_ptr *fn; uint32_t data =3D 0; =20 + if (ctx->sew =3D=3D MO_16) { + fn =3D gen_helper_vfwcvtbf16_f_f_v; + } else { + fn =3D ctx->altfmt ? gen_helper_vfwcvtbf16_f_f_v_ofp8e5m2 : + gen_helper_vfwcvtbf16_f_f_v_ofp8e4m3; + } + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -106,8 +115,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, a= rg_vfwcvtbf16_f_f_v *a) tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), vreg_ofs(ctx, a->rs2), tcg_env, ctx->cfg_ptr->vlenb, - ctx->cfg_ptr->vlenb, data, - gen_helper_vfwcvtbf16_f_f_v); + ctx->cfg_ptr->vlenb, data, fn); finalize_rvv_inst(ctx); return true; } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ee5a1e595b..418212973d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5024,6 +5024,103 @@ GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4) RVVCALL(OPFVV1, vfncvtbf16_f_f_w, NOP_UU_H, H2, H4, float32_to_bfloat16) GEN_VEXT_V_ENV(vfncvtbf16_f_f_w, 2) =20 +/* + * OCP FP8 Narrowing Conversions (BF16/F32 -> FP8) + * 1. Initialize a local float_status with RISC-V specific NaN handling + * 2. Call the softfloat conversion function with saturation parameter + * 3. Merge exception flags back to the original status + */ +#define GEN_OCP_FP8_NARROW(NAME, CONVERT_FN, SATURATE, IN_TYPE) \ +static uint8_t NAME(IN_TYPE a, float_status *s) \ +{ \ + float_status local =3D *s; \ + local.default_nan_pattern =3D 0x70; \ + local.default_nan_mode =3D true; \ + uint8_t result =3D CONVERT_FN(a, SATURATE, &local); \ + s->float_exception_flags |=3D local.float_exception_flags; \ + return result; \ +} + +/* BF16 -> E4M3/E5M2 conversions */ +GEN_OCP_FP8_NARROW(vfncvt_bf16_to_e4m3, bfloat16_to_float8_e4m3, false, + uint16_t) +GEN_OCP_FP8_NARROW(vfncvt_bf16_to_e5m2, bfloat16_to_float8_e5m2, false, + uint16_t) +GEN_OCP_FP8_NARROW(vfncvt_bf16_to_e4m3_sat, bfloat16_to_float8_e4m3, true, + uint16_t) +GEN_OCP_FP8_NARROW(vfncvt_bf16_to_e5m2_sat, bfloat16_to_float8_e5m2, true, + uint16_t) + +/* F32 -> E4M3/E5M2 conversions */ +GEN_OCP_FP8_NARROW(vfncvt_f32_to_e4m3, float32_to_float8_e4m3, false, uint= 32_t) +GEN_OCP_FP8_NARROW(vfncvt_f32_to_e5m2, float32_to_float8_e5m2, false, uint= 32_t) +GEN_OCP_FP8_NARROW(vfncvt_f32_to_e4m3_sat, float32_to_float8_e4m3, true, + uint32_t) +GEN_OCP_FP8_NARROW(vfncvt_f32_to_e5m2_sat, float32_to_float8_e5m2, true, + uint32_t) + +/* + * OCP FP8 Widening Conversions (FP8 -> BF16) + * According to Zvfofp8min isa specification: "No rounding occurs, and no + * floating-point exception flags are set." + * 1. Initialize a local float_status with no_signaling_nans=3Dtrue + * 2. Call the softfloat conversion function + * 3. Intentionally DISCARD exception flags (not merged back) + */ +#define GEN_OCP_FP8_WIDEN(NAME, CONVERT_FN) \ +static uint16_t NAME(uint8_t a, float_status *s) \ +{ \ + float_status local =3D *s; \ + local.no_signaling_nans =3D true; \ + return CONVERT_FN(a, &local); \ +} + +GEN_OCP_FP8_WIDEN(vfwcvt_e4m3_to_bf16, float8_e4m3_to_bfloat16) +GEN_OCP_FP8_WIDEN(vfwcvt_e5m2_to_bf16, float8_e5m2_to_bfloat16) + +/* vfwcvtbf16.f.f.w vd, vs2, vm # Convert OFP8 to BF16. */ +RVVCALL(OPFVV1, vfwcvtbf16_f_f_v_ofp8e4m3, WOP_UU_B, H2, H1, + vfwcvt_e4m3_to_bf16) +RVVCALL(OPFVV1, vfwcvtbf16_f_f_v_ofp8e5m2, WOP_UU_B, H2, H1, + vfwcvt_e5m2_to_bf16) +GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v_ofp8e4m3, 2) +GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v_ofp8e5m2, 2) + +/* vfncvtbf16.f.f.w vd, vs2, vm # Convert BF16 to OFP8 without saturation.= */ +RVVCALL(OPFVV1, vfncvtbf16_f_f_w_ofp8e4m3, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e4m3) +RVVCALL(OPFVV1, vfncvtbf16_f_f_w_ofp8e5m2, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e5m2) +GEN_VEXT_V_ENV(vfncvtbf16_f_f_w_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvtbf16_f_f_w_ofp8e5m2, 1) + +/* vfncvtbf16.sat.f.f.w vd, vs2, vm # Convert BF16 to OFP8 with saturation= . */ +RVVCALL(OPFVV1, vfncvtbf16_sat_f_f_w_ofp8e4m3, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e4m3_sat) +RVVCALL(OPFVV1, vfncvtbf16_sat_f_f_w_ofp8e5m2, NOP_UU_B, H1, H2, + vfncvt_bf16_to_e5m2_sat) +GEN_VEXT_V_ENV(vfncvtbf16_sat_f_f_w_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvtbf16_sat_f_f_w_ofp8e5m2, 1) + +/* Quad-width narrowing type for FP32 to OFP8 */ +#define QOP_UU_B uint8_t, uint32_t, uint32_t + +/* vfncvt.f.f.q vd, vs2, vm # Convert FP32 to OFP8. */ +RVVCALL(OPFVV1, vfncvt_f_f_q_ofp8e4m3, QOP_UU_B, H1, H4, + vfncvt_f32_to_e4m3) +RVVCALL(OPFVV1, vfncvt_f_f_q_ofp8e5m2, QOP_UU_B, H1, H4, + vfncvt_f32_to_e5m2) +GEN_VEXT_V_ENV(vfncvt_f_f_q_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvt_f_f_q_ofp8e5m2, 1) + +/* vfncvt.sat.f.f.q vd, vs2, vm # Convert FP32 to OFP8 with saturation. */ +RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e4m3, QOP_UU_B, H1, H4, + vfncvt_f32_to_e4m3_sat) +RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e5m2, QOP_UU_B, H1, H4, + vfncvt_f32_to_e5m2_sat) +GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e4m3, 1) +GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e5m2, 1) + /* * Vector Reduction Operations */ --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182458; cv=none; d=zohomail.com; s=zohoarc; b=NSz/BKWtP5wieGsRNXuHrwm0edPI5g54BYFx5xNx3ysW7BIh/p8IPnZMWcePjJ+sY3wP7sEboHiCQJN1gcKk7scI+y4pGMQfFG6EjUa9ldNanmwwbrR4qqO9Nfpj9Dch2D5JVLZEDf4LDjHpjZN7cQE1BbzTgjPg6/Hui/DAkgY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182458; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=FIZ+8DhFMV5di51oJwROCHq2vvo+jCjrZCBVlKzi/NE=; b=OY050wW2uSowoMOdF/RWy0aniHCTgHqz0hXxsSjXA5eXae9npEfzVki1h1U9oUYWRa2d7lfj0LtWZN56Ai0KXElnnSty1Z6iBVJsfczFlkQnT345ZuRldkEKcQGsBBZ6c2vYwWFC1KxpgdTOBUyAK08GIuqyOZlhbI4DAYsKUL4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182458738644.3186031924125; Tue, 3 Feb 2026 21:20:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVHq-0007aK-AV; Wed, 04 Feb 2026 00:18:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHk-0007Yb-8P for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:42 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHi-00081Z-Lq for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:39 -0500 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-35338b3dd31so2979045a91.2 for ; Tue, 03 Feb 2026 21:18:36 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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And the VTYPE.altfmt field is used to select the OFP8 format. * altfmt =3D 0: BF16 to OFP8.e4m3 * altfmt =3D 1: BF16 to OFP8.e5m2 Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/insn_trans/trans_rvbf16.c.inc | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn= _trans/trans_rvbf16.c.inc index 9aafd4d2ef..16f4403909 100644 --- a/target/riscv/insn_trans/trans_rvbf16.c.inc +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc @@ -67,11 +67,20 @@ static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fc= vt_s_bf16 *a) static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w= *a) { REQUIRE_FPU; - REQUIRE_ZVFBFMIN(ctx); =20 - if (opfv_narrow_check(ctx, a) && (ctx->sew =3D=3D MO_16)) { + if (opfv_narrow_check(ctx, a) && + ((ctx->sew =3D=3D MO_16 && ctx->cfg_ptr->ext_zvfbfmin) || + (ctx->sew =3D=3D MO_8 && ctx->cfg_ptr->ext_zvfofp8min))) { + gen_helper_gvec_3_ptr *fn; uint32_t data =3D 0; =20 + if (ctx->sew =3D=3D MO_16) { + fn =3D gen_helper_vfncvtbf16_f_f_w; + } else { + fn =3D ctx->altfmt ? gen_helper_vfncvtbf16_f_f_w_ofp8e5m2 : + gen_helper_vfncvtbf16_f_f_w_ofp8e4m3; + } + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -81,8 +90,7 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg= _vfncvtbf16_f_f_w *a) tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), vreg_ofs(ctx, a->rs2), tcg_env, ctx->cfg_ptr->vlenb, - ctx->cfg_ptr->vlenb, data, - gen_helper_vfncvtbf16_f_f_w); + ctx->cfg_ptr->vlenb, data, fn); finalize_rvv_inst(ctx); return true; } --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182451; cv=none; d=zohomail.com; s=zohoarc; b=jPmCw2mn4ScNblfzBRbHc5LZnSLXQfBruhR88H/SyqADwFe03KAj49l0lOPSqeNuA9cMn8PzsHwcUuONdtNfUtHhdJ94IgzaGoCtTzHOO2B7oQefoTCk6xxTfwKIMYgzsFWNWkbyqW000i4SQYAdcEZKsopjEnoJxOy6CQAMkvg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182451; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4xhjFhewDZ8HVtK25LyUvnhiok1WWrm6V2kKzv9k0BU=; b=Ffhw/FDXJeNoWkjGo/Kh1ImIvK1abQP4JcvQZ7QUq+DoSSluq/tMvvNmZWZM02L3i6I/VTeSh4bIq4/u09qoNj0+laoOi8J13JgYWwpb2AqZTcsMb1nB5uJMN1CNmkEnLmLGJgiLTOHGW99z7w1rc1+F/eOro/H7gTFhFj1EBIQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182451639722.1166287270017; Tue, 3 Feb 2026 21:20:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVHq-0007aN-Bl; Wed, 04 Feb 2026 00:18:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHl-0007Yf-VF for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:42 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHk-000828-1P for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:41 -0500 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-34be2be4b7cso3396416a91.3 for ; Tue, 03 Feb 2026 21:18:39 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35485eb8d90sm1266314a91.12.2026.02.03.21.18.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Feb 2026 21:18:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1770182318; x=1770787118; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4xhjFhewDZ8HVtK25LyUvnhiok1WWrm6V2kKzv9k0BU=; b=IsB20SgxaLVeKw0u47znyZuDqjajXYMo7cCVQ4Ks+4BgX/TewXRQSiacKkVhKU5/gB +xOVbGarM95f38Q7aaSHHK+3YE5YeeDBBT+Kf3xxj4YlmTP8L2d5r1KAbhHVv/YxMmzk 0Cm+7fQISUQQ2pRJHla+fv0kA1zx1YQkoOoL9wHWepvpbFfGwwZB3QRk2ASFBJSPAvxA h2V/5wnnYDL2PLutvIEJ+xHQB0GymB2bQee1s5F2VSSK9MWSJN3oEYfWY5jNb4gellPG D0JNAMo29ZEh2v71ZEC/1JILU97ISu8REzM5VFaVtv6JJXn/RMVKgYxucTknIe3HOlhP 1VjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770182318; x=1770787118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=4xhjFhewDZ8HVtK25LyUvnhiok1WWrm6V2kKzv9k0BU=; b=toBtYdOEyb6+5DIdcansYHWmAF+mPM+43YHmoXsO/pIOqKXCXUtP13AD7rNMiM5afl iYjI4SPYFVV4JLiP5RUlMW7r8Izxi3pnWvhBhuhoJuWUg+p4j31fFNXVBUqM4kouZnPX zyiDNQhfiYLWxfeiQwIBJl54W2IBAkbnW5S7jFbrSADUo9j80IuUPtiKSfITH+mCsZkN bKTSqgHJzd5pPw22u+0t4euuYirQlxwfo28XeBPBSKIaNQxeCf5yyBBrHH0vC/29FbLA 8sObcN3Az0mK2873qTfVUUL/h2u908hj5/OfC7mreRnQ7XkDff4v5pI7IcJXKNJyaTfb 3tdA== X-Gm-Message-State: AOJu0YwZRG9xRELOHsNMIG5Y/P//cBUZ2nUP0AQHHk7l176Z7+MntLtH 3rkiSmDPF0ASKP36ZgtB+rHzV2YcC4X6Snqh1EMmFJfuoRn9S9YB9aItA+pKiLGHlRNSTYbDGQ6 sJaZ8wjgn/rHj9z8ohV+2/ekVNhh4hi1yqz6j90rQUnXBLkf8FKpAYdbKSOsFDwvn60sWIdTtXJ S09PbRrtwFqBnOXItJguQpOhSDyHB70ByPw16UM2yim8BS X-Gm-Gg: AZuq6aJIcp+N9IMZlme1mFtlPhb8p8f/aB7o9w+PdUeN9NX4SAry51TSUBQzpGEAwy8 5DkjEwQLzseRopTsvoewelA1isV23JZnRlCewcanMvW7XXjxjGOK0b5dDSruJv3xt9zqiF6QPDm upkN2BbZc8khOoEMWioXy+jDFqn+xQXtSQYPlsb3UliOdVIwlMnIISVvYIxewTwIKy6AZTfJeY3 IZc3E8W/akK3DFQqKsKXL2UnpfredWZzCEm0msEaqffRqXDKtFE6jGLfDGb3g8ZH7+nRncAAb5a Koogt5hV3gH+fXIpcfSWBaStj8NPQ9dHKfGX03ZTvyNzbklTJHgh8t6onD48uuAhnWncJhlbgBV e5xHqQpCnq6l9COTeUwmuyITjlgQ+/s4/DwsyTlSWyB57Ts4ADvtvXrI+X8di+zNy3F7DGVri8Z ltnhBbrPUGhoVErv8kAOvzONsnfwFwckONOg0FtH5lL4KBgkTiS1bQx/P6yAq6CVfFlIDBE/PMY vXa+DbNEP0vzLg= X-Received: by 2002:a17:90b:5348:b0:340:ec8f:82d8 with SMTP id 98e67ed59e1d1-354870e9703mr1628842a91.12.1770182318088; Tue, 03 Feb 2026 21:18:38 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou , Alistair Francis Subject: [PATCH v3 11/19] target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min extension Date: Wed, 4 Feb 2026 13:17:47 +0800 Message-ID: <20260204051756.667397-12-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260204051756.667397-1-max.chou@sifive.com> References: <20260204051756.667397-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=max.chou@sifive.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1770182453828158500 Content-Type: text/plain; charset="utf-8" The vfncvtbf16.sat.f.f.w instruction converts a vector of 16-bit floating-point numbers to a vector of 8-bit floating-point numbers with saturation. The VTYPE.altfmt field is used to select the format of the 8-bit floating-p= oint numbers. * altfmt =3D 0: BF16 to OFP8.e4m3 * altfmt =3D 1: BF16 to OFP8.e5m2 Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvofp8.c.inc | 42 ++++++++++++++++++++++ target/riscv/translate.c | 1 + 3 files changed, 46 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6e35c4b1e6..49201c0c20 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -973,6 +973,9 @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 101011= 1 @r2_vm vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm =20 +# *** Zvfofp8min Extension *** +vfncvtbf16_sat_f_f_w 010010 . ..... 11111 001 ..... 1010111 @r2_vm + # *** Zvbc vector crypto extension *** vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvofp8.c.inc b/target/riscv/insn= _trans/trans_rvofp8.c.inc new file mode 100644 index 0000000000..d28f92e050 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvofp8.c.inc @@ -0,0 +1,42 @@ +/* + * RISC-V translation routines for the OFP8 Standard Extensions. + * + * Copyright (C) 2025 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#define REQUIRE_ZVFOFP8MIN(ctx) do { \ + if (!ctx->cfg_ptr->ext_zvfofp8min) { \ + return false; \ + } \ +} while (0) + + +static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (opfv_narrow_check(ctx, a) && ctx->sew =3D=3D MO_8) { + gen_helper_gvec_3_ptr *fn; + uint32_t data =3D 0; + + fn =3D ctx->altfmt ? gen_helper_vfncvtbf16_sat_f_f_w_ofp8e5m2 : + gen_helper_vfncvtbf16_sat_f_f_w_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); + data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a1c4b325e5..137022d7fb 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1219,6 +1219,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" +#include "insn_trans/trans_rvofp8.c.inc" #include "decode-xthead.c.inc" #include "decode-xmips.c.inc" #include "insn_trans/trans_xthead.c.inc" --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182391; cv=none; d=zohomail.com; s=zohoarc; b=XcLO1Pnk8lp5++DjKL5P1jUtSB86MErTNFEQogkzE/nzY6qEn2FXx8/8U/YF1baUm4nT/JMedv3E6hf1TUg98XqG2puamMvcMPUILLVhsayYKzqzwLQpERlR+ZtdWszzKqyhp6ANjeIfeRYvfSL8Ud8d9kyiMgjY0RecaR/A45E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182391; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sJSEG1iIZzEKOd/uP+q0Ia0xnPXmB0ZXfsMVcmphdno=; b=jzVWA90DBfT7T+XXW9pAqHuZpZuraL/+CgJatIUFy5PH8XQdtdp2++DSS3NZZ4izzC34yuzXsFqu1BqsDARlhJd/iC0cMQFzEqDpVSBt2QGmro0qx+ZywpgCUopsHZ8wYUNX6SjrGK4NHcIYHnEydYEJoBhF/2dL1keezAbm1iY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182391916244.0890414357898; Tue, 3 Feb 2026 21:19:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVHw-0007md-7m; Wed, 04 Feb 2026 00:18:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHq-0007b7-L3 for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:48 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHm-00082q-FK for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:44 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-34f2a0c4574so6137421a91.1 for ; Tue, 03 Feb 2026 21:18:42 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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The vfncvt.sat.f.fq instruction converts a vector of FP32 elements to a vector of OFP8 elements with satura= tion. The VTYPE.altfmt field is used to select the OFP8 format. * altfmt =3D 0: FP32 to OFP8.e4m3 * altfmt =3D 1: FP32 to OFP8.e5m2 Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvofp8.c.inc | 63 ++++++++++++++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++++++++++++ 3 files changed, 104 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 49201c0c20..f2b413c7d4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -974,6 +974,8 @@ vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 101011= 1 @r_vm vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm =20 # *** Zvfofp8min Extension *** +vfncvt_f_f_q 010010 . ..... 11001 001 ..... 1010111 @r2_vm +vfncvt_sat_f_f_q 010010 . ..... 11011 001 ..... 1010111 @r2_vm vfncvtbf16_sat_f_f_w 010010 . ..... 11111 001 ..... 1010111 @r2_vm =20 # *** Zvbc vector crypto extension *** diff --git a/target/riscv/insn_trans/trans_rvofp8.c.inc b/target/riscv/insn= _trans/trans_rvofp8.c.inc index d28f92e050..619ee4d773 100644 --- a/target/riscv/insn_trans/trans_rvofp8.c.inc +++ b/target/riscv/insn_trans/trans_rvofp8.c.inc @@ -12,6 +12,13 @@ } \ } while (0) =20 +static bool zvfofp8min_narrow_quad_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_sq(s, a->rd, a->rs2, a->vm) && + (s->sew =3D=3D MO_8); +} =20 static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx, arg_rmr *a) { @@ -40,3 +47,59 @@ static bool trans_vfncvtbf16_sat_f_f_w(DisasContext *ctx= , arg_rmr *a) } return false; } + +static bool trans_vfncvt_f_f_q(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (zvfofp8min_narrow_quad_check(ctx, a)) { + gen_helper_gvec_3_ptr *fn; + uint32_t data =3D 0; + + fn =3D ctx->altfmt ? gen_helper_vfncvt_f_f_q_ofp8e5m2 : + gen_helper_vfncvt_f_f_q_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); + data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} + +static bool trans_vfncvt_sat_f_f_q(DisasContext *ctx, arg_rmr *a) +{ + REQUIRE_FPU; + REQUIRE_ZVFOFP8MIN(ctx); + + if (zvfofp8min_narrow_quad_check(ctx, a)) { + gen_helper_gvec_3_ptr *fn; + uint32_t data =3D 0; + + fn =3D ctx->altfmt ? gen_helper_vfncvt_sat_f_f_q_ofp8e5m2 : + gen_helper_vfncvt_sat_f_f_q_ofp8e4m3; + + gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN); + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, ctx->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); + data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), + vreg_ofs(ctx, a->rs2), tcg_env, + ctx->cfg_ptr->vlenb, + ctx->cfg_ptr->vlenb, data, fn); + finalize_rvv_inst(ctx); + return true; + } + return false; +} diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index bcd45b0aa3..9053b9fb57 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -621,6 +621,45 @@ static bool vext_check_sds(DisasContext *s, int vd, in= t vs1, int vs2, int vm) require_align(vs1, s->lmul); } =20 +/* + * Common check function for vector narrowing instructions + * of single-width result (SEW) and quad-width source (4*SEW). + * + * Rules to be checked here: + * 1. The largest vector register group used by an instruction + * can not be greater than 8 vector registers + * (Section 31.5.2) + * 2. Quad-width SEW cannot greater than ELEN. + * (Section 31.2) + * 3. Source vector register number is multiples of 4 * LMUL. + * (Section 31.3.4.2) + * 4. Destination vector register number is multiples of LMUL. + * (Section 31.3.4.2) + * 5. Destination vector register group for a masked vector + * instruction cannot overlap the source mask register (v0). + * (Section 31.5.3) + * risc-v unprivileged spec + */ +static bool vext_quad_narrow_check_common(DisasContext *s, int vd, int vs2, + int vm) +{ + return (s->lmul <=3D 1) && + (s->sew < MO_32) && + ((s->sew + 2) <=3D (s->cfg_ptr->elen >> 4)) && + require_align(vs2, s->lmul + 2) && + require_align(vd, s->lmul) && + require_vm(vm, vd); +} + +static bool vext_check_sq(DisasContext *s, int vd, int vs, int vm) +{ + bool ret =3D vext_quad_narrow_check_common(s, vd, vs, vm); + if (vd !=3D vs) { + ret &=3D require_noover(vd, s->lmul, vs, s->lmul + 2); + } + return ret; +} + /* * Check function for vector reduction instructions. * --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182465; cv=none; d=zohomail.com; s=zohoarc; b=HVFXuSDuaBnMQHF9x6lva9ibDjARV4n9n7VBSdPvKHU0AoqOygIYumGRa0tZjE+uKpe3AUFU/oewGj3trOeOCJxha31R7S7py6i+qTsJ2biASWJP/2OM5dg5zfiPoK4QdQyRgpCZVFPpTHNjrkA7adn+uRguYx6bCAtTdO2uS1c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182465; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NKFOVd1x1tdBqkVfLTFpz+52PeGKZ9TXVu5yfqKIdwY=; b=jlxxyu8rq7yULl1hwoLOf2U667T3hfFwhYCn7vOKyKqiw2zq2GuTrbCOWwrAednWiCSmWLRZ37rpENlSPZ4LwCGt4x6yxa6MIELZxizzBPfiZXHt/ylx8du153PZLW3Ck/QvDPKFRlpsphuMcuBEyoq/pR/SWAiY+aQdDRgTFyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182465690766.0873412197861; Tue, 3 Feb 2026 21:21:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVHx-0007o8-CJ; Wed, 04 Feb 2026 00:18:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHr-0007ci-Pl for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:48 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHq-00083g-Dn for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:47 -0500 Received: by mail-pj1-x1031.google.com with SMTP id 98e67ed59e1d1-352e2156450so3078958a91.3 for ; Tue, 03 Feb 2026 21:18:45 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Tue, 03 Feb 2026 21:18:43 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou , Alistair Francis Subject: [PATCH v3 13/19] target/riscv: Expose Zvfofp8min properity Date: Wed, 4 Feb 2026 13:17:49 +0800 Message-ID: <20260204051756.667397-14-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260204051756.667397-1-max.chou@sifive.com> References: <20260204051756.667397-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=max.chou@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1770182467107154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 36fddce5bf..c8cb3d021d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1381,6 +1381,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), MULTI_EXT_CFG_BOOL("x-zvfbfa", ext_zvfbfa, false), =20 + /* Zvfofp8min extension for OFP8 conversion */ + MULTI_EXT_CFG_BOOL("x-zvfofp8min", ext_zvfofp8min, false), + { }, }; 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Signed-off-by: Max Chou Reviewed-by: Chao Liu --- disas/riscv.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 85cd2a9c2a..daffe9917f 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -984,6 +984,9 @@ typedef enum { rv_op_ssamoswap_d =3D 953, rv_op_c_sspush =3D 954, rv_op_c_sspopchk =3D 955, + rv_op_vfncvtbf16_sat_f_f_w =3D 956, + rv_op_vfncvt_f_f_q =3D 957, + rv_op_vfncvt_sat_f_f_q =3D 958, } rv_op; =20 /* register names */ @@ -2254,6 +2257,9 @@ const rv_opcode_data rvi_opcode_data[] =3D { rv_op_sspush, 0 }, { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk, rv_op_sspopchk, 0 }, + { "vfncvtbf16.sat.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, = 0 }, + { "vfncvt.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vfncvt.sat.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -3630,7 +3636,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_is= a isa) case 21: op =3D rv_op_vfncvt_rod_f_f_w; break; case 22: op =3D rv_op_vfncvt_rtz_xu_f_w; break; case 23: op =3D rv_op_vfncvt_rtz_x_f_w; break; + case 25: op =3D rv_op_vfncvt_f_f_q; break; + case 27: op =3D rv_op_vfncvt_sat_f_f_q; break; case 29: op =3D rv_op_vfncvtbf16_f_f_w; break; + case 31: op =3D rv_op_vfncvtbf16_sat_f_f_w; break; } break; case 19: --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182351; cv=none; d=zohomail.com; s=zohoarc; b=BCYbZdeMFzOFtpa5q1DsIBDBtLF1r1f2gUiBur7XyYtJih3rxiuxzZAPgrEuIcyaQxQul2XwknvbHP+4w5OVOkOE2vFoXDN9SgkRCRYUr/Rv/Hpd6wZ9EWXVkw+jq/FriDZuyMfQAi14iXTht3UZ7XZjip43hhsX7wBA0aUchcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182351; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ATVqaM7ZW01f8u/zPmOMSZFgIAA3aDS5ix/aVxS3Tys=; b=fCiG5kE7zSLSVETJUt6rjnbmxhEMy+MGCm41Fch/rt87qwYZXinQYMmegXDNUFneI1dvYrTGxaxylO8OCIkWfdKd8Gwou/rB1Zj9tt+l/tV0WJXlLq5wXZ23jvqDpTLaJzXCfPA3mVHnNQa/sMRj762sPgTQNmGjqgEfR3Nfs5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182351920223.24212961296075; Tue, 3 Feb 2026 21:19:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVHy-0007oh-3A; Wed, 04 Feb 2026 00:18:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHw-0007mw-LU for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:52 -0500 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHv-00085R-29 for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:52 -0500 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-3545cf80e1dso1643312a91.2 for ; Tue, 03 Feb 2026 21:18:50 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/tcg/tcg-cpu.c | 5 +++++ 3 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c8cb3d021d..7823508615 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvfofp4min, PRIV_VERSION_1_12_0, ext_zvfofp4min), ISA_EXT_DATA_ENTRY(zvfofp8min, PRIV_VERSION_1_12_0, ext_zvfofp8min), ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 59302894af..353a932c36 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -104,6 +104,7 @@ BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) BOOL_FIELD(ext_zvfhmin) +BOOL_FIELD(ext_zvfofp4min) BOOL_FIELD(ext_zvfofp8min) BOOL_FIELD(ext_smaia) BOOL_FIELD(ext_ssaia) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ba89436f13..b1097e55a3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -715,6 +715,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + if (cpu->cfg.ext_zvfofp4min && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfofp4min extension depends on Zve32f extension= "); + return; + } + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { error_setg(errp, "Zvfh extensions requires Zfhmin extension"); return; --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182449; cv=none; d=zohomail.com; s=zohoarc; b=Gsj8JXK2uKIwQ6HaU6rcvjhYZMe0zTVXMRf+qh4YCxfaHTNeCjcatyoBHlXrpUC7Tjq+Kmc+a53muJXjwMKs2KApjK7tiee7vHUfqHau1EMbrOVvHN5jdbiwefMxu0Kqm6vGjZoMWPEUx4xf3AHB8xEirhclK2leIhdBhtvOoY8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182449; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/7RJutSKn1k65hDY8Ig9jUscMyGWjNCtLo7Y1bHL9Eo=; b=mk7+JClxG/65HKO6SXdtlD9ANSu44+jS2qAueuVw8dieE26qYukSUh5KNytPi2deyIGPQlImzNycbCkEe5ldYxTe/c9iAsBvi97uU7G9AtoRoBLDKGrlfN0N2ffXYOHZDuZn/lyd6wf2w+uCMupWRvSM5Ez40xEH6CxEHooQ0F4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182449941315.6427057150938; Tue, 3 Feb 2026 21:20:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVI1-0007yf-EZ; Wed, 04 Feb 2026 00:18:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVHz-0007v0-Oh for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:55 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVHy-00086R-7V for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:18:55 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-352e2156450so3079012a91.3 for ; Tue, 03 Feb 2026 21:18:53 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/cpu.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7823508615..87827441d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2520,6 +2520,15 @@ static RISCVCPUImpliedExtsRule ZVFOFP8MIN_IMPLIED = =3D { }, }; =20 +static RISCVCPUImpliedExtsRule ZVFOFP4MIN_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfofp4min), + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + static RISCVCPUImpliedExtsRule ZVKN_IMPLIED =3D { .ext =3D CPU_CFG_OFFSET(ext_zvkn), .implied_multi_exts =3D { @@ -2648,9 +2657,10 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rul= es[] =3D { &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, - &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVFOFP8MIN_IMPLIED, - &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, - &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVFOFP4MIN_IMPLIED, + &ZVFOFP8MIN_IMPLIED, &ZVKN_IMPLIED, &ZVKNC_IMPLIED, + &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, + &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, &SSCTR_IMPLIED, NULL }; --=20 2.52.0 From nobody Sat Feb 7 05:48:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1770182455; cv=none; d=zohomail.com; s=zohoarc; b=a0XY4JlDJmNPmt1zGgCUASAXbJ33Uf1ws6p2GTvQdNErmCV2uLaNIxfM/NuZ5ab9zty7Cm5oqiPXfxnwqmplD+ZMmtu7wuKNd06lMn4QfTUG7fKECgFFWyUkBwFmop4NNj1xcKZV4PucZbhZpi8Xkj4A6RFld1UU/RjtIQU0Ds8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770182455; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OK/3yavGotR2xRXzhalL1d9lbHkE0ldapRXCJj6e1js=; b=grM3QvTvlZE15HzLOMP5Q215Tpn9dL28mseDYJjx5sXezFfkL7sP1h943+hcF950C2+BDFemKzOOksjWRX4GMhQEGOMkYYWp4gsN/ika3PCi4je0p3LT8iRvfKnP8r35Rzgwpfx+Zgj+5v4eGEoLsIaCPUI4YF7QH7ITsOfrTCE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770182455519671.8934695116419; Tue, 3 Feb 2026 21:20:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnVI6-000828-2V; Wed, 04 Feb 2026 00:19:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnVI4-00080v-AZ for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:19:00 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vnVI1-00086y-KB for qemu-devel@nongnu.org; Wed, 04 Feb 2026 00:19:00 -0500 Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-34c708702dfso3488950a91.1 for ; Tue, 03 Feb 2026 21:18:57 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. 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Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvofp4.c.inc | 43 ++++++++++++++++++++++ target/riscv/translate.c | 1 + target/riscv/vector_helper.c | 33 +++++++++++++++++ 5 files changed, 83 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvofp4.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 356c24d9fb..162303fb6c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1259,6 +1259,9 @@ DEF_HELPER_5(vfncvt_f_f_q_ofp8e5m2, void, ptr, ptr, p= tr, env, i32) DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e4m3, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_sat_f_f_q_ofp8e5m2, void, ptr, ptr, ptr, env, i32) =20 +/* OFP4 function */ +DEF_HELPER_5(vfext_vf2, void, ptr, ptr, ptr, env, i32) + /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f2b413c7d4..c58223ebd8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -754,6 +754,9 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111 = @r2_vm vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm =20 +# Zvfofp4min Extension +vfext_vf2 010010 . ..... 10110 010 ..... 1010111 @r2_vm + vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11 vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10 vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvofp4.c.inc b/target/riscv/insn= _trans/trans_rvofp4.c.inc new file mode 100644 index 0000000000..0fb5d7d534 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvofp4.c.inc @@ -0,0 +1,43 @@ +/* + * RISC-V translation routines for the OFP4 Standard Extensions. + * + * Copyright (C) 2025 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +static bool vext_zvfofp4min_check(DisasContext *s, arg_rmr *a) +{ + return s->cfg_ptr->ext_zvfofp4min && + (s->sew =3D=3D MO_8) && + vext_check_altfmt(s, -1) && + (s->lmul >=3D -2) && + require_rvv(s) && + vext_check_isa_ill(s) && + (a->rd !=3D a->rs2) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul - 1) && + require_vm(a->vm, a->rd) && + require_noover(a->rd, s->lmul, a->rs2, s->lmul - 1); +} + +static bool trans_vfext_vf2(DisasContext *s, arg_rmr *a) +{ + if (vext_zvfofp4min_check(s, a)) { + uint32_t data =3D 0; + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), tcg_env, + s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, data, + gen_helper_vfext_vf2); + tcg_gen_movi_tl(cpu_vstart, 0); + finalize_rvv_inst(s); + + return true; + } + return false; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 137022d7fb..bf403785b5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1220,6 +1220,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" #include "insn_trans/trans_rvofp8.c.inc" +#include "insn_trans/trans_rvofp4.c.inc" #include "decode-xthead.c.inc" #include "decode-xmips.c.inc" #include "insn_trans/trans_xthead.c.inc" diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 418212973d..a87728f130 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -5121,6 +5121,7 @@ RVVCALL(OPFVV1, vfncvt_sat_f_f_q_ofp8e5m2, QOP_UU_B, = H1, H4, GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e4m3, 1) GEN_VEXT_V_ENV(vfncvt_sat_f_f_q_ofp8e5m2, 1) =20 +/* Zvfofp4min: vfext.vf2 - OFP4 E2M1 to OFP8 E4M3 conversion */ /* * Vector Reduction Operations */ @@ -5920,3 +5921,35 @@ GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, = H4) GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1) GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2) GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1) + + +void HELPER(vfext_vf2)(void *vd, void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + float_status fp_status =3D env->fp_status; + uint32_t vl =3D env->vl; + uint32_t vm =3D vext_vm(desc); + uint32_t esz =3D sizeof(uint8_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + VSTART_CHECK_EARLY_EXIT(env, vl); + + for (i =3D env->vstart; i < vl; ++i) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + + uint8_t input =3D *((uint8_t *)vs2 + H1((i % 2 ? i - 1 : i) / 2)); + input =3D (i % 2) ? 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Tue, 03 Feb 2026 21:18:58 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Aurelien Jarno , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Max Chou , Alistair Francis Subject: [PATCH v3 18/19] target/riscv: Expose Zvfofp4min properity Date: Wed, 4 Feb 2026 13:17:54 +0800 Message-ID: <20260204051756.667397-19-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260204051756.667397-1-max.chou@sifive.com> References: <20260204051756.667397-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=max.chou@sifive.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1770182454962154100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 87827441d3..d2f25cd14b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1384,6 +1384,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { =20 /* Zvfofp8min extension for OFP8 conversion */ MULTI_EXT_CFG_BOOL("x-zvfofp8min", ext_zvfofp8min, false), + /* Zvfofp4min extension for OFP4 conversion */ + MULTI_EXT_CFG_BOOL("x-zvfofp4min", ext_zvfofp4min, false), =20 { }, }; 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Signed-off-by: Max Chou Reviewed-by: Chao Liu --- disas/riscv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index daffe9917f..9abf86f2d7 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -987,6 +987,7 @@ typedef enum { rv_op_vfncvtbf16_sat_f_f_w =3D 956, rv_op_vfncvt_f_f_q =3D 957, rv_op_vfncvt_sat_f_f_q =3D 958, + rv_op_vfext_vf2 =3D 959, } rv_op; =20 /* register names */ @@ -2260,6 +2261,7 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "vfncvtbf16.sat.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, = 0 }, { "vfncvt.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, { "vfncvt.sat.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vfext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -3715,6 +3717,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 12: op =3D rv_op_vclz_v; break; case 13: op =3D rv_op_vctz_v; break; case 14: op =3D rv_op_vcpop_v; break; + case 22: op =3D rv_op_vfext_vf2; break; } break; case 20: --=20 2.52.0