From nobody Sun Feb 8 22:21:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770108897; cv=none; d=zohomail.com; s=zohoarc; b=FcXIqaOa155BKlp5e7BIfKKtpY/ByuZ/jvPhhBj6WfohNjTi0P2x9DJS2hSpRLIANQlpWgI3sZMRBZBvUBMyqlraPXBauRPcHRZ//Xf4fkxpAeHVtjFQRUfohWACBt72yTKYfsKqvKrwd2WxicAlAxytnL5FrHniSz10CbagQxc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770108897; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=wPTh9V27BswV6XgXuBz2u78u2qfQ/uC4tCWVwzJiWtM=; b=Hm9JKjquuccLFtQsDkGoWaq7P04lc6gl0UMVDD/tTp1YRo7os8AjFTFYWV1gs06VuB0ItRFMvN0+fmpM6hcWGFlxu7EyczBXN6N2tzaYdBb/6sIJwnRe43Z/7ObUawO/sACaRM9cr2H+o/HbZx507qZqQhcwbEX5pybmtCHEsjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770108897628920.1868477204725; Tue, 3 Feb 2026 00:54:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnC9g-0004p5-Fl; Tue, 03 Feb 2026 03:53:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnC9f-0004kd-5t; Tue, 03 Feb 2026 03:53:03 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnC9d-0002qU-NH; Tue, 03 Feb 2026 03:53:02 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 3 Feb 2026 16:52:33 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 3 Feb 2026 16:52:33 +0800 To: , , Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "open list:All patches CC here" , "open list:ARM TCG CPUs" CC: , , , Patrick Venture Subject: [PATCH v2 08/20] hw/i3c/dw-i3c: Add register RO field masks Date: Tue, 3 Feb 2026 16:52:08 +0800 Message-ID: <20260203085229.1543287-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> References: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770108899211154101 Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Adds read-only register masks for the DwC I3C controller. Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Reviewed-by: Jamin Lin --- hw/i3c/dw-i3c.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index 7bb33c7a9e..02fa9b3c00 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -296,6 +296,45 @@ static const uint32_t dw_i3c_resets[DW_I3C_NR_REGS] = =3D { [R_SLAVE_CONFIG] =3D 0x00000023, }; =20 +static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] =3D { + [R_DEVICE_CTRL] =3D 0x04fffe00, + [R_DEVICE_ADDR] =3D 0x7f807f80, + [R_HW_CAPABILITY] =3D 0xffffffff, + [R_IBI_QUEUE_STATUS] =3D 0xffffffff, + [R_DATA_BUFFER_THLD_CTRL] =3D 0xf8f8f8f8, + [R_IBI_QUEUE_CTRL] =3D 0xfffffff0, + [R_RESET_CTRL] =3D 0xffffffc0, + [R_SLV_EVENT_CTRL] =3D 0xffffff3f, + [R_INTR_STATUS] =3D 0xffff809f, + [R_INTR_STATUS_EN] =3D 0xffff8080, + [R_INTR_SIGNAL_EN] =3D 0xffff8080, + [R_INTR_FORCE] =3D 0xffff8000, + [R_QUEUE_STATUS_LEVEL] =3D 0xffffffff, + [R_DATA_BUFFER_STATUS_LEVEL] =3D 0xffffffff, + [R_PRESENT_STATE] =3D 0xffffffff, + [R_CCC_DEVICE_STATUS] =3D 0xffffffff, + [R_I3C_VER_ID] =3D 0xffffffff, + [R_I3C_VER_TYPE] =3D 0xffffffff, + [R_DEVICE_ADDR_TABLE_POINTER] =3D 0xffffffff, + [R_DEV_CHAR_TABLE_POINTER] =3D 0xffcbffff, + [R_SLV_PID_VALUE] =3D 0xffff0fff, + [R_SLV_CHAR_CTRL] =3D 0xffffffff, + [A_VENDOR_SPECIFIC_REG_POINTER] =3D 0xffffffff, + [R_SLV_MAX_LEN] =3D 0xffffffff, + [R_MAX_READ_TURNAROUND] =3D 0xffffffff, + [R_MAX_DATA_SPEED] =3D 0xffffffff, + [R_SLV_INTR_REQ] =3D 0xfffffff0, + [R_SLV_TSX_SYMBL_TIMING] =3D 0xffffffc0, + [R_DEVICE_CTRL_EXTENDED] =3D 0xfffffff8, + [R_SCL_I3C_OD_TIMING] =3D 0xff00ff00, + [R_SCL_I3C_PP_TIMING] =3D 0xff00ff00, + [R_SCL_I2C_FMP_TIMING] =3D 0xff000000, + [R_SCL_EXT_TERMN_LCNT_TIMING] =3D 0x0000fff0, + [R_BUS_IDLE_TIMING] =3D 0xfff00000, + [R_EXTENDED_CAPABILITY] =3D 0xffffffff, + [R_SLAVE_CONFIG] =3D 0xffffffff, +}; + static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) { DWI3C *s =3D DW_I3C(opaque); @@ -324,6 +363,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, u= int64_t value, =20 trace_dw_i3c_write(s->id, offset, value); =20 + value &=3D ~dw_i3c_ro[addr]; switch (addr) { case R_HW_CAPABILITY: case R_RESPONSE_QUEUE_PORT: --=20 2.43.0