From nobody Sat Feb 7 07:15:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770108888; cv=none; d=zohomail.com; s=zohoarc; b=GZM7QTjQQRyvHlm8cUzIhTCBtdnWurvQjsU85ux2mP/C2HqZTcJ9VsiaCl0+SOQ4B4TZv6DKwjyDPKwN6imUWPvScOyuIi11ZOamYvuaZgkYWZbJ2Z+ylATo5p0BIw1+Izujus4gyhknnV9fv4zCP4XhXmIe+AJ3wt33hYT7MrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770108888; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=gFn6ptiu6rBFzhJJ8o5tPXhJ3Zigu1qwvKw6tT9lLtQ=; b=Yp1Qz0asVW1J7nO0ZYCH9uwWXCc9Xu9uYrkF9jv6Z3kHJ/B5vAoF+fTNLmS92kUOzKOhEAePJArA+gHdZainbpowCjzx/zcNJ9Co+iYA/RrsXsaOlnHNu/RyXQPXpkJN3SQs7+/Y42EVokLb8QB4HGrwUuQ3AGb1VxKQGl6Eecw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770108888057676.692258117591; Tue, 3 Feb 2026 00:54:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnC9b-0004cq-6g; Tue, 03 Feb 2026 03:52:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnC9Y-0004bh-D7; Tue, 03 Feb 2026 03:52:56 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnC9X-0002qU-0O; Tue, 03 Feb 2026 03:52:56 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 3 Feb 2026 16:52:31 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 3 Feb 2026 16:52:31 +0800 To: , , Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "open list:All patches CC here" , "open list:ARM TCG CPUs" CC: , , , Patrick Venture Subject: [PATCH v2 05/20] hw/i3c/aspeed_i3c: Add more register fields Date: Tue, 3 Feb 2026 16:52:05 +0800 Message-ID: <20260203085229.1543287-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> References: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770108888970154100 Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Adds the rest of the Aspeed I3C controller register fields. Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Reviewed-by: Jamin Lin --- hw/i3c/aspeed_i3c.c | 54 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index b0844d4da2..f0352aaca0 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -21,28 +21,58 @@ /* I3C Controller Registers */ REG32(I3C1_REG0, 0x10) REG32(I3C1_REG1, 0x14) - FIELD(I3C1_REG1, I2C_MODE, 0, 1) - FIELD(I3C1_REG1, SA_EN, 15, 1) + FIELD(I3C1_REG1, I2C_MODE, 0, 1) + FIELD(I3C1_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C1_REG1, ACT_MODE, 2, 2) + FIELD(I3C1_REG1, PENDING_INT, 4, 4) + FIELD(I3C1_REG1, SA, 8, 7) + FIELD(I3C1_REG1, SA_EN, 15, 1) + FIELD(I3C1_REG1, INST_ID, 16, 4) REG32(I3C2_REG0, 0x20) REG32(I3C2_REG1, 0x24) - FIELD(I3C2_REG1, I2C_MODE, 0, 1) - FIELD(I3C2_REG1, SA_EN, 15, 1) + FIELD(I3C2_REG1, I2C_MODE, 0, 1) + FIELD(I3C2_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C2_REG1, ACT_MODE, 2, 2) + FIELD(I3C2_REG1, PENDING_INT, 4, 4) + FIELD(I3C2_REG1, SA, 8, 7) + FIELD(I3C2_REG1, SA_EN, 15, 1) + FIELD(I3C2_REG1, INST_ID, 16, 4) REG32(I3C3_REG0, 0x30) REG32(I3C3_REG1, 0x34) - FIELD(I3C3_REG1, I2C_MODE, 0, 1) - FIELD(I3C3_REG1, SA_EN, 15, 1) + FIELD(I3C3_REG1, I2C_MODE, 0, 1) + FIELD(I3C3_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C3_REG1, ACT_MODE, 2, 2) + FIELD(I3C3_REG1, PENDING_INT, 4, 4) + FIELD(I3C3_REG1, SA, 8, 7) + FIELD(I3C3_REG1, SA_EN, 15, 1) + FIELD(I3C3_REG1, INST_ID, 16, 4) REG32(I3C4_REG0, 0x40) REG32(I3C4_REG1, 0x44) - FIELD(I3C4_REG1, I2C_MODE, 0, 1) - FIELD(I3C4_REG1, SA_EN, 15, 1) + FIELD(I3C4_REG1, I2C_MODE, 0, 1) + FIELD(I3C4_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C4_REG1, ACT_MODE, 2, 2) + FIELD(I3C4_REG1, PENDING_INT, 4, 4) + FIELD(I3C4_REG1, SA, 8, 7) + FIELD(I3C4_REG1, SA_EN, 15, 1) + FIELD(I3C4_REG1, INST_ID, 16, 4) REG32(I3C5_REG0, 0x50) REG32(I3C5_REG1, 0x54) - FIELD(I3C5_REG1, I2C_MODE, 0, 1) - FIELD(I3C5_REG1, SA_EN, 15, 1) + FIELD(I3C5_REG1, I2C_MODE, 0, 1) + FIELD(I3C5_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C5_REG1, ACT_MODE, 2, 2) + FIELD(I3C5_REG1, PENDING_INT, 4, 4) + FIELD(I3C5_REG1, SA, 8, 7) + FIELD(I3C5_REG1, SA_EN, 15, 1) + FIELD(I3C5_REG1, INST_ID, 16, 4) REG32(I3C6_REG0, 0x60) REG32(I3C6_REG1, 0x64) - FIELD(I3C6_REG1, I2C_MODE, 0, 1) - FIELD(I3C6_REG1, SA_EN, 15, 1) + FIELD(I3C6_REG1, I2C_MODE, 0, 1) + FIELD(I3C6_REG1, SLV_TEST_MODE, 1, 1) + FIELD(I3C6_REG1, ACT_MODE, 2, 2) + FIELD(I3C6_REG1, PENDING_INT, 4, 4) + FIELD(I3C6_REG1, SA, 8, 7) + FIELD(I3C6_REG1, SA_EN, 15, 1) + FIELD(I3C6_REG1, INST_ID, 16, 4) =20 static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int si= ze) { --=20 2.43.0