From nobody Sat Feb 7 07:15:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770108914; cv=none; d=zohomail.com; s=zohoarc; b=gDU+7HcggeVoUEHTW73oQkAjupn45/xwZdo1rQLX/wlci2kDQvNbqSKM6xyIiqyeaRPW/H05PHKvQYxXhWO1p44PtkiRn3Iz8fNgSATVdybPP6GMf/iBAKQxlGFsv6UH+BmXgYclHswK0vep9xdEBb9MqWqwNDtxspVHq8ewX50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770108914; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=dn3N9ToP+Eg3iDkoj38WlDx/UWCnbm2jAWElOUSKJEM=; b=QUUiAae53afG8+DHlAPceoukd/UQpVz7p1ixE0uAfB1nwJVEEm4RPUeYaqB/ewnWSHnsQ1JmCdT/Pobl9ye2u2oZs1RgpnTemmajCZi/dnvff/Sb9qFaYpszcF1FhDbkAgIeGHJFDawpMYAGaDfqu3YmUu+FPMfyGU2tdHOGKUM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770108914552863.1667689129616; Tue, 3 Feb 2026 00:55:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnCB4-0006DH-FF; Tue, 03 Feb 2026 03:54:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnCAb-0005OJ-P4; Tue, 03 Feb 2026 03:54:05 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnCAX-0003Po-Vb; Tue, 03 Feb 2026 03:54:01 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 3 Feb 2026 16:52:37 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 3 Feb 2026 16:52:37 +0800 To: , , Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "open list:All patches CC here" , "open list:ARM TCG CPUs" CC: , , , Titus Rwantare , "Patrick Venture" Subject: [PATCH v2 17/20] hw/i3c: Add Mock target Date: Tue, 3 Feb 2026 16:52:17 +0800 Message-ID: <20260203085229.1543287-18-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> References: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770108915416158500 Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Adds a simple i3c device to be used for testing in lieu of a real device. The mock target supports the following features: - A buffer that users can read and write to. - CCC support for commonly used CCCs when probing devices on an I3C bus. - IBI sending upon receiving a user-defined byte. Signed-off-by: Joe Komlodi Reviewed-by: Titus Rwantare Reviewed-by: Patrick Venture Reviewed-by: Jamin Lin --- include/hw/i3c/mock-i3c-target.h | 52 ++++++ hw/i3c/mock-i3c-target.c | 311 +++++++++++++++++++++++++++++++ hw/i3c/Kconfig | 10 + hw/i3c/meson.build | 1 + hw/i3c/trace-events | 9 + 5 files changed, 383 insertions(+) create mode 100644 include/hw/i3c/mock-i3c-target.h create mode 100644 hw/i3c/mock-i3c-target.c diff --git a/include/hw/i3c/mock-i3c-target.h b/include/hw/i3c/mock-i3c-tar= get.h new file mode 100644 index 0000000000..7ac55a3179 --- /dev/null +++ b/include/hw/i3c/mock-i3c-target.h @@ -0,0 +1,52 @@ +#ifndef MOCK_I3C_TARGET_H_ +#define MOCK_I3C_TARGET_H_ + +/* + * Mock I3C Device + * + * Copyright (c) 2025 Google LLC + * + * The mock I3C device can be thought of as a simple EEPROM. It has a buff= er, + * and the pointer in the buffer is reset to 0 on an I3C STOP. + * To write to the buffer, issue a private write and send data. + * To read from the buffer, issue a private read. + * + * The mock target also supports sending target interrupt IBIs. + * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number,= and + * send that number in a private transaction. The mock target will issue a= n IBI + * after 1 second. + * + * It also supports a handful of CCCs that are typically used when probing= I3C + * devices. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "hw/i3c/i3c.h" + +#define TYPE_MOCK_I3C_TARGET "mock-i3c-target" +OBJECT_DECLARE_SIMPLE_TYPE(MockI3cTargetState, MOCK_I3C_TARGET) + +struct MockI3cTargetState { + I3CTarget i3c; + + /* General device state */ + bool can_ibi; + QEMUTimer qtimer; + size_t p_buf; + uint8_t *buf; + + /* For Handing CCCs. */ + bool in_ccc; + I3CCCC curr_ccc; + uint8_t ccc_byte_offset; + + struct { + uint32_t buf_size; + uint8_t ibi_magic; + } cfg; +}; + +#endif diff --git a/hw/i3c/mock-i3c-target.c b/hw/i3c/mock-i3c-target.c new file mode 100644 index 0000000000..e540a6c2f7 --- /dev/null +++ b/hw/i3c/mock-i3c-target.c @@ -0,0 +1,311 @@ +/* + * Mock I3C Device + * + * Copyright (c) 2025 Google LLC + * + * The mock I3C device can be thought of as a simple EEPROM. It has a buff= er, + * and the pointer in the buffer is reset to 0 on an I3C STOP. + * To write to the buffer, issue a private write and send data. + * To read from the buffer, issue a private read. + * + * The mock target also supports sending target interrupt IBIs. + * To issue an IBI, set the 'ibi-magic-num' property to a non-zero number,= and + * send that number in a private transaction. The mock target will issue a= n IBI + * after 1 second. + * + * It also supports a handful of CCCs that are typically used when probing= I3C + * devices. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "trace.h" +#include "hw/i3c/i3c.h" +#include "hw/i3c/mock-i3c-target.h" +#include "hw/core/irq.h" +#include "hw/core/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/module.h" + +#ifndef MOCK_I3C_TARGET_DEBUG +#define MOCK_I3C_TARGET_DEBUG 0 +#endif + +#define DB_PRINTF(...) do { \ + if (MOCK_I3C_TARGET_DEBUG) { \ + qemu_log("%s: ", __func__); \ + qemu_log(__VA_ARGS__); \ + } \ + } while (0) + +#define IBI_DELAY_NS (1 * 1000 * 1000) + +static uint32_t mock_i3c_target_rx(I3CTarget *i3c, uint8_t *data, + uint32_t num_to_read) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c); + uint32_t i; + + /* Bounds check. */ + if (s->p_buf =3D=3D s->cfg.buf_size) { + return 0; + } + + for (i =3D 0; i < num_to_read; i++) { + data[i] =3D s->buf[s->p_buf]; + trace_mock_i3c_target_rx(data[i]); + s->p_buf++; + if (s->p_buf =3D=3D s->cfg.buf_size) { + break; + } + } + + /* Return the number of bytes we're sending to the controller. */ + return i; +} + +static void mock_i3c_target_ibi_timer_start(MockI3cTargetState *s) +{ + int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + timer_mod(&s->qtimer, now + IBI_DELAY_NS); +} + +static int mock_i3c_target_tx(I3CTarget *i3c, const uint8_t *data, + uint32_t num_to_send, uint32_t *num_sent) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c); + int ret; + uint32_t to_write; + + if (s->cfg.ibi_magic && num_to_send =3D=3D 1 && s->cfg.ibi_magic =3D= =3D *data) { + mock_i3c_target_ibi_timer_start(s); + return 0; + } + + /* Bounds check. */ + if (num_to_send + s->p_buf > s->cfg.buf_size) { + to_write =3D s->cfg.buf_size - s->p_buf; + ret =3D -1; + } else { + to_write =3D num_to_send; + ret =3D 0; + } + for (uint32_t i =3D 0; i < to_write; i++) { + trace_mock_i3c_target_tx(data[i]); + s->buf[s->p_buf] =3D data[i]; + s->p_buf++; + } + return ret; +} + +static int mock_i3c_target_event(I3CTarget *i3c, enum I3CEvent event) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c); + + trace_mock_i3c_target_event(event); + if (event =3D=3D I3C_STOP) { + s->in_ccc =3D false; + s->curr_ccc =3D 0; + s->ccc_byte_offset =3D 0; + s->p_buf =3D 0; + } + + return 0; +} + +static int mock_i3c_target_handle_ccc_read(I3CTarget *i3c, uint8_t *data, + uint32_t num_to_read, + uint32_t *num_read) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c); + + switch (s->curr_ccc) { + case I3C_CCCD_GETMXDS: + /* Default data rate for I3C. */ + while (s->ccc_byte_offset < num_to_read) { + if (s->ccc_byte_offset >=3D 2) { + break; + } + data[s->ccc_byte_offset] =3D 0; + *num_read =3D s->ccc_byte_offset; + s->ccc_byte_offset++; + } + break; + case I3C_CCCD_GETCAPS: + /* Support I3C version 1.1.x, no other features. */ + while (s->ccc_byte_offset < num_to_read) { + if (s->ccc_byte_offset >=3D 2) { + break; + } + if (s->ccc_byte_offset =3D=3D 0) { + data[s->ccc_byte_offset] =3D 0; + } else { + data[s->ccc_byte_offset] =3D 0x01; + } + *num_read =3D s->ccc_byte_offset; + s->ccc_byte_offset++; + } + break; + case I3C_CCCD_GETMWL: + case I3C_CCCD_GETMRL: + /* MWL/MRL is MSB first. */ + while (s->ccc_byte_offset < num_to_read) { + if (s->ccc_byte_offset >=3D 2) { + break; + } + data[s->ccc_byte_offset] =3D (s->cfg.buf_size & + (0xff00 >> (s->ccc_byte_offset * 8= ))) >> + (8 - (s->ccc_byte_offset * 8)); + s->ccc_byte_offset++; + *num_read =3D num_to_read; + } + break; + case I3C_CCC_ENTDAA: + case I3C_CCCD_GETPID: + case I3C_CCCD_GETBCR: + case I3C_CCCD_GETDCR: + /* Nothing to do. */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Unhandled CCC 0x%.2x\n", s->curr_c= cc); + return -1; + } + + trace_mock_i3c_target_handle_ccc_read(*num_read, num_to_read); + return 0; +} + +static int mock_i3c_target_handle_ccc_write(I3CTarget *i3c, const uint8_t = *data, + uint32_t num_to_send, + uint32_t *num_sent) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c); + + if (!s->curr_ccc) { + s->in_ccc =3D true; + s->curr_ccc =3D *data; + trace_mock_i3c_target_new_ccc(s->curr_ccc); + } + + *num_sent =3D 1; + switch (s->curr_ccc) { + case I3C_CCC_ENEC: + case I3C_CCCD_ENEC: + s->can_ibi =3D true; + break; + case I3C_CCC_DISEC: + case I3C_CCCD_DISEC: + s->can_ibi =3D false; + break; + case I3C_CCC_ENTDAA: + case I3C_CCC_SETAASA: + case I3C_CCC_RSTDAA: + case I3C_CCCD_SETDASA: + case I3C_CCCD_GETPID: + case I3C_CCCD_GETBCR: + case I3C_CCCD_GETDCR: + case I3C_CCCD_GETMWL: + case I3C_CCCD_GETMRL: + case I3C_CCCD_GETMXDS: + case I3C_CCCD_GETCAPS: + /* Nothing to do. */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Unhandled CCC 0x%.2x\n", s->curr_c= cc); + return -1; + } + + trace_mock_i3c_target_handle_ccc_write(*num_sent, num_to_send); + return 0; +} + +static void mock_i3c_target_do_ibi(MockI3cTargetState *s) +{ + if (!s->can_ibi) { + DB_PRINTF("IBIs disabled by controller"); + return; + } + + trace_mock_i3c_target_do_ibi(s->i3c.address, true); + int nack =3D i3c_target_send_ibi(&s->i3c, s->i3c.address, /*is_recv=3D= */true); + /* Getting NACKed isn't necessarily an error, just print it out. */ + if (nack) { + DB_PRINTF("NACKed from controller when sending target interrupt.\n= "); + } + nack =3D i3c_target_ibi_finish(&s->i3c, 0x00); + if (nack) { + DB_PRINTF("NACKed from controller when finishing target interrupt.= \n"); + } +} + +static void mock_i3c_target_timer_elapsed(void *opaque) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(opaque); + timer_del(&s->qtimer); + mock_i3c_target_do_ibi(s); +} + +static void mock_i3c_target_reset(I3CTarget *i3c) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(i3c); + s->can_ibi =3D false; +} + +static void mock_i3c_target_realize(DeviceState *dev, Error **errp) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(dev); + s->buf =3D g_new0(uint8_t, s->cfg.buf_size); + mock_i3c_target_reset(&s->i3c); +} + +static void mock_i3c_target_init(Object *obj) +{ + MockI3cTargetState *s =3D MOCK_I3C_TARGET(obj); + s->can_ibi =3D false; + + /* For IBIs. */ + timer_init_ns(&s->qtimer, QEMU_CLOCK_VIRTUAL, mock_i3c_target_timer_el= apsed, + s); +} + +static const Property remote_i3c_props[] =3D { + /* The size of the internal buffer. */ + DEFINE_PROP_UINT32("buf-size", MockI3cTargetState, cfg.buf_size, 0x100= ), + /* + * If the mock target receives this number, it will issue an IBI after + * 1 second. Disabled if the IBI magic number is 0. + */ + DEFINE_PROP_UINT8("ibi-magic-num", MockI3cTargetState, cfg.ibi_magic, = 0x00), +}; + +static void mock_i3c_target_class_init(ObjectClass *klass, const void *dat= a) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + I3CTargetClass *k =3D I3C_TARGET_CLASS(klass); + + dc->realize =3D mock_i3c_target_realize; + k->event =3D mock_i3c_target_event; + k->recv =3D mock_i3c_target_rx; + k->send =3D mock_i3c_target_tx; + k->handle_ccc_read =3D mock_i3c_target_handle_ccc_read; + k->handle_ccc_write =3D mock_i3c_target_handle_ccc_write; + + device_class_set_props(dc, remote_i3c_props); +} + +static const TypeInfo mock_i3c_target_info =3D { + .name =3D TYPE_MOCK_I3C_TARGET, + .parent =3D TYPE_I3C_TARGET, + .instance_size =3D sizeof(MockI3cTargetState), + .instance_init =3D mock_i3c_target_init, + .class_init =3D mock_i3c_target_class_init, +}; + +static void mock_i3c_target_register_types(void) +{ + type_register_static(&mock_i3c_target_info); +} + +type_init(mock_i3c_target_register_types) diff --git a/hw/i3c/Kconfig b/hw/i3c/Kconfig index ecec77d6fc..d5c6d4049b 100644 --- a/hw/i3c/Kconfig +++ b/hw/i3c/Kconfig @@ -3,3 +3,13 @@ config I3C =20 config DW_I3C bool + +config I3C_DEVICES + # Device group for i3c devices which can reasonably be user-plugged to= any + # board's i3c bus. + bool + +config MOCK_I3C_TARGET + bool + select I3C + default y if I3C_DEVICES diff --git a/hw/i3c/meson.build b/hw/i3c/meson.build index 83d75e7d5c..e614b18712 100644 --- a/hw/i3c/meson.build +++ b/hw/i3c/meson.build @@ -2,4 +2,5 @@ i3c_ss =3D ss.source_set() i3c_ss.add(when: 'CONFIG_I3C', if_true: files('core.c')) i3c_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_i3c.c')) i3c_ss.add(when: 'CONFIG_DW_I3C', if_true: files('dw-i3c.c')) +i3c_ss.add(when: 'CONFIG_MOCK_I3C_TARGET', if_true: files('mock-i3c-target= .c')) system_ss.add_all(when: 'CONFIG_I3C', if_true: i3c_ss) diff --git a/hw/i3c/trace-events b/hw/i3c/trace-events index 39f33d9a50..3d6dd4f7dd 100644 --- a/hw/i3c/trace-events +++ b/hw/i3c/trace-events @@ -36,3 +36,12 @@ legacy_i2c_recv(uint8_t byte) "Legacy I2C recv 0x%" PRIx8 legacy_i2c_send(uint8_t byte) "Legacy I2C send 0x%" PRIx8 legacy_i2c_start_transfer(uint8_t address, bool is_recv) "Legacy I2C START= with address 0x%" PRIx8 " is_recv=3D%d" legacy_i2c_end_transfer(void) "Legacy I2C STOP" + +# mock-target.c +mock_i3c_target_rx(uint8_t byte) "I3C mock target read 0x%" PRIx8 +mock_i3c_target_tx(uint8_t byte) "I3C mock target write 0x%" PRIx8 +mock_i3c_target_event(uint8_t event) "I3C mock target event 0x%" PRIx8 +mock_i3c_target_handle_ccc_read(uint32_t num_read, uint32_t num_to_read) "= I3C mock target read %" PRId32 "/%" PRId32 " bytes" +mock_i3c_target_new_ccc(uint8_t ccc) "I3C mock target handle CCC 0x%" PRIx8 +mock_i3c_target_handle_ccc_write(uint32_t num_sent, uint32_t num_to_send) = "I3C mock target send %" PRId32 "/%" PRId32 " bytes" +mock_i3c_target_do_ibi(uint8_t address, bool is_recv) "I3C mock target IBI= with address 0x%" PRIx8 " RnW=3D%d" --=20 2.43.0