From nobody Sun Feb 8 23:58:45 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770108872; cv=none; d=zohomail.com; s=zohoarc; b=HuZVHVko3Fikjt+V3kl/jp5xzbHFitDR0Tb5omCsaUkImLcMmRBvgPCvomPaIPfj8VhBkKbMpidb2fOdGVBpbEAzRcArPPPFO0a4dGL8Ht2ip5l3D7emn6Cp3c5x2JGU1EuGLiLCrPVRL3i8zcMN33jfFDsc5oRPZNpA+EHLuno= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770108872; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=poj/4nZiObk4oI7LUXAJrGclfQYcfWAJvdd7AUEZTic=; b=TmGnJKS1OQ/gkvB9CN0FZC1rWKNbLT1sy84QevpTLmr6yfu/JW7g7WS3Ff1Hc3p59TT4rrRhqhogVF/mdcJxKSdTYUxs2Za9qoOTKUciUyce4vL8fbvpGoss1MpInco4TAFIM6GR/flbuwfIK0XOmd/Ev/UtTENdAKuYTVNLtS0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177010887256263.01190044072496; Tue, 3 Feb 2026 00:54:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnCAz-0005eQ-FX; Tue, 03 Feb 2026 03:54:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnCAL-0005DB-7g; Tue, 03 Feb 2026 03:53:46 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnCAJ-0003Po-FT; Tue, 03 Feb 2026 03:53:44 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 3 Feb 2026 16:52:36 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 3 Feb 2026 16:52:36 +0800 To: , , Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "open list:All patches CC here" , "open list:ARM TCG CPUs" CC: , , , Titus Rwantare , "Patrick Venture" Subject: [PATCH v2 14/20] hw/i3c/dw-i3c: Add ctrl MMIO handling Date: Tue, 3 Feb 2026 16:52:14 +0800 Message-ID: <20260203085229.1543287-15-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> References: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770108874756154100 Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Adds functionality to the CTRL register. Signed-off-by: Joe Komlodi Reviewed-by: Titus Rwantare Reviewed-by: Patrick Venture Reviewed-by: Jamin Lin --- hw/i3c/dw-i3c.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index 9a0460cf31..7a1f79e10d 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -344,6 +344,8 @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] =3D { [R_SLAVE_CONFIG] =3D 0xffffffff, }; =20 +static void dw_i3c_cmd_queue_execute(DWI3C *s); + static inline bool dw_i3c_has_hdr_ts(DWI3C *s) { return ARRAY_FIELD_EX32(s->regs, HW_CAPABILITY, HDR_TS); @@ -503,6 +505,36 @@ static int dw_i3c_recv_data(DWI3C *s, bool is_i2c, uin= t8_t *data, return ret; } =20 +static void dw_i3c_ctrl_w(DWI3C *s, uint32_t val) +{ + /* + * If the user is setting I3C_RESUME, the controller was halted. + * Try and resume execution and leave the bit cleared. + */ + if (FIELD_EX32(val, DEVICE_CTRL, I3C_RESUME)) { + dw_i3c_cmd_queue_execute(s); + val =3D FIELD_DP32(val, DEVICE_CTRL, I3C_RESUME, 0); + } + /* + * I3C_ABORT being set sends an I3C STOP. It's cleared when the STOP is + * sent. + */ + if (FIELD_EX32(val, DEVICE_CTRL, I3C_ABORT)) { + dw_i3c_end_transfer(s, /*is_i2c=3D*/true); + dw_i3c_end_transfer(s, /*is_i2c=3D*/false); + val =3D FIELD_DP32(val, DEVICE_CTRL, I3C_ABORT, 0); + ARRAY_FIELD_DP32(s->regs, INTR_STATUS, TRANSFER_ABORT, 1); + dw_i3c_update_irq(s); + } + /* Update present state. */ + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_ST_STATUS, + DW_I3C_TRANSFER_STATE_IDLE); + ARRAY_FIELD_DP32(s->regs, PRESENT_STATE, CM_TFR_STATUS, + DW_I3C_TRANSFER_STATUS_IDLE); + + s->regs[R_DEVICE_CTRL] =3D val; +} + static inline bool dw_i3c_target_is_i2c(DWI3C *s, uint16_t offset) { /* / sizeof(uint32_t) because we're indexing into our 32-bit reg array= . */ @@ -1575,6 +1607,9 @@ static void dw_i3c_write(void *opaque, hwaddr offset,= uint64_t value, "] =3D 0x%08" PRIx64 "\n", __func__, offset, value); break; + case R_DEVICE_CTRL: + dw_i3c_ctrl_w(s, val32); + break; case R_RX_TX_DATA_PORT: dw_i3c_push_tx(s, val32); break; --=20 2.43.0