From nobody Mon Feb 9 01:35:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770108842; cv=none; d=zohomail.com; s=zohoarc; b=Hy75Tr57Qsy0XG4P3CK612ud51l3Wy5HSvE2Xpt/e72QSwkAOwjiPxTtBj5we5IBtli6awa/Y2Hoyjt9Wgfn2HLJq+7GfH4/QNm9cDJIlWNV9aUyepevayFx+oOGUu0A21mZIkaE7z5pt138VgapL4jUwrAf5UpGpxn4eraqKnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770108842; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=T8PLGuvobrw8snoKQ/KaXLcsBf0wZfxoPq+9Mj4bRTY=; b=IZha/yhbKLC/tAaCcJ2uzlkoIs22LnY30E8YP78JFimkPme/bYKH7cWzS8DJ+FfHvQUWTobx4Ys7yqxgEnyVWzZApmxRK3q2fjI3MMrsQRowUYU/DMSj2HIYWxq4B8nFWLqdGiFU/tIdIpIPvefYhJGYZN4keeNmJefd2pr1uCI= ARC-Authentication-Results: i=1; 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Tue, 3 Feb 2026 16:52:34 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 3 Feb 2026 16:52:34 +0800 To: , , Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "open list:All patches CC here" , "open list:ARM TCG CPUs" CC: , , , Patrick Venture , Hao Wu Subject: [PATCH v2 11/20] hw/i3c/dw-i3c: Add IRQ MMIO behavior Date: Tue, 3 Feb 2026 16:52:11 +0800 Message-ID: <20260203085229.1543287-12-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> References: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770108844794154100 Content-Type: text/plain; charset="utf-8" From: Joe Komlodi Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Reviewed-by: Hao Wu Reviewed-by: Jamin Lin --- hw/i3c/dw-i3c.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index 9dc71aa3d8..bda8ab5d51 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -17,6 +17,7 @@ #include "qapi/error.h" #include "migration/vmstate.h" #include "trace.h" +#include "hw/core/irq.h" =20 REG32(DEVICE_CTRL, 0x00) FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) @@ -335,6 +336,46 @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] =3D { [R_SLAVE_CONFIG] =3D 0xffffffff, }; =20 +static void dw_i3c_update_irq(DWI3C *s) +{ + bool level =3D !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); + qemu_set_irq(s->irq, level); +} + +static uint32_t dw_i3c_intr_status_r(DWI3C *s) +{ + /* Only return the status whose corresponding EN bits are set. */ + return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; +} + +static void dw_i3c_intr_status_w(DWI3C *s, uint32_t val) +{ + /* INTR_STATUS[13:5] is w1c, other bits are RO. */ + val &=3D 0x3fe0; + s->regs[R_INTR_STATUS] &=3D ~val; + + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_status_en_w(DWI3C *s, uint32_t val) +{ + s->regs[R_INTR_STATUS_EN] =3D val; + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_signal_en_w(DWI3C *s, uint32_t val) +{ + s->regs[R_INTR_SIGNAL_EN] =3D val; + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val) +{ + /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */ + s->regs[R_INTR_STATUS] =3D val; + dw_i3c_update_irq(s); +} + static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) { DWI3C *s =3D DW_I3C(opaque); @@ -348,6 +389,9 @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset= , unsigned size) case R_INTR_FORCE: value =3D 0; break; + case R_INTR_STATUS: + value =3D dw_i3c_intr_status_r(s); + break; default: value =3D s->regs[addr]; break; @@ -392,6 +436,18 @@ static void dw_i3c_write(void *opaque, hwaddr offset, = uint64_t value, break; case R_RESET_CTRL: break; + case R_INTR_STATUS: + dw_i3c_intr_status_w(s, val32); + break; + case R_INTR_STATUS_EN: + dw_i3c_intr_status_en_w(s, val32); + break; + case R_INTR_SIGNAL_EN: + dw_i3c_intr_signal_en_w(s, val32); + break; + case R_INTR_FORCE: + dw_i3c_intr_force_w(s, val32); + break; default: s->regs[addr] =3D val32; break; --=20 2.43.0