From nobody Mon Feb 9 01:35:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1770108871; cv=none; d=zohomail.com; s=zohoarc; b=V0Z3OEuNT1PQQ5DTM8moReYbnoH3SKJ94+vaSxBfiqogLADn1wDoXpkg/VXEtUTykh8EMhl6DP1WxF78r6LhNNm78ACIbRa6q3Ah4l2a6VtDiWYnYLpTOWB7oWq6+WwaOoGEK0L0wP/hBY4bTYW3vyiOZxtL0z76QvqUnQJ1TxA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770108871; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=v0GbFyabNwrbll/srZ7lg/FAoSvnLpzHBwCs8wXSImA=; b=SrQHOv6EDw66AU8ARyYWGh4odDNKNKpzg1YKYKxEH25NqDVX32wX2b2ddO+Qo43A4C3A2oMtpoUtT8x76g66OeHRlsoTAISG13+s1cyxXB1ani/tav1K76B6eWU3LodCaWtPEeOnyw1mljO/0/q3ccvEjxbTgLWOrqS2JburQiY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770108871065720.8452961911778; Tue, 3 Feb 2026 00:54:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnCAL-0005A8-G6; Tue, 03 Feb 2026 03:53:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnC9j-0004qb-Kn; Tue, 03 Feb 2026 03:53:08 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnC9i-0002qU-53; Tue, 03 Feb 2026 03:53:07 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 3 Feb 2026 16:52:34 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 3 Feb 2026 16:52:34 +0800 To: , , Paolo Bonzini , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "open list:All patches CC here" , "open list:ARM TCG CPUs" CC: , , , Patrick Venture , "Titus Rwantare" Subject: [PATCH v2 10/20] hw/i3c/dw-i3c: Use 32 bits on MMIO writes Date: Tue, 3 Feb 2026 16:52:10 +0800 Message-ID: <20260203085229.1543287-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> References: <20260203085229.1543287-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770108873661158500 Content-Type: text/plain; charset="utf-8" From: Joe Komlodi The registers are only 32 bits wide, so we should cast the 64-bit value passed in to only be 32 bits wide. Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Reviewed-by: Titus Rwantare Reviewed-by: Jamin Lin --- hw/i3c/dw-i3c.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index e20244de2c..9dc71aa3d8 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -363,10 +363,11 @@ static void dw_i3c_write(void *opaque, hwaddr offset,= uint64_t value, { DWI3C *s =3D DW_I3C(opaque); uint32_t addr =3D offset >> 2; + uint32_t val32 =3D (uint32_t)value; =20 trace_dw_i3c_write(s->id, offset, value); =20 - value &=3D ~dw_i3c_ro[addr]; + val32 &=3D ~dw_i3c_ro[addr]; switch (addr) { case R_HW_CAPABILITY: case R_RESPONSE_QUEUE_PORT: @@ -392,7 +393,7 @@ static void dw_i3c_write(void *opaque, hwaddr offset, u= int64_t value, case R_RESET_CTRL: break; default: - s->regs[addr] =3D value; + s->regs[addr] =3D val32; break; } } --=20 2.43.0