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Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Yoshinori Sato , Thomas Huth , Ilya Leoshkevich , David Hildenbrand , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov , qemu-ppc@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 7/7] disas: Have disas_set_info() take a const CPUState Date: Mon, 2 Feb 2026 23:24:12 +0100 Message-ID: <20260202222412.24923-8-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260202222412.24923-1-philmd@linaro.org> References: <20260202222412.24923-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=philmd@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770071170392154100 The CPUClass::disas_set_info() handler is meant to initialize the %disassemble_info structure; it shoudn't alter the CPU state. Enforce the CPUState can not be modified by having the handler take a const pointer. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- include/hw/core/cpu.h | 2 +- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 6 +++--- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 3 ++- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 6 +++--- target/loongarch/cpu.c | 3 ++- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 7 +++++-- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 5 +++-- target/riscv/cpu.c | 7 ++++--- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 19 files changed, 38 insertions(+), 27 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 61da2ea4331..b2d33aac262 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -175,7 +175,7 @@ struct CPUClass { const char * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_core_xml_file)(CPUState *cpu); =20 - void (*disas_set_info)(CPUState *cpu, disassemble_info *info); + void (*disas_set_info)(const CPUState *cpu, disassemble_info *info); =20 const char *deprecation_note; struct AccelCPUClass *accel_cpu; diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 932cddac055..1780db7d1e2 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -98,7 +98,8 @@ static int alpha_cpu_mmu_index(CPUState *cs, bool ifetch) return alpha_env_mmu_index(cpu_env(cs)); } =20 -static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void alpha_cpu_disas_set_info(const CPUState *cpu, + disassemble_info *info) { info->endian =3D BFD_ENDIAN_LITTLE; info->mach =3D bfd_mach_alpha_ev6; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 586202071d0..c535b292d99 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -789,10 +789,10 @@ static void arm_wfxt_timer_cb(void *opaque) } #endif =20 -static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) +static void arm_disas_set_info(const CPUState *cpu, disassemble_info *info) { - ARMCPU *ac =3D ARM_CPU(cpu); - CPUARMState *env =3D &ac->env; + const ARMCPU *ac =3D ARM_CPU(cpu); + const CPUARMState *env =3D &ac->env; bool sctlr_b =3D arm_sctlr_b(env); =20 if (is_a64(env)) { diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 52237da3ce9..8579a7283b1 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -116,7 +116,7 @@ static void avr_cpu_reset_hold(Object *obj, ResetType t= ype) memset(env->r, 0, sizeof(env->r)); } =20 -static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void avr_cpu_disas_set_info(const CPUState *cpu, disassemble_info *= info) { info->endian =3D BFD_ENDIAN_LITTLE; info->mach =3D bfd_arch_avr; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 8ac4f49aa3b..58a22ee41f2 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -301,7 +301,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetTy= pe type) set_float_default_nan_pattern(0b11111111, &env->fp_status); } =20 -static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void hexagon_cpu_disas_set_info(const CPUState *cs, + disassemble_info *info) { info->print_insn =3D print_insn_hexagon; info->endian =3D BFD_ENDIAN_LITTLE; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 0ca79ee5e23..714f3bbdaf7 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -150,7 +150,7 @@ static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch) return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; } =20 -static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) +static void hppa_cpu_disas_set_info(const CPUState *cs, disassemble_info *= info) { info->mach =3D bfd_mach_hppa20; info->endian =3D BFD_ENDIAN_BIG; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 45f0b80deb0..0a7b884528e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -10359,10 +10359,10 @@ static bool x86_cpu_has_work(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -static void x86_disas_set_info(CPUState *cs, disassemble_info *info) +static void x86_disas_set_info(const CPUState *cs, disassemble_info *info) { - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; + const X86CPU *cpu =3D X86_CPU(cs); + const CPUX86State *env =3D &cpu->env; =20 info->endian =3D BFD_ENDIAN_LITTLE; info->mach =3D (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b6539485266..4fa629cb144 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -506,7 +506,8 @@ static void loongarch_cpu_reset_hold(Object *obj, Reset= Type type) cs->exception_index =3D -1; } =20 -static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *in= fo) +static void loongarch_cpu_disas_set_info(const CPUState *cs, + disassemble_info *info) { info->endian =3D BFD_ENDIAN_LITTLE; info->print_insn =3D print_insn_loongarch; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index b55e604b11d..c721a23b966 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -176,7 +176,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType = type) env->pc =3D 0; } =20 -static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void m68k_cpu_disas_set_info(const CPUState *cs, disassemble_info *= info) { info->print_insn =3D print_insn_m68k; info->endian =3D BFD_ENDIAN_BIG; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 53649ec6567..ae41a1a3287 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -233,7 +233,7 @@ static void mb_cpu_reset_hold(Object *obj, ResetType ty= pe) #endif } =20 -static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) +static void mb_disas_set_info(const CPUState *cpu, disassemble_info *info) { info->mach =3D bfd_arch_microblaze; info->print_insn =3D print_insn_microblaze; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index f74a9d5f615..e424d115018 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -422,9 +422,12 @@ static void mips_cpu_reset_hold(Object *obj, ResetType= type) #endif } =20 -static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void mips_cpu_disas_set_info(const CPUState *cs, disassemble_info *= info) { - if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { + const MIPSCPU *cpu =3D MIPS_CPU(cs); + const CPUMIPSState *env =3D &cpu->env; + + if (!(env->insn_flags & ISA_NANOMIPS32)) { info->endian =3D TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; info->print_insn =3D TARGET_BIG_ENDIAN ? print_insn_big_mips diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 9bbfe22ed3a..c64542a59a2 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -94,7 +94,7 @@ static int openrisc_cpu_mmu_index(CPUState *cs, bool ifet= ch) return MMU_NOMMU_IDX; /* mmu is disabled */ } =20 -static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) +static void openrisc_disas_set_info(const CPUState *cpu, disassemble_info = *info) { info->endian =3D BFD_ENDIAN_BIG; info->print_insn =3D print_insn_or1k; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 58816c51a74..d67db2e0064 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7452,9 +7452,10 @@ static bool ppc_pvr_match_default(PowerPCCPUClass *p= cc, uint32_t pvr, bool best) return pcc->pvr =3D=3D pvr; } =20 -static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) +static void ppc_disas_set_info(const CPUState *cs, disassemble_info *info) { - CPUPPCState *env =3D cpu_env(cs); + const PowerPCCPU *cpu =3D POWERPC_CPU(cs); + const CPUPPCState *env =3D &cpu->env; =20 if ((env->hflags >> MSR_LE) & 1) { info->endian =3D BFD_ENDIAN_LITTLE; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e95eea02493..e56470a3748 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -795,10 +795,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) #endif } =20 -static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) +static void riscv_cpu_disas_set_info(const CPUState *s, disassemble_info *= info) { - RISCVCPU *cpu =3D RISCV_CPU(s); - CPURISCVState *env =3D &cpu->env; + const RISCVCPU *cpu =3D RISCV_CPU(s); + const CPURISCVState *env =3D &cpu->env; + info->target_info =3D &cpu->cfg; =20 /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 0437edca1ba..b5284199e6d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -178,7 +178,7 @@ static void rx_cpu_set_irq(void *opaque, int no, int re= quest) } } =20 -static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void rx_cpu_disas_set_info(const CPUState *cpu, disassemble_info *i= nfo) { info->endian =3D BFD_ENDIAN_LITTLE; info->mach =3D bfd_mach_rx; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index cd472d38be7..c074e12ba2d 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -222,7 +222,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType = type) } } =20 -static void s390_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +static void s390_cpu_disas_set_info(const CPUState *cpu, disassemble_info = *info) { info->mach =3D bfd_mach_s390_64; info->cap_arch =3D CS_ARCH_SYSZ; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 1dd21ad9ed6..e2bde457618 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -164,7 +164,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetTyp= e type) set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); } =20 -static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *inf= o) +static void superh_cpu_disas_set_info(const CPUState *cpu, + disassemble_info *info) { info->endian =3D TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bfc6fb9d00d..3991681d1d1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -103,7 +103,8 @@ static bool sparc_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) } #endif /* !CONFIG_USER_ONLY */ =20 -static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info) +static void cpu_sparc_disas_set_info(const CPUState *cpu, + disassemble_info *info) { info->print_insn =3D print_insn_sparc; info->endian =3D BFD_ENDIAN_BIG; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ecc5e093a40..86ec899a67c 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -226,7 +226,8 @@ static ObjectClass *xtensa_cpu_class_by_name(const char= *cpu_model) return oc; } =20 -static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) +static void xtensa_cpu_disas_set_info(const CPUState *cs, + disassemble_info *info) { XtensaCPU *cpu =3D XTENSA_CPU(cs); =20 --=20 2.52.0