From nobody Tue Feb 10 20:48:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770070209027651.7478721069604; Mon, 2 Feb 2026 14:10:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vn27M-0006L3-Pj; Mon, 02 Feb 2026 17:10:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vn26o-0005Ml-55; Mon, 02 Feb 2026 17:09:29 -0500 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vn26m-0002i0-Ax; Mon, 02 Feb 2026 17:09:25 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 3AD9F1852C0; Tue, 03 Feb 2026 01:07:35 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 199AA35B3D3; Tue, 03 Feb 2026 01:08:17 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Paolo Bonzini , Richard Henderson , Michael Tokarev Subject: [Stable-10.2.1 19/56] target/i386/tcg: do not mark all SSE instructions as unaligned Date: Tue, 3 Feb 2026 01:07:24 +0300 Message-ID: <20260202220805.945271-19-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770070209988158500 Content-Type: text/plain; charset="utf-8" From: Paolo Bonzini If the vex_special field was not initialized, it was considered to be X86_VEX_SSEUnaligned (whose value was zero). Add a new value to fix that. Cc: qemu-stable@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini (cherry picked from commit 73dd6e4a36dd8d85548292f382a4d479e2810371) Signed-off-by: Michael Tokarev diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index dfaffec599..31aad730fc 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -944,15 +944,15 @@ static void decode_0F10(DisasContext *s, CPUX86State = *env, X86OpEntry *entry, ui static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *ent= ry, uint8_t *b) { static const X86OpEntry opcodes_0F11_reg[4] =3D { - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* MOVUPS= */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* MOVUPD= */ X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5), X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */ }; =20 static const X86OpEntry opcodes_0F11_mem[4] =3D { - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */ - X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* MOV= UPS */ + X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* MOV= UPD */ X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5), X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */ }; @@ -2382,6 +2382,9 @@ static bool validate_vex(DisasContext *s, X86DecodedI= nsn *decode) X86OpEntry *e =3D &decode->e; =20 switch (e->vex_special) { + case X86_VEX_None: + break; + case X86_VEX_REPScalar: /* * Instructions which differ between 00/66 and F2/F3 in the diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index 7f23d373ea..9282296900 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -242,6 +242,8 @@ typedef enum X86InsnSpecial { * section of the manual. */ typedef enum X86VEXSpecial { + X86_VEX_None, + /* Legacy SSE instructions that allow unaligned operands */ X86_VEX_SSEUnaligned, =20 --=20 2.47.3