From nobody Tue Feb 10 13:17:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770065988717489.1038090356303; Mon, 2 Feb 2026 12:59:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vn11F-0004QC-Tc; Mon, 02 Feb 2026 15:59:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vn10r-000457-Hj; Mon, 02 Feb 2026 15:59:15 -0500 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vn10o-0003mq-Cr; Mon, 02 Feb 2026 15:59:13 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 0E247185191; Mon, 02 Feb 2026 23:57:52 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id C9C5835B308; Mon, 02 Feb 2026 23:58:33 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jessica Clarke , Richard Henderson , Michael Tokarev Subject: [Stable-10.1.4 05/74] target/arm: handle unaligned PC during tlb probe Date: Mon, 2 Feb 2026 23:57:16 +0300 Message-ID: <20260202205833.941615-5-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1770065992546158500 From: Alex Benn=C3=A9e PC alignment faults have priority over instruction aborts and we have code to deal with this in the translation front-ends. However during tb_lookup we can see a potentially faulting probe which doesn't get a MemOp set. If the page isn't available this results in EC_INSNABORT (0x20) instead of EC_PCALIGNMENT (0x22). As there is no easy way to set the appropriate MemOp in the instruction fetch probe path lets just detect it in arm_cpu_tlb_fill_align() ahead of the main alignment check. We also teach arm_deliver_fault to deliver the right syndrome for MMU_INST_FETCH alignment issues. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3233 Tested-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20251209092459.1058313-5-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e (cherry picked from commit dd77ef99aa0280c467fe8442b4238122899ae6cf) Signed-off-by: Michael Tokarev diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 23c72a99f5..91f5735b2b 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -243,7 +243,11 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); =20 if (access_type =3D=3D MMU_INST_FETCH) { - syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); + if (fi->type =3D=3D ARMFault_Alignment) { + syn =3D syn_pcalignment(); + } else { + syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); + } exc =3D EXCP_PREFETCH_ABORT; } else { syn =3D merge_syn_data_abort(env->exception.syndrome, fi, target_e= l, @@ -338,11 +342,18 @@ bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntry= Full *out, vaddr address, } =20 /* - * Per R_XCHFJ, alignment fault not due to memory type has - * highest precedence. Otherwise, walk the page table and - * and collect the page description. + * PC alignment faults should be dealt with at translation time + * but we also need to catch them while being probed. + * + * Then per R_XCHFJ, alignment fault not due to memory type take + * precedence. Otherwise, walk the page table and and collect the + * page description. + * */ - if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + if (access_type =3D=3D MMU_INST_FETCH && !cpu->env.thumb && + (address & 3)) { + fi->type =3D ARMFault_Alignment; + } else if (address & ((1 << memop_alignment_bits(memop)) - 1)) { fi->type =3D ARMFault_Alignment; } else if (!get_phys_addr(&cpu->env, address, access_type, memop, core_to_arm_mmu_idx(&cpu->env, mmu_idx), --=20 2.47.3