From nobody Tue Feb 10 15:45:56 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1770039272; cv=none; d=zohomail.com; s=zohoarc; b=M6VEeY7/m7WczNyBEHsjmSZYq/Gk/5+Bq4tckjtLTfuwwhD7Aoxt1KacJNifH+1/YiGg7nWN7jDJP3Pgi3UxIiaAJ1Ro1GScfGT4N/MmC3esYYVSgIEce3P+0GKAp5/iJxbGiFuYhcw7pD0dCwwg4w2gCTOq5uOq+KpI0HyHH5I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770039272; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wb6+lM6pydrnwcLmZGcqj6kVPeiLe8pR1QP6em9mlF8=; b=PvIIJ1Z67hmKGTPlxaj6zn/TQyrW5NGsQn87syZVqzKpzlZDkSay3/MPHRC2AGjGmz3VqMmBEEchx+4sLYHcwepSF2fDw97aa9tSXzk3vI5jw8m4ZBMEZO/1bVXpSDjQA6ia9eg/AWsvaRYc55CIuDkx/xDcOL0kPiJ8VL/L/f8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770039272151470.8549554099392; Mon, 2 Feb 2026 05:34:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vmu4J-0007CS-Pm; Mon, 02 Feb 2026 08:34:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vmu4F-00075s-LR for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:15 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vmu4B-0002hc-89 for qemu-devel@nongnu.org; Mon, 02 Feb 2026 08:34:15 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4807068eacbso37133235e9.2 for ; Mon, 02 Feb 2026 05:34:10 -0800 (PST) Received: from lanath.. (wildly.archaic.org.uk. [81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c42895sm478054495e9.14.2026.02.02.05.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 05:34:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1770039250; x=1770644050; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wb6+lM6pydrnwcLmZGcqj6kVPeiLe8pR1QP6em9mlF8=; b=AOpyN+Zjk9hvyRhDUJnmafdGsxWmvSsAdEdQCoXr1Fwgza6Oo0Xpbw7R/is1khmfUO UGb5pF5YAa8ewYEUymZeS6ySkmD+UBfZAEhXGiDu2BciheqOtKK0DlrOkCnZMmaAjcxz YCttxf1nw6ssg+9TsCgzB3GuLSM9caTxacTiasDJLgd0/LT7WPakV4H6A191rRF92gVa BRnshXaaWXIKtA2kXsKDogLNhgV9sgtZSBPUn04zxkOn2fn65Dr2QWebfQVS8bl1y1F4 ywyyrhIr9JXQe3N9MtFxHFyVlqRuHroxVzvSGRS4Z6rPeuLCDdXazDddHX5PZymys/my feGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770039250; x=1770644050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wb6+lM6pydrnwcLmZGcqj6kVPeiLe8pR1QP6em9mlF8=; b=cXy5cDmkR9cR64EpiQYR/8UFX3J3BiBKl2ebGctoePo44dYBXOIRfaxpj42KpIQUOe ga8SkkfCk1I9qP41mKs9tS20HEA1LZS3SqMjI7+YHk1wmiENRbKGByZBMaoJl0F0kzio F98JjZPKZyu3kgtZDRMMO5vVk27QFxYtd/pk6HV+3DF1bvKEzrOZL3qioH19CqYahK3c as8dA3PIxj1YcAn0Q9jfKhLn77HDcl8Kf/7s54pyDMV3io+OQ5AulkPisD8ZC0YVswXo H0nx1chOHfHipBB0tyN/W/pIXlvQQA1yuxUiI90jqpH5yDddqQfKUfDcEjn6/RpMQm3b clIQ== X-Forwarded-Encrypted: i=1; AJvYcCXScmjbbb0gFroPS5YFrc2f4Sew0n6cu9uHWeoMY8WJeWSqRMvpytwoYWD+2w31kuvfCIh6hvwofYJW@nongnu.org X-Gm-Message-State: AOJu0Yx11J+4LtxjbZCtUGn1Sd7NL+f2H0OvftZE4aIMhHBEXhKL7P+f R/AmnzYLZeOQrYncb1VB1dEz+YzlwVJDD8kpJycOtSTWAK5Icmjb0+nihONO96SCCF4= X-Gm-Gg: AZuq6aIet1+V9oXwSVdypZEPygVvEphSkqOqgOvzjZB2440rs5W7dlt0mCBIcgP59kP rF7XxJjWBFJIvOff3MMHSIcvydFfUF9L197q5Dwn6eK6Ia1e7YiPoZuDtRFHU4KNftXi6boA40c zYNKY8WdHI0EI7vnFm3YQg8pqqsQcu6qU1YqGQiGF5u8SRTAK0iD2UyNls+suCg/AZG/6rayC5O jTQQmAMCoq+6PnxzkT7t0YeA5DmXU+WyXULcxbkt42hPx+E3r0/ma5H9lrzy5Hl/7V+Q6nBlLfL 4zq2Av7W4u2+8En6ctYq/HMi4dQTmFcenBJn7agJD2NvmoDISvZZpT6Ut6MR5hujSiw3jt/nNyL xvxuD64MrWKtP/ZLHtJCn5RaXxc5QyRNbMyuHbwruageIxlx/jXamUCB/G4FT+HaJilNmLbRW3i 2E/t/M08jsFzWannldtse9E75Exfx1og== X-Received: by 2002:a05:600c:19cc:b0:480:690e:f14a with SMTP id 5b1f17b1804b1-482db4563b7mr156150385e9.14.1770039249839; Mon, 02 Feb 2026 05:34:09 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , Manos Pitsidianakis , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH v3 12/15] target/arm/tcg: Correct SVE/SME BF16 checks Date: Mon, 2 Feb 2026 13:33:50 +0000 Message-ID: <20260202133353.2231685-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260202133353.2231685-1-peter.maydell@linaro.org> References: <20260202133353.2231685-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1770039273756158500 Content-Type: text/plain; charset="utf-8" As with I8MM, the BF16 field of ID_AA64ZFR0_EL1 is set when the CPU implements FEAT_BF16 and either FEAT_SVE or FEAT_SME, so we need to have separate checks for "(SVE || SME) && BF16" and "SVE && BF16". Follow the same pattern as with I8MM: * aa64_sve_sme_bf16 means (SVE || SME) && BF16 * aa64_sve_bf16 means (SVE && BF16) BFMMLA is the only SVE BF16 insn that isn't in SME. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu-features.h | 7 ++++++- target/arm/tcg/translate-sve.c | 16 ++++++++-------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 8b8de5db04..1bcf28ab08 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1434,7 +1434,7 @@ static inline bool isar_feature_aa64_sve2_bitperm(con= st ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 -static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) +static inline bool isar_feature_aa64_sme_sve_bf16(const ARMISARegisters *i= d) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) !=3D 0; } @@ -1548,6 +1548,11 @@ static inline bool isar_feature_aa64_sve_i8mm(const = ARMISARegisters *id) return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id); } =20 +static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) +{ + return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 53d35f6de9..956ddee123 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4430,7 +4430,7 @@ TRANS_FEAT(FCVT_sh, aa64_sme_or_sve, gen_gvec_fpst_ar= g_zpz, TRANS_FEAT(FCVT_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(BFCVT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 @@ -7818,7 +7818,7 @@ TRANS_FEAT(FCVTNT_sh, aa64_sme_or_sve2, gen_gvec_fpst= _arg_zpz, TRANS_FEAT(FCVTNT_ds, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 @@ -7875,9 +7875,9 @@ TRANS_FEAT(FDOT_zzzz, aa64_sme2_or_sve2p1, gen_gvec_e= nv_arg_zzzz, TRANS_FEAT(FDOT_zzxz, aa64_sme2_or_sve2p1, gen_gvec_env_arg_zzxz, gen_helper_sme2_fdot_idx_h, a) =20 -TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_env_arg_zzzz, +TRANS_FEAT(BFDOT_zzzz, aa64_sme_sve_bf16, gen_gvec_env_arg_zzzz, gen_helper_gvec_bfdot, a, 0) -TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_env_arg_zzxz, +TRANS_FEAT(BFDOT_zzxz, aa64_sme_sve_bf16, gen_gvec_env_arg_zzxz, gen_helper_gvec_bfdot_idx, a) =20 TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_env_arg_zzzz, @@ -7890,8 +7890,8 @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_= esz *a, bool sel) s->fpcr_ah ? FPST_AH : FPST_A64); } =20 -TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false) -TRANS_FEAT(BFMLALT_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, true) +TRANS_FEAT(BFMLALB_zzzw, aa64_sme_sve_bf16, do_BFMLAL_zzzw, a, false) +TRANS_FEAT(BFMLALT_zzzw, aa64_sme_sve_bf16, do_BFMLAL_zzzw, a, true) =20 static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) { @@ -7901,8 +7901,8 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_= esz *a, bool sel) s->fpcr_ah ? FPST_AH : FPST_A64); } =20 -TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) -TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) +TRANS_FEAT(BFMLALB_zzxw, aa64_sme_sve_bf16, do_BFMLAL_zzxw, a, false) +TRANS_FEAT(BFMLALT_zzxw, aa64_sme_sve_bf16, do_BFMLAL_zzxw, a, true) =20 static bool do_BFMLSL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) { --=20 2.43.0