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Sun, 01 Feb 2026 23:54:18 -0800 (PST) From: Jim Shu To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Richard Henderson , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , Michael Rolnik , Helge Deller , Eduardo Habkost , Song Gao , Laurent Vivier , "Edgar E. Iglesias" , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Chinmay Rath , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Yoshinori Sato , Ilya Leoshkevich , David Hildenbrand , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [PATCH 2/2] accel/tcg: address_space_translate*() will pass the correct iommu_flags Date: Mon, 2 Feb 2026 15:53:58 +0800 Message-ID: <20260202075358.2137740-3-jim.shu@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260202075358.2137740-1-jim.shu@sifive.com> References: <20260202075358.2137740-1-jim.shu@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x442.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_SBL=1.623 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1770018914286154100 Content-Type: text/plain; charset="utf-8" Instead of IOMMU_NONE, address_space_translate_for_iotlb() now can pass the correct iommu_flags to the IOMMU translate function from the access_type. Since RISC-V wgChecker [1] could permit access in RO or WO permission only, the IOMMUMemoryRegion could return different section for read and write access. To support this kind of IOMMUMemoryRegion in the path of CPU access, we should pass correct iommu_flags here. [1] RISC-V WG: https://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/ Signed-off-by: Jim Shu --- accel/tcg/cputlb.c | 3 ++- include/accel/tcg/iommu.h | 3 ++- system/physmem.c | 16 +++++++++++----- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2a0f4cfff62..404a8607b9b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1050,7 +1050,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, prot =3D full->prot; asidx =3D cpu_asidx_from_attrs(cpu, full->attrs); section =3D address_space_translate_for_iotlb(cpu, asidx, paddr_page, - &xlat, &sz, full->attrs, &= prot); + &xlat, &sz, full->attrs, &= prot, + access_type); assert(sz >=3D TARGET_PAGE_SIZE); =20 tlb_debug("vaddr=3D%016" VADDR_PRIx " paddr=3D0x" HWADDR_FMT_plx diff --git a/include/accel/tcg/iommu.h b/include/accel/tcg/iommu.h index 547f8ea0ef0..2a79f859834 100644 --- a/include/accel/tcg/iommu.h +++ b/include/accel/tcg/iommu.h @@ -20,7 +20,8 @@ MemoryRegionSection *address_space_translate_for_iotlb(CP= UState *cpu, hwaddr *xlat, hwaddr *plen, MemTxAttrs attrs, - int *prot); + int *prot, + MMUAccessType acces= s_type); =20 #endif =20 diff --git a/system/physmem.c b/system/physmem.c index 2fb0c25c93b..337137489de 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -683,12 +683,14 @@ void tcg_iommu_init_notifier_list(CPUState *cpu) MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr orig_ad= dr, hwaddr *xlat, hwaddr *plen, - MemTxAttrs attrs, int *prot) + MemTxAttrs attrs, int *prot, + MMUAccessType access_type) { MemoryRegionSection *section; IOMMUMemoryRegion *iommu_mr; IOMMUMemoryRegionClass *imrc; IOMMUTLBEntry iotlb; + IOMMUAccessFlags iommu_flags; int iommu_idx; hwaddr addr =3D orig_addr; AddressSpaceDispatch *d =3D address_space_to_dispatch(cpu->cpu_ases[as= idx].as); @@ -705,10 +707,14 @@ address_space_translate_for_iotlb(CPUState *cpu, int = asidx, hwaddr orig_addr, =20 iommu_idx =3D imrc->attrs_to_index(iommu_mr, attrs); tcg_register_iommu_notifier(cpu, iommu_mr, iommu_idx); - /* We need all the permissions, so pass IOMMU_NONE so the IOMMU - * doesn't short-cut its translation table walk. - */ - iotlb =3D imrc->translate(iommu_mr, addr, IOMMU_NONE, iommu_idx); + + if (access_type =3D=3D MMU_DATA_STORE) { + iommu_flags =3D IOMMU_WO; + } else { + iommu_flags =3D IOMMU_RO; + } + + iotlb =3D imrc->translate(iommu_mr, addr, iommu_flags, iommu_idx); addr =3D ((iotlb.translated_addr & ~iotlb.addr_mask) | (addr & iotlb.addr_mask)); /* Update the caller's prot bits to remove permissions the IOMMU --=20 2.43.0