From nobody Sun Feb 8 22:00:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1770102311; cv=none; d=zohomail.com; s=zohoarc; b=OfNyN3UEbiSAgtXCmm38z5pw1FNCpKjBEt7STrBovMfGsuxjWcC79cXhasjE1wopaouykPnARUpPysXw4sByAM4CFzgO3xUKlu4ktpU17BTgthWujhSTBqWh6RCedfHhgkcclF9hmCOj27qHQjLjPnG2Xni9MQ+s0WF+99Kw6pI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770102311; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=m2mVBAEah6FvRCaAgJ8LEM2M8PFLaDkQUDZUPErKJQg=; b=oK4lLB/Bo28OiIrWeIvs8JrxEa3CjKUioyBwbsqFci5hsbmCFUsIwBbfSpRT+yjQxIms5dab8RSn9KFrXY9g8mMK9LTvDcSPMrJqJh7QBwP4P6BjczIS78oCYpTGW9KbW1l1G0QV6ec5MpzDQ4f5HcMPpRmoTJ93BigsI3m9Wdg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1770102311547699.0885504042445; Mon, 2 Feb 2026 23:05:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vnASC-0002Fv-LZ; Tue, 03 Feb 2026 02:04:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnARy-00020z-4T; Tue, 03 Feb 2026 02:03:51 -0500 Received: from sea.source.kernel.org ([172.234.252.31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vnARv-0003Du-Iw; Tue, 03 Feb 2026 02:03:49 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sea.source.kernel.org (Postfix) with ESMTP id B4A0541874; Tue, 3 Feb 2026 07:03:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4754BC19425; Tue, 3 Feb 2026 07:03:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770102216; bh=wxW16Aj8+WzjRknuFv3nEfcuaZXq+HX7rJ/JER0/6CM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=MawDolkzv19ctlvC0TLxkDaRclaw8oxxAEtE/JJyNL08KZCWJ0F5y2BdNZdtXP9Yk 5HsFulI+NMi68HUtNZc06WkjSlRGLJ6gu3mJhLW8t+c3E8IioJWT/F0x+iWAkJHe7/ gJBxzrl6m7j7pVgjWDxugUSVryH3J2GRg9/OQrqExk/UPfvrrsvo0xuGQGSPH5caSO 3Vy+FwqF8+6Sxx4xjixKniSevIJciDvv9vuzbKY9TlBs7ixBnRs8qjO5DTkDoqR2qR idwPBp12+ybS0iuPQxEhOGtKpFABqvtSDJ7L5s+6UNCmhNBINNPQQuXclEqGXUJaGr oH+dE4q+gO63A== From: Drew Fustini Date: Mon, 02 Feb 2026 23:01:18 -0800 Subject: [PATCH RFC 2/7] acpi: aml-build: Add cache structure table creation for PPTT table MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260202-riscv-rqsc-v1-2-dcf448a3ed73@kernel.org> References: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> In-Reply-To: <20260202-riscv-rqsc-v1-0-dcf448a3ed73@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Sunil V L , "Michael S. Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Peter Maydell , Sia Jee Heng , qemu-arm@nongnu.org, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=8295; i=fustini@kernel.org; h=from:subject:message-id; bh=5p3vnkRRKyTkMr0IIO7uoTexFRSKAeuHTrWqcyemBRY=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWQ2zj3W75lzS6DswOUvM2eztO35e5iD5eR/35XimTWt6 nc2qpU3dZSyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmoi3N8M96nkb5k0x1kelH hWyqpy3LvmVbrx+27f8S9aZr60KLV0gwMpw2+at7XZmPZ8q6w+uSvv3kWvjw6//bq9lYtE//WiV /7gY/AA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.234.252.31; envelope-from=fustini@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1770103862757158500 From: Sia Jee Heng Adds cache structure table generation for the Processor Properties Topology Table (PPTT) to describe cache hierarchy information for ACPI guests. A 3-level cache topology is employed here, referring to the type 1 cache structure according to ACPI spec v6.3. The L1 cache and L2 cache are private resources for the core, while the L3 cache is the private resource for the cluster. In the absence of cluster values in the QEMU command, a 2-layer cache is expected. The default cache value should be passed in from the architecture code. Examples: 3-layer: -smp 4,sockets=3D1,clusters=3D2,cores=3D2,threads=3D1 2-layer: -smp 4,sockets=3D1,cores=3D2,threads=3D2 Link: https://lore.kernel.org/all/20240129104039.117671-1-jeeheng.sia@starf= ivetech.com/ Signed-off-by: Sia Jee Heng Signed-off-by: Drew Fustini --- hw/acpi/aml-build.c | 69 +++++++++++++++++++++++++++++++++++++++++= ---- include/hw/acpi/aml-build.h | 21 +++++++++++++- 2 files changed, 84 insertions(+), 6 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index dad4cfcc7d80..742e7a6eb261 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2140,12 +2140,41 @@ void build_spcr(GArray *table_data, BIOSLinker *lin= ker, } acpi_table_end(linker, &table); } + +/* ACPI spec, Revision 6.3 Cache type structure (Type 1) */ +static void build_cache_structure(GArray *tbl, + uint32_t next_level, + CPUCacheInfo *cache_info) +{ + /* Cache type structure */ + build_append_byte(tbl, 1); + /* Length */ + build_append_byte(tbl, 24); + /* Reserved */ + build_append_int_noprefix(tbl, 0, 2); + /* Flags */ + build_append_int_noprefix(tbl, 0x7f, 4); + /* Next level cache */ + build_append_int_noprefix(tbl, next_level, 4); + /* Size */ + build_append_int_noprefix(tbl, cache_info->size, 4); + /* Number of sets */ + build_append_int_noprefix(tbl, cache_info->sets, 4); + /* Associativity */ + build_append_byte(tbl, cache_info->associativity); + /* Attributes */ + build_append_byte(tbl, cache_info->attributes); + /* Line size */ + build_append_int_noprefix(tbl, cache_info->line_size, 2); +} + /* * ACPI spec, Revision 6.3 * 5.2.29 Processor Properties Topology Table (PPTT) */ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id) + const char *oem_id, const char *oem_table_id, + const CPUCaches *CPUCaches) { MachineClass *mc =3D MACHINE_GET_CLASS(ms); CPUArchIdList *cpus =3D ms->possible_cpus; @@ -2153,6 +2182,8 @@ void build_pptt(GArray *table_data, BIOSLinker *linke= r, MachineState *ms, uint32_t socket_offset =3D 0, cluster_offset =3D 0, core_offset =3D 0; uint32_t pptt_start =3D table_data->len; uint32_t root_offset; + uint32_t l3_offset =3D 0, priv_num =3D 0; + uint32_t priv_rsrc[3] =3D {0}; int n; AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 2, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; @@ -2183,11 +2214,15 @@ void build_pptt(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms, socket_id =3D cpus->cpus[n].props.socket_id; cluster_id =3D -1; core_id =3D -1; + priv_num =3D 0; socket_offset =3D table_data->len - pptt_start; build_processor_hierarchy_node(table_data, (1 << 0) | /* Physical package */ (1 << 4), /* Identical Implementation */ - root_offset, socket_id, NULL, 0); + root_offset, + socket_id, + NULL, + priv_num); } =20 if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters= ) { @@ -2195,21 +2230,45 @@ void build_pptt(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms, assert(cpus->cpus[n].props.cluster_id > cluster_id); cluster_id =3D cpus->cpus[n].props.cluster_id; core_id =3D -1; + priv_num =3D 0; + l3_offset =3D table_data->len - pptt_start; + /* L3 cache type structure */ + if (CPUCaches && CPUCaches->l3_cache) { + priv_num =3D 1; + build_cache_structure(table_data, 0, CPUCaches->l3_cac= he); + } cluster_offset =3D table_data->len - pptt_start; build_processor_hierarchy_node(table_data, (0 << 0) | /* Not a physical package */ (1 << 4), /* Identical Implementation */ - socket_offset, cluster_id, NULL, 0); + socket_offset, cluster_id, &l3_offset, priv_num); } } else { cluster_offset =3D socket_offset; } =20 + if (CPUCaches) { + /* L2 cache type structure */ + priv_rsrc[0] =3D table_data->len - pptt_start; + build_cache_structure(table_data, 0, CPUCaches->l2_cache); + + /* L1d cache type structure */ + priv_rsrc[1] =3D table_data->len - pptt_start; + build_cache_structure(table_data, priv_rsrc[0], + CPUCaches->l1d_cache); + + /* L1i cache type structure */ + priv_rsrc[2] =3D table_data->len - pptt_start; + build_cache_structure(table_data, priv_rsrc[0], + CPUCaches->l1i_cache); + + priv_num =3D 3; + } if (ms->smp.threads =3D=3D 1) { build_processor_hierarchy_node(table_data, (1 << 1) | /* ACPI Processor ID valid */ (1 << 3), /* Node is a Leaf */ - cluster_offset, n, NULL, 0); + cluster_offset, n, priv_rsrc, priv_num); } else { if (cpus->cpus[n].props.core_id !=3D core_id) { assert(cpus->cpus[n].props.core_id > core_id); @@ -2225,7 +2284,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linke= r, MachineState *ms, (1 << 1) | /* ACPI Processor ID valid */ (1 << 2) | /* Processor is a Thread */ (1 << 3), /* Node is a Leaf */ - core_offset, n, NULL, 0); + core_offset, n, priv_rsrc, priv_num); } } =20 diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index f38e12971932..33b303fc833b 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -3,6 +3,7 @@ =20 #include "hw/acpi/acpi-defs.h" #include "hw/acpi/bios-linker-loader.h" +#include "include/hw/core/cpu.h" =20 #define ACPI_BUILD_APPNAME6 "BOCHS " #define ACPI_BUILD_APPNAME8 "BXPC " @@ -234,6 +235,23 @@ struct CrsRangeSet { GPtrArray *mem_64bit_ranges; } CrsRangeSet; =20 +typedef +struct CPUCacheInfo { + enum CacheType type; /* Cache Type*/ + uint32_t size; /* Size of the cache in bytes */ + uint32_t sets; /* Number of sets in the cache */ + uint8_t associativity; /* Cache associativity */ + uint8_t attributes; /* Cache attributes */ + uint16_t line_size; /* Line size in bytes */ +} CPUCacheInfo; + +typedef +struct CPUCaches { + CPUCacheInfo *l1d_cache; + CPUCacheInfo *l1i_cache; + CPUCacheInfo *l2_cache; + CPUCacheInfo *l3_cache; +} CPUCaches; =20 /* * ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors @@ -499,7 +517,8 @@ void build_slit(GArray *table_data, BIOSLinker *linker,= MachineState *ms, const char *oem_id, const char *oem_table_id); =20 void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, - const char *oem_id, const char *oem_table_id); + const char *oem_id, const char *oem_table_id, + const CPUCaches *CPUCaches); =20 void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); --=20 2.43.0