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Sun, 1 Feb 2026 23:58:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 762AEC19425; Sun, 1 Feb 2026 23:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769990294; bh=HVS5JYvijnQJyKEuHjIO7N2xWlOVIn8UiT/rV+Rt4ss=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jm5L/sW1s/CHAkzGwXip0n3vTEzi3j3kr3y9qcr+SSAHlTUXuXFQBGD5YNGHOu2vq Jr0/QbYNHA5cYg2sR7ouAMBQPPXCLN6v0LYuSasEZgi6niZYRZbMOuwCKpFXZfCnWe o8rKEZ67jVzc5mchpbrqhr5ibBijT3t8z9mJ7MhKh5vKJGVwyOpv1oDTbMzy7i3iH4 tFCwy/V9HmAo/eIXfcnFpFVe8N7F9werI/wIsuBYcP5o66oRyUQ71HEMjcTVRCuTsR Lsrg3f6sHd8ovBIPqFNDfgquujMFfV0h2vyHgZIlzLZOy/G0rpw8Q1vDJSi6gNvFQD EVDb9/c7Ewvgw== From: Drew Fustini Date: Sun, 01 Feb 2026 15:58:10 -0800 Subject: [PATCH v5 4/6] hw/riscv: implement CBQRI bandwidth controller MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260201-riscv-ssqosid-cbqri-v5-4-273ea4a21703@kernel.org> References: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> In-Reply-To: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=23805; i=fustini@kernel.org; h=from:subject:message-id; bh=d6Qz76xl+Br2Ks9OXLCKQUqgV8Xcv1+lbih8SOXHUNQ=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTWv5jyP/r7mQc+P2psNJO2TSjpdtqUc2Ni9feJ3zL1I 4SWBaWod5SyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmcm4lw/+sDU1SmsXZW3QT QlnvVCUvuaTgb+z14vSs5BuP9om02osy/DP5dOzprQ5fsUXBu5a9bPX+Wm7eoV2a7TbFZE+gws/ 6BRwA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2600:3c0a:e001:78e:0:1991:8:25; envelope-from=fustini@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1769990380010158500 From: Nicolas Pitre Implement a bandwidth controller according to the Capacity and Bandwidth QoS Register Interface (CBQRI) which supports these capabilities: - Number of access types: 2 (code and data) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None, Total read/write byte count, Total read byte count, Total write byte count - Bandwidth allocation operations: CONFIG_LIMIT, READ_LIMIT Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Signed-off-by: Nicolas Pitre [fustini: add fields introduced in the ratified spec: rpfx and p] Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + hw/riscv/cbqri_bandwidth.c | 638 +++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 639 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 99f4c12f3b92..3c10cd154635 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -362,6 +362,7 @@ M: Nicolas Pitre M: Drew Fustini L: qemu-riscv@nongnu.org S: Supported +F: hw/riscv/cbqri_bandwidth.c F: hw/riscv/cbqri_capacity.c F: include/hw/riscv/cbqri.h =20 diff --git a/hw/riscv/cbqri_bandwidth.c b/hw/riscv/cbqri_bandwidth.c new file mode 100644 index 000000000000..f86b3bf75027 --- /dev/null +++ b/hw/riscv/cbqri_bandwidth.c @@ -0,0 +1,638 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 + * + * Copyright (c) 2023 BayLibre SAS + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This file contains the Bandwidth-controller QoS Register Interface. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/cbqri.h" + +/* Encodings of `AT` field */ +enum { + BC_AT_DATA =3D 0, + BC_AT_CODE =3D 1, +}; + +/* Capabilities */ +REG64(BC_CAPABILITIES, 0); +FIELD(BC_CAPABILITIES, VER, 0, 8); +FIELD(BC_CAPABILITIES, VER_MINOR, 0, 4); +FIELD(BC_CAPABILITIES, VER_MAJOR, 4, 4); +FIELD(BC_CAPABILITIES, NBWBLKS, 8, 16); +FIELD(BC_CAPABILITIES, RPFX, 24, 1); +FIELD(BC_CAPABILITIES, P, 25, 4); +FIELD(BC_CAPABILITIES, MRBWB, 32, 16); + +/* Usage monitoring control */ +REG64(BC_MON_CTL, 8); +FIELD(BC_MON_CTL, OP, 0, 5); +FIELD(BC_MON_CTL, AT, 5, 3); +FIELD(BC_MON_CTL, MCID, 8, 12); +FIELD(BC_MON_CTL, EVT_ID, 20, 8); +FIELD(BC_MON_CTL, ATV, 28, 1); +FIELD(BC_MON_CTL, STATUS, 32, 7); +FIELD(BC_MON_CTL, BUSY, 39, 1); + +/* Usage monitoring operations */ +enum { + BC_MON_OP_CONFIG_EVENT =3D 1, + BC_MON_OP_READ_COUNTER =3D 2, +}; + +/* Bandwidth monitoring event ID */ +enum { + BC_EVT_ID_None =3D 0, + BC_EVT_ID_RDWR_count =3D 1, + BC_EVT_ID_RDONLY_count =3D 2, + BC_EVT_ID_WRONLY_count =3D 3, +}; + +/* BC_MON_CTL.STATUS field encodings */ +enum { + BC_MON_CTL_STATUS_SUCCESS =3D 1, + BC_MON_CTL_STATUS_INVAL_OP =3D 2, + BC_MON_CTL_STATUS_INVAL_MCID =3D 3, + BC_MON_CTL_STATUS_INVAL_EVT_ID =3D 4, + BC_MON_CTL_STATUS_INVAL_AT =3D 5, +}; + +/* Monitoring counter value */ +REG64(BC_MON_CTR_VAL, 16); +FIELD(BC_MON_CTR_VAL, CTR, 0, 62); +FIELD(BC_MON_CTR_VAL, INVALID, 62, 1); +FIELD(BC_MON_CTR_VAL, OVF, 63, 1); + +/* Bandwidth Allocation control */ +REG64(BC_ALLOC_CTL, 24); +FIELD(BC_ALLOC_CTL, OP, 0, 5); +FIELD(BC_ALLOC_CTL, AT, 5, 3); +FIELD(BC_ALLOC_CTL, RCID, 8, 12); +FIELD(BC_ALLOC_CTL, STATUS, 32, 7); +FIELD(BC_ALLOC_CTL, BUSY, 39, 1); + +/* Bandwidth allocation operations */ +enum { + BC_ALLOC_OP_CONFIG_LIMIT =3D 1, + BC_ALLOC_OP_READ_LIMIT =3D 2, +}; + +/* BC_ALLOC_CTL.STATUS field encodings */ +enum { + BC_ALLOC_STATUS_SUCCESS =3D 1, + BC_ALLOC_STATUS_INVAL_OP =3D 2, + BC_ALLOC_STATUS_INVAL_RCID =3D 3, + BC_ALLOC_STATUS_INVAL_AT =3D 4, + BC_ALLOC_STATUS_INVAL_BLKS =3D 5, +}; + +/* Bandwidth allocation */ +REG64(BC_BW_ALLOC, 32); +FIELD(BC_BW_ALLOC, Rbwb, 0, 16); +FIELD(BC_BW_ALLOC, Mweight, 20, 8); +FIELD(BC_BW_ALLOC, sharedAT, 28, 3); +FIELD(BC_BW_ALLOC, useShared, 31, 1); + + +typedef struct MonitorCounter { + uint64_t ctr_val; + int at; + int evt_id; + bool active; +} MonitorCounter; + +typedef struct BandwidthAllocation { + uint32_t Rbwb:16; + uint32_t Mweight:8; + uint32_t sharedAT:3; + bool useShared:1; +} BandwidthAllocation; + +typedef struct RiscvCbqriBandwidthState { + SysBusDevice parent_obj; + MemoryRegion mmio; + + /* cached value of some registers */ + uint64_t bc_mon_ctl; + uint64_t bc_mon_ctr_val; + uint64_t bc_alloc_ctl; + uint64_t bc_bw_alloc; + + MonitorCounter *mon_counters; + BandwidthAllocation *bw_allocations; + + /* properties */ + + uint64_t mmio_base; + char *target; + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t nbwblks; + uint16_t mrbwb; + + bool supports_at_data; + bool supports_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_rdwr_count; + bool supports_mon_evt_id_rdonly_count; + bool supports_mon_evt_id_wronly_count; +} RiscvCbqriBandwidthState; + +#define RISCV_CBQRI_BC(obj) \ + OBJECT_CHECK(RiscvCbqriBandwidthState, (obj), TYPE_RISCV_CBQRI_BC) + +static BandwidthAllocation *get_bw_alloc(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at) +{ + /* + * All bandwidth allocation records are contiguous to simplify + * allocation. The first one is used to hold the BC_BW_ALLOC register + * content, followed by respective records for each AT per RCID. + */ + + unsigned int nb_ats =3D 0; + nb_ats +=3D !!bc->supports_at_data; + nb_ats +=3D !!bc->supports_at_code; + nb_ats =3D MAX(nb_ats, 1); + assert(at < nb_ats); + + return &bc->bw_allocations[1 + rcid * nb_ats + at]; +} + +static uint32_t bandwidth_config(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + BandwidthAllocation *bw_alloc =3D get_bw_alloc(bc, rcid, at); + + /* + * Bandwidth is allocated in multiples of bandwidth blocks, and the + * value in Rbwb must be at least 1 and must not exceed MRBWB value. + */ + if (bc->bw_allocations[0].Rbwb < 1) { + return BC_ALLOC_STATUS_INVAL_OP; + } else if (bc->bw_allocations[0].Rbwb > bc->mrbwb) { + return BC_ALLOC_STATUS_INVAL_OP; + } + + /* Save contents of BC_BW_ALLOC register for this rcid and at */ + *bw_alloc =3D bc->bw_allocations[0]; + return BC_ALLOC_STATUS_SUCCESS; +} + +static uint32_t bandwidth_read(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + BandwidthAllocation *bw_alloc =3D get_bw_alloc(bc, rcid, at); + + /* Populate BC_BW_ALLOC register with selected content */ + bc->bw_allocations[0] =3D *bw_alloc; + return BC_ALLOC_STATUS_SUCCESS; +} + +static bool is_valid_at(RiscvCbqriBandwidthState *bc, uint32_t at) +{ + switch (at) { + case BC_AT_DATA: + return bc->supports_at_data; + case BC_AT_CODE: + return bc->supports_at_code; + default: + return false; + } +} + +static void riscv_cbqri_bc_write_mon_ctl(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (!bc->supports_mon_op_config_event && + !bc->supports_mon_op_read_counter) { + /* monitoring not supported: leave mon_ctl set to 0 */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, BC_MON_CTL, OP); + uint32_t at =3D FIELD_EX64(value, BC_MON_CTL, AT); + uint32_t mcid =3D FIELD_EX64(value, BC_MON_CTL, MCID); + uint32_t evt_id =3D FIELD_EX64(value, BC_MON_CTL, EVT_ID); + bool atv =3D FIELD_EX64(value, BC_MON_CTL, ATV); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(bc->bc_mon_ctl, BC_MON_CTL, STATUS); + bool busy =3D FIELD_EX64(bc->bc_mon_ctl, BC_MON_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + if (!bc->supports_at_data && + !bc->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (mcid >=3D bc->nb_mcids) { + status =3D BC_MON_CTL_STATUS_INVAL_MCID; + } else if (op =3D=3D BC_MON_OP_CONFIG_EVENT && + bc->supports_mon_op_config_event) { + if (evt_id =3D=3D BC_EVT_ID_None && + bc->supports_mon_evt_id_none) { + bc->mon_counters[mcid].active =3D false; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } else if ((evt_id =3D=3D BC_EVT_ID_RDWR_count && + bc->supports_mon_evt_id_rdwr_count) || + (evt_id =3D=3D BC_EVT_ID_RDONLY_count && + bc->supports_mon_evt_id_rdonly_count) || + (evt_id =3D=3D BC_EVT_ID_WRONLY_count && + bc->supports_mon_evt_id_wronly_count)) { + if (atv && !is_valid_at(bc, at)) { + status =3D BC_MON_CTL_STATUS_INVAL_AT; + } else { + bc->mon_counters[mcid].ctr_val =3D + FIELD_DP64(0, BC_MON_CTR_VAL, INVALID, 1); + bc->mon_counters[mcid].evt_id =3D evt_id; + bc->mon_counters[mcid].at =3D atv ? at : -1; + bc->mon_counters[mcid].active =3D true; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } + } else { + status =3D BC_MON_CTL_STATUS_INVAL_EVT_ID; + } + } else if (op =3D=3D BC_MON_OP_READ_COUNTER && + bc->supports_mon_op_read_counter) { + bc->bc_mon_ctr_val =3D bc->mon_counters[mcid].ctr_val; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } else { + status =3D BC_MON_CTL_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, BC_MON_CTL, OP, op); + value =3D FIELD_DP64(value, BC_MON_CTL, AT, at); + value =3D FIELD_DP64(value, BC_MON_CTL, MCID, mcid); + value =3D FIELD_DP64(value, BC_MON_CTL, EVT_ID, evt_id); + value =3D FIELD_DP64(value, BC_MON_CTL, ATV, atv); + value =3D FIELD_DP64(value, BC_MON_CTL, STATUS, status); + value =3D FIELD_DP64(value, BC_MON_CTL, BUSY, busy); + bc->bc_mon_ctl =3D value; +} + +static void riscv_cbqri_bc_write_alloc_ctl(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (bc->nbwblks =3D=3D 0 || + (!bc->supports_alloc_op_config_limit && + !bc->supports_alloc_op_read_limit)) { + /* capacity allocation not supported: leave bc_alloc_ctl set to 0 = */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, BC_ALLOC_CTL, OP); + uint32_t at =3D FIELD_EX64(value, BC_ALLOC_CTL, AT); + uint32_t rcid =3D FIELD_EX64(value, BC_ALLOC_CTL, RCID); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(bc->bc_alloc_ctl, BC_ALLOC_CTL, STATUS); + bool busy =3D FIELD_EX64(bc->bc_alloc_ctl, BC_ALLOC_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + bool atv =3D true; + if (!bc->supports_at_data && + !bc->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (rcid >=3D bc->nb_rcids) { + status =3D BC_ALLOC_STATUS_INVAL_RCID; + } else if (atv && !is_valid_at(bc, at)) { + status =3D BC_ALLOC_STATUS_INVAL_AT; + } else if (op =3D=3D BC_ALLOC_OP_CONFIG_LIMIT && + bc->supports_alloc_op_config_limit) { + status =3D bandwidth_config(bc, rcid, at, &busy); + } else if (op =3D=3D BC_ALLOC_OP_READ_LIMIT && + bc->supports_alloc_op_read_limit) { + status =3D bandwidth_read(bc, rcid, at, &busy); + } else { + status =3D BC_ALLOC_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, BC_ALLOC_CTL, OP, op); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, AT, at); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, RCID, rcid); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, STATUS, status); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, BUSY, busy); + bc->bc_alloc_ctl =3D value; +} + +static void riscv_cbqri_bc_write_bw_alloc(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (bc->nbwblks =3D=3D 0) { + /* capacity allocation not supported: leave bw_alloc set to 0 */ + return; + } + + BandwidthAllocation *bc_bw_alloc =3D &bc->bw_allocations[0]; + + /* extract writable fields */ + bc_bw_alloc->Rbwb =3D FIELD_EX64(value, BC_BW_ALLOC, Rbwb); + bc_bw_alloc->Mweight =3D FIELD_EX64(value, BC_BW_ALLOC, Mweight); + bc_bw_alloc->sharedAT =3D FIELD_EX64(value, BC_BW_ALLOC, sharedAT); + bc_bw_alloc->useShared =3D FIELD_EX64(value, BC_BW_ALLOC, useShared); + + if (!bc->supports_at_data && + !bc->supports_at_code) { + /* AT not supported: hardwire to 0 */ + bc_bw_alloc->sharedAT =3D 0; + bc_bw_alloc->useShared =3D false; + } +} + +static void riscv_cbqri_bc_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + RiscvCbqriBandwidthState *bc =3D opaque; + + assert((addr % 8) =3D=3D 0); + + switch (addr) { + case A_BC_CAPABILITIES: + /* read-only register */ + break; + case A_BC_MON_CTL: + riscv_cbqri_bc_write_mon_ctl(bc, value); + break; + case A_BC_MON_CTR_VAL: + /* read-only register */ + break; + case A_BC_ALLOC_CTL: + riscv_cbqri_bc_write_alloc_ctl(bc, value); + break; + case A_BC_BW_ALLOC: + riscv_cbqri_bc_write_bw_alloc(bc, value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + } +} + +static uint64_t riscv_cbqri_bc_read(void *opaque, hwaddr addr, unsigned si= ze) +{ + RiscvCbqriBandwidthState *bc =3D opaque; + uint64_t value =3D 0; + + assert((addr % 8) =3D=3D 0); + + switch (addr) { + case A_BC_CAPABILITIES: + value =3D FIELD_DP64(value, BC_CAPABILITIES, VER_MAJOR, + RISCV_CBQRI_VERSION_MAJOR); + value =3D FIELD_DP64(value, BC_CAPABILITIES, VER_MINOR, + RISCV_CBQRI_VERSION_MINOR); + value =3D FIELD_DP64(value, BC_CAPABILITIES, RPFX, 0); + value =3D FIELD_DP64(value, BC_CAPABILITIES, P, 0); + value =3D FIELD_DP64(value, BC_CAPABILITIES, NBWBLKS, bc->nbwblks); + value =3D FIELD_DP64(value, BC_CAPABILITIES, MRBWB, bc->mrbwb); + break; + case A_BC_MON_CTL: + value =3D bc->bc_mon_ctl; + break; + case A_BC_MON_CTR_VAL: + value =3D bc->bc_mon_ctr_val; + break; + case A_BC_ALLOC_CTL: + value =3D bc->bc_alloc_ctl; + break; + case A_BC_BW_ALLOC: + BandwidthAllocation *bc_bw_alloc =3D &bc->bw_allocations[0]; + value =3D FIELD_DP64(value, BC_BW_ALLOC, Rbwb, bc_bw_alloc->Rbwb); + value =3D FIELD_DP64(value, BC_BW_ALLOC, Mweight, bc_bw_alloc->Mwe= ight); + value =3D FIELD_DP64(value, BC_BW_ALLOC, sharedAT, bc_bw_alloc->sh= aredAT); + value =3D FIELD_DP64(value, BC_BW_ALLOC, useShared, + bc_bw_alloc->useShared); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + } + + return value; +} + +static uint64_t riscv_cbqri_bc_read_wrapper(void *opaque, hwaddr addr, + unsigned size) +{ + uint64_t value =3D riscv_cbqri_bc_read(opaque, addr & ~0x7UL, 8); + if (size =3D=3D 4) { + if (addr & 0x7) { + return value >> 32; + } else { + return value & 0xffffffff; + } + } + return value; +} + +static void riscv_cbqri_bc_write_wrapper(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + if (size =3D=3D 4) { + uint64_t reg =3D riscv_cbqri_bc_read(opaque, addr & ~0x7UL, 8); + if (addr & 0x7) { + value =3D value << 32 | (reg & 0xffffffff); + } else { + value =3D value | (reg & ~0xffffffffUL); + } + } + riscv_cbqri_bc_write(opaque, addr & ~0x7UL, value, 8); +} + + +static const MemoryRegionOps riscv_cbqri_bc_ops =3D { + .read =3D riscv_cbqri_bc_read_wrapper, + .write =3D riscv_cbqri_bc_write_wrapper, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 8, +}; + +static void riscv_cbqri_bc_realize(DeviceState *dev, Error **errp) +{ + RiscvCbqriBandwidthState *bc =3D RISCV_CBQRI_BC(dev); + + if (!bc->mmio_base) { + error_setg(errp, "mmio_base property not set"); + return; + } + + assert(bc->mon_counters =3D=3D NULL); + bc->mon_counters =3D g_new0(MonitorCounter, bc->nb_mcids); + + assert(bc->bw_allocations =3D=3D NULL); + BandwidthAllocation *bw_alloc_end =3D get_bw_alloc(bc, bc->nb_rcids, 0= ); + unsigned int bw_alloc_size =3D bw_alloc_end - bc->bw_allocations; + bc->bw_allocations =3D g_new0(BandwidthAllocation, bw_alloc_size); + + memory_region_init_io(&bc->mmio, OBJECT(dev), &riscv_cbqri_bc_ops, + bc, TYPE_RISCV_CBQRI_BC".mmio", 4 * 1024); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &bc->mmio); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, bc->mmio_base); +} + +static void riscv_cbqri_bc_reset(DeviceState *dev) +{ + RiscvCbqriBandwidthState *bc =3D RISCV_CBQRI_BC(dev); + + bc->bc_mon_ctl =3D 0; + bc->bc_alloc_ctl =3D 0; +} + +static Property riscv_cbqri_bc_properties[] =3D { + DEFINE_PROP_UINT64("mmio_base", RiscvCbqriBandwidthState, mmio_base, 0= ), + DEFINE_PROP_STRING("target", RiscvCbqriBandwidthState, target), + + DEFINE_PROP_UINT16("max_mcids", RiscvCbqriBandwidthState, nb_mcids, 25= 6), + DEFINE_PROP_UINT16("max_rcids", RiscvCbqriBandwidthState, nb_rcids, 64= ), + DEFINE_PROP_UINT16("nbwblks", RiscvCbqriBandwidthState, nbwblks, 1024), + DEFINE_PROP_UINT16("mrbwb", RiscvCbqriBandwidthState, mrbwb, 819), + + DEFINE_PROP_BOOL("at_data", RiscvCbqriBandwidthState, + supports_at_data, true), + DEFINE_PROP_BOOL("at_code", RiscvCbqriBandwidthState, + supports_at_code, true), + + DEFINE_PROP_BOOL("alloc_op_config_limit", RiscvCbqriBandwidthState, + supports_alloc_op_config_limit, true), + DEFINE_PROP_BOOL("alloc_op_read_limit", RiscvCbqriBandwidthState, + supports_alloc_op_read_limit, true), + + DEFINE_PROP_BOOL("mon_op_config_event", RiscvCbqriBandwidthState, + supports_mon_op_config_event, true), + DEFINE_PROP_BOOL("mon_op_read_counter", RiscvCbqriBandwidthState, + supports_mon_op_read_counter, true), + + DEFINE_PROP_BOOL("mon_evt_id_none", RiscvCbqriBandwidthState, + supports_mon_evt_id_none, true), + DEFINE_PROP_BOOL("mon_evt_id_rdwr_count", RiscvCbqriBandwidthState, + supports_mon_evt_id_rdwr_count, true), + DEFINE_PROP_BOOL("mon_evt_id_rdonly_count", RiscvCbqriBandwidthState, + supports_mon_evt_id_rdonly_count, true), + DEFINE_PROP_BOOL("mon_evt_id_wronly_count", RiscvCbqriBandwidthState, + supports_mon_evt_id_wronly_count, true), +}; + +static void riscv_cbqri_bc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D riscv_cbqri_bc_realize; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc =3D "RISC-V CBQRI Bandwidth Controller"; + device_class_set_props(dc, riscv_cbqri_bc_properties); + dc->legacy_reset =3D riscv_cbqri_bc_reset; + dc->user_creatable =3D true; +} + +static const TypeInfo riscv_cbqri_bc_info =3D { + .name =3D TYPE_RISCV_CBQRI_BC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RiscvCbqriBandwidthState), + .class_init =3D riscv_cbqri_bc_class_init, +}; + +static void riscv_cbqri_bc_register_types(void) +{ + type_register_static(&riscv_cbqri_bc_info); +} + +DeviceState *riscv_cbqri_bc_create(hwaddr addr, + const RiscvCbqriBandwidthCaps *caps, + const char *target_name) +{ + DeviceState *dev =3D qdev_new(TYPE_RISCV_CBQRI_BC); + + qdev_prop_set_uint64(dev, "mmio_base", addr); + qdev_prop_set_string(dev, "target", target_name); + qdev_prop_set_uint16(dev, "max_mcids", caps->nb_mcids); + qdev_prop_set_uint16(dev, "max_rcids", caps->nb_rcids); + qdev_prop_set_uint16(dev, "nbwblks", caps->nbwblks); + + qdev_prop_set_bit(dev, "at_data", + caps->supports_at_data); + qdev_prop_set_bit(dev, "at_code", + caps->supports_at_code); + qdev_prop_set_bit(dev, "alloc_op_config_limit", + caps->supports_alloc_op_config_limit); + qdev_prop_set_bit(dev, "alloc_op_read_limit", + caps->supports_alloc_op_read_limit); + qdev_prop_set_bit(dev, "mon_op_config_event", + caps->supports_mon_op_config_event); + qdev_prop_set_bit(dev, "mon_op_read_counter", + caps->supports_mon_op_read_counter); + qdev_prop_set_bit(dev, "mon_evt_id_none", + caps->supports_mon_evt_id_none); + qdev_prop_set_bit(dev, "mon_evt_id_rdwr_count", + caps->supports_mon_evt_id_rdwr_count); + qdev_prop_set_bit(dev, "mon_evt_id_rdonly_count", + caps->supports_mon_evt_id_rdonly_count); + qdev_prop_set_bit(dev, "mon_evt_id_wronly_count", + caps->supports_mon_evt_id_wronly_count); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + return dev; +} + +type_init(riscv_cbqri_bc_register_types) --=20 2.43.0