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Sun, 1 Feb 2026 23:58:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7A0D0C4AF0B; Sun, 1 Feb 2026 23:58:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769990293; bh=7PBKYqI5XMpagFd21xzmh3DIpzHMfcpMSp6vyVCkpXI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=FsNRc/5ebtCi2T/Yh48Q+UhmeKb+TzCtp2W/eOMPGwV9VLDms2Kvhnmycz1ZabE80 rEJzkevj++nI4QkgHoiaHnLKdcFwkqCoBjIU6pTvT6znBMpdpVsM5Vc87VEpGaovTb kEVYhEaORB7eIfz8pOk6Tot9rmNLVkM/QRMGMNK4fh23bkxZdndNYPMAnxiwI6vXXb oQMPPvfS0Z9UWUVSsT5XyGWg9Kij0E4tNnLBAI+kgGabvuFyXbc2LSrdkhXM9vieEf 1nbV6rlEvGmSodod+uyUozrFywX1TfuQVyIK2uTGvYFiclxuiZT8uFx073gd67Dl++ MHKSwMgcEDY1w== From: Drew Fustini Date: Sun, 01 Feb 2026 15:58:07 -0800 Subject: [PATCH v5 1/6] riscv: implement Ssqosid extension and srmcfg CSR MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260201-riscv-ssqosid-cbqri-v5-1-273ea4a21703@kernel.org> References: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> In-Reply-To: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=6693; i=fustini@kernel.org; h=from:subject:message-id; bh=xYM47oqTdnfm4nufTRjEyNgDVz96xV9bD7l4VUuUTuw=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTWv5gS8S+bparzpie/7GSn6tXHY6KC+9o3836SFCi8v b08I+F2RykLgxgXg6yYIsumD3kXlniFfl0w/8U2mDmsTCBDGLg4BWAi7h8Z/ns/uiGy9+uDKzeX zF19zN7uKtc+5p6rF28dvR54ufT0yQPyDP8zk542uDjk1kQe4rerCDy00M42VlJAQ37aIv0VU1/ rTuYBAA== X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.234.252.31; envelope-from=fustini@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1769990367890158500 From: Kornel Dul=C4=99ba Implement the srmcfg CSR defined by the Ssqosid ISA extension (Supervisor-mode Quality of Service ID). The CSR contains two fields: - Resource Control ID (RCID) used determine resource allocation - Monitoring Counter ID (MCID) used to track resource usage The CSR is defined for S-mode, so check mstateen0.srmcfg to determine if s-mode is allowed to access it. In addition, accessing it when V=3D1 shall cause a virtual instruction exception. Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/download/v1.0/r= iscv-cbqri.pdf Link: https://docs.riscv.org/reference/isa/priv/smstateen.html Signed-off-by: Kornel Dul=C4=99ba [fustini: rebase on v10.1.50, fix check_srmcfg] Signed-off-by: Drew Fustini --- disas/riscv.c | 1 + target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 3 +++ target/riscv/cpu_bits.h | 9 +++++++++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/csr.c | 37 +++++++++++++++++++++++++++++++++++= ++ 6 files changed, 53 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 85cd2a9c2aef..86fc710528c1 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -2289,6 +2289,7 @@ static const char *csr_name(int csrno) case 0x0143: return "stval"; case 0x0144: return "sip"; case 0x0180: return "satp"; + case 0x0181: return "srmcfg"; case 0x0200: return "hstatus"; case 0x0202: return "hedeleg"; case 0x0203: return "hideleg"; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8f26d8b8b076..f665308896e5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -216,6 +216,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp), ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm), ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm), + ISA_EXT_DATA_ENTRY(ssqosid, PRIV_VERSION_1_13_0, ext_ssqosid), ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), @@ -1268,6 +1269,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false), MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false), MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), + MULTI_EXT_CFG_BOOL("ssqosid", ext_ssqosid, true), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), MULTI_EXT_CFG_BOOL("sspm", ext_sspm, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 90b3e951053a..20c2eada1014 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -336,6 +336,9 @@ struct CPUArchState { uint64_t ctr_dst[16 << SCTRDEPTH_MAX]; uint64_t ctr_data[16 << SCTRDEPTH_MAX]; =20 + /* Ssqosid extension */ + target_ulong srmcfg; + /* Machine and Supervisor interrupt priorities */ uint8_t miprio[64]; uint8_t siprio[64]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7c0..bd73f9232d70 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -228,6 +228,9 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 =20 +/* Ssqosid extension */ +#define CSR_SRMCFG 0x181 + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 @@ -356,6 +359,7 @@ #define SMSTATEEN0_FCSR (1ULL << 1) #define SMSTATEEN0_JVT (1ULL << 2) #define SMSTATEEN0_CTR (1ULL << 54) +#define SMSTATEEN0_SRMCFG (1ULL << 55) #define SMSTATEEN0_P1P13 (1ULL << 56) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) @@ -1164,4 +1168,9 @@ typedef enum CTRType { #define MCONTEXT64 0x0000000000001FFFULL #define MCONTEXT32_HCONTEXT 0x0000007F #define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL + +/* SRMCFG CSR field masks (Ssqosid extensions) */ +#define SRMCFG_RCID 0x00000FFF +#define SRMCFG_MCID 0x0FFF0000 + #endif diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index a154ecdc792b..6518f6f9c571 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -105,6 +105,7 @@ BOOL_FIELD(ext_ssaia) BOOL_FIELD(ext_smctr) BOOL_FIELD(ext_ssctr) BOOL_FIELD(ext_sscofpmf) +BOOL_FIELD(ext_ssqosid) BOOL_FIELD(ext_smepmp) BOOL_FIELD(ext_smrnmi) BOOL_FIELD(ext_ssnpm) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c91658c3dc4..298829c0239f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1759,6 +1759,40 @@ static RISCVException write_stimecmph(CPURISCVState = *env, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException check_srmcfg(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_ssqosid) { + return RISCV_EXCP_ILLEGAL_INST; + } + + RISCVException ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SRMCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + /* + * Even though this is an S-mode CSR the spec says that we need to thr= ow + * and virt instruction fault if a guest tries to access it. + */ + return env->virt_enabled ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : smode(env, csrno); +} + +static RISCVException read_srmcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->srmcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_srmcfg(CPURISCVState *env, int csrno, + target_ulong val, uintptr_t ra) +{ + env->srmcfg =3D val & (SRMCFG_RCID | SRMCFG_MCID); + return RISCV_EXCP_NONE; +} + + #define VSTOPI_NUM_SRCS 5 =20 /* @@ -6035,6 +6069,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", satp, read_satp, write_satp }, =20 + /* Supervisor-Level Quality-of-Service Identifiers (Ssqosid) */ + [CSR_SRMCFG] =3D { "srmcfg", check_srmcfg, read_srmcfg, write_srmcf= g }, + /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ [CSR_SISELECT] =3D { "siselect", csrind_or_aia_smode, NULL, NULL, rmw_xiselect = }, --=20 2.43.0 From nobody Mon Feb 9 13:46:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 1 Feb 2026 23:58:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CDF2AC2BC86; Sun, 1 Feb 2026 23:58:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769990294; bh=87yUqJH6aCJ3Tzr0TY4MD9gaivxrl+oPobd3+WA3yRw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=BJXJifkLslSVQ0VsnL+UdtbLc+hFJNuWn+fvdD2tCJsaQfZfwF3FZzqDUoYdLsuZq H8MnpikJcH9o+IhvSiyOlxjgd8Rh1FoNVrve5EGtP1xFSY+4wBKtYvvyEYX3VpK9gY X1k2Zb5k04uqpkx0x3xFnmBtV2LX3J1QDZ76PIqtM6PTG87ZcRCc1EZiVy0sOGH+Um DyBEYUuK5i8Ft43V7BtVnWSeS4QOsnRiuqz6bOYpmYIHHk/jprL53S5Zo9ZeWyudTk e1x9qzdPaw62Jw3KJyvkAOxwf01bKyFqCWv3Ln7WL3TSa5vrexdR3QUNriZ3l92EAf CUitUHaHecHJQ== From: Drew Fustini Date: Sun, 01 Feb 2026 15:58:08 -0800 Subject: [PATCH v5 2/6] hw/riscv: define capabilities of CBQRI controllers MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260201-riscv-ssqosid-cbqri-v5-2-273ea4a21703@kernel.org> References: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> In-Reply-To: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4086; i=fustini@kernel.org; h=from:subject:message-id; bh=DEQYQbjVSlboGU+BOdVfGwtVHZcRjAKo5oA3AsVDxuE=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTWv5hSaP7dwFihdc6M1WafWQyOfpryVSP6zWXXZ3I9m 2NW2C1S6ihlYRDjYpAVU2TZ9CHvwhKv0K8L5r/YBjOHlQlkCAMXpwBMZH8vw38np46naa157mUB JmedVI9XPIt0O1ZRaev0pjb8zPMI/wcM/zTvWj0uqfognl8Qq7Nlh+6PXVc/LRRpXXPs9s6fYoU qZowA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2600:3c0a:e001:78e:0:1991:8:25; envelope-from=fustini@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1769990379944158500 From: Nicolas Pitre Define structs to represent the hardware capabilities of capacity and bandwidth controllers according to the RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI). Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Signed-off-by: Nicolas Pitre Reviewed-by: Daniel Henrique Barboza Signed-off-by: Drew Fustini --- MAINTAINERS | 7 +++++ include/hw/riscv/cbqri.h | 82 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 89 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cbae7c26f83e..9d1b2b411010 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -357,6 +357,13 @@ F: target/riscv/XVentanaCondOps.decode F: target/riscv/insn_trans/trans_xventanacondops.c.inc F: disas/riscv-xventana* =20 +RISC-V QoS (Ssqosid ext and CBQRI spec) +M: Nicolas Pitre +M: Drew Fustini +L: qemu-riscv@nongnu.org +S: Supported +F: include/hw/riscv/cbqri.h + RENESAS RX CPUs R: Yoshinori Sato S: Orphan diff --git a/include/hw/riscv/cbqri.h b/include/hw/riscv/cbqri.h new file mode 100644 index 000000000000..a07f1e3a2dde --- /dev/null +++ b/include/hw/riscv/cbqri.h @@ -0,0 +1,82 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 + * + * Copyright (c) 2023 BayLibre SAS + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_RISCV_CBQRI_H +#define HW_RISCV_CBQRI_H + +#include "qemu/typedefs.h" + +#define RISCV_CBQRI_VERSION_MAJOR 0 +#define RISCV_CBQRI_VERSION_MINOR 1 + +#define TYPE_RISCV_CBQRI_CC "riscv.cbqri.capacity" +#define TYPE_RISCV_CBQRI_BC "riscv.cbqri.bandwidth" + +/* Capacity Controller hardware capabilities */ +typedef struct RiscvCbqriCapacityCaps { + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t ncblks; + + bool supports_at_data:1; + bool supports_at_code:1; + + bool supports_alloc_op_config_limit:1; + bool supports_alloc_op_read_limit:1; + bool supports_alloc_op_flush_rcid:1; + + bool supports_mon_op_config_event:1; + bool supports_mon_op_read_counter:1; + + bool supports_mon_evt_id_none:1; + bool supports_mon_evt_id_occupancy:1; +} RiscvCbqriCapacityCaps; + +/* Bandwidth Controller hardware capabilities */ +typedef struct RiscvCbqriBandwidthCaps { + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t nbwblks; + uint16_t mrbwb; + + bool supports_at_data:1; + bool supports_at_code:1; + + bool supports_alloc_op_config_limit:1; + bool supports_alloc_op_read_limit:1; + + bool supports_mon_op_config_event:1; + bool supports_mon_op_read_counter:1; + + bool supports_mon_evt_id_none:1; + bool supports_mon_evt_id_rdwr_count:1; + bool supports_mon_evt_id_rdonly_count:1; + bool supports_mon_evt_id_wronly_count:1; +} RiscvCbqriBandwidthCaps; + +DeviceState *riscv_cbqri_cc_create(hwaddr addr, + const RiscvCbqriCapacityCaps *caps, + const char *target_name); +DeviceState *riscv_cbqri_bc_create(hwaddr addr, + const RiscvCbqriBandwidthCaps *caps, + const char *target_name); +#endif --=20 2.43.0 From nobody Mon Feb 9 13:46:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1769990384; 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bh=B4SLdxxADNjnGyie4UvrB0lWf8dY87STFGBFxEf3Me8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=l+rky28M/ks0Qbglvlk5g1gJ18Oq6e1JoFABbsI4x+ljvO9YBvUgVRKEItZCklVos FoXuxU19EZQ3dXKvmxK6idJj9MrmLzNR8suovwGF3jMbwR8J5dVsFT6uAtkzS0RbCv YyGPaKAEVu6vIQJVk+zMTpaXpZmW8dC2rMSGp5i3wu37N1dYLkbzg9VL/SlqQnxl49 q3SMMEtXunFeYGWXDNlNqYlfObg0TIHTLGfgMlVHsrF9HW/GLPWFkRho9iSlGYaTG7 ckZS+tciwKj94n14QvMygZM4BlMCo712igizcuXcBet32LDqH5CvkH2b1BjsGcN9te Fh6XtpKqaZ0Ag== From: Drew Fustini Date: Sun, 01 Feb 2026 15:58:09 -0800 Subject: [PATCH v5 3/6] hw/riscv: implement CBQRI capacity controller MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260201-riscv-ssqosid-cbqri-v5-3-273ea4a21703@kernel.org> References: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> In-Reply-To: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=26815; i=fustini@kernel.org; h=from:subject:message-id; bh=wqC/zYuiirAzjf4Qz1zwa2Dce+aJTOR4GSUGb7fbeCU=; b=kA0DAAoW2+wsw9kosQwByyZiAGl/6JSj5VDAMq4eI0gw6CCdRcSYlxeWcwHegVmKjusKzuMFJ Ih1BAAWCgAdFiEEsvBu0KRKVfWgn+i22+wsw9kosQwFAml/6JQACgkQ2+wsw9kosQwJQwD/Tk/1 UlfG695G6/INLDQ3keOh8N1pTrgzdFzPWHZuMN0A/A+hiNfkocPBWGG7Afd/df/3AomU+c4Pe77 SZARFxm8H X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2600:3c04:e001:324:0:1991:8:25; envelope-from=fustini@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1769990386069158500 From: Nicolas Pitre Implement a capacity controller according to the Capacity and Bandwidth QoS Register Interface (CBQRI) which supports these capabilities: - Number of access types: 2 (code and data) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None, Occupancy - Capacity allocation ops: CONFIG_LIMIT, READ_LIMIT, FLUSH_RCID Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Signed-off-by: Nicolas Pitre [fustini: add fields introduced in the ratified spec: cunits, rpfx, p] Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + hw/riscv/cbqri_capacity.c | 733 ++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 734 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9d1b2b411010..99f4c12f3b92 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -362,6 +362,7 @@ M: Nicolas Pitre M: Drew Fustini L: qemu-riscv@nongnu.org S: Supported +F: hw/riscv/cbqri_capacity.c F: include/hw/riscv/cbqri.h =20 RENESAS RX CPUs diff --git a/hw/riscv/cbqri_capacity.c b/hw/riscv/cbqri_capacity.c new file mode 100644 index 000000000000..1c3570262a36 --- /dev/null +++ b/hw/riscv/cbqri_capacity.c @@ -0,0 +1,733 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 + * + * Copyright (c) 2023 BayLibre SAS + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This file contains the Capacity-controller QoS Register Interface. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/bitmap.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/cbqri.h" + +/* Encodings of `AT` field */ +enum { + CC_AT_DATA =3D 0, + CC_AT_CODE =3D 1, +}; + +/* Capabilities */ +REG64(CC_CAPABILITIES, 0); +FIELD(CC_CAPABILITIES, VER, 0, 8); +FIELD(CC_CAPABILITIES, VER_MINOR, 0, 4); +FIELD(CC_CAPABILITIES, VER_MAJOR, 4, 4); +FIELD(CC_CAPABILITIES, NCBLKS, 8, 16); +FIELD(CC_CAPABILITIES, FRCID, 24, 1); +FIELD(CC_CAPABILITIES, CUNITS, 25, 1); +FIELD(CC_CAPABILITIES, RPFX, 26, 1); +FIELD(CC_CAPABILITIES, P, 27, 4); + +/* Usage monitoring control */ +REG64(CC_MON_CTL, 8); +FIELD(CC_MON_CTL, OP, 0, 5); +FIELD(CC_MON_CTL, AT, 5, 3); +FIELD(CC_MON_CTL, MCID, 8, 12); +FIELD(CC_MON_CTL, EVT_ID, 20, 8); +FIELD(CC_MON_CTL, ATV, 28, 1); +FIELD(CC_MON_CTL, STATUS, 32, 7); +FIELD(CC_MON_CTL, BUSY, 39, 1); + +/* Usage monitoring operations */ +enum { + CC_MON_OP_CONFIG_EVENT =3D 1, + CC_MON_OP_READ_COUNTER =3D 2, +}; + +/* Usage monitoring event ID */ +enum { + CC_EVT_ID_None =3D 0, + CC_EVT_ID_Occupancy =3D 1, +}; + +/* CC_MON_CTL.STATUS field encodings */ +enum { + CC_MON_CTL_STATUS_SUCCESS =3D 1, + CC_MON_CTL_STATUS_INVAL_OP =3D 2, + CC_MON_CTL_STATUS_INVAL_MCID =3D 3, + CC_MON_CTL_STATUS_INVAL_EVT_ID =3D 4, + CC_MON_CTL_STATUS_INVAL_AT =3D 5, +}; + +/* Monitoring counter value */ +REG64(CC_MON_CTR_VAL, 16); +FIELD(CC_MON_CTR_VAL, CTR, 0, 63); +FIELD(CC_MON_CTR_VAL, INVALID, 63, 1); + +/* Capacity allocation control */ +REG64(CC_ALLOC_CTL, 24); +FIELD(CC_ALLOC_CTL, OP, 0, 5); +FIELD(CC_ALLOC_CTL, AT, 5, 3); +FIELD(CC_ALLOC_CTL, RCID, 8, 12); +FIELD(CC_ALLOC_CTL, STATUS, 32, 7); +FIELD(CC_ALLOC_CTL, BUSY, 39, 1); + +/* Capacity allocation operations */ +enum { + CC_ALLOC_OP_CONFIG_LIMIT =3D 1, + CC_ALLOC_OP_READ_LIMIT =3D 2, + CC_ALLOC_OP_FLUSH_RCID =3D 3, +}; + +/* CC_ALLOC_CTL.STATUS field encodings */ +enum { + CC_ALLOC_STATUS_SUCCESS =3D 1, + CC_ALLOC_STATUS_INVAL_OP =3D 2, + CC_ALLOC_STATUS_INVAL_RCID =3D 3, + CC_ALLOC_STATUS_INVAL_AT =3D 4, + CC_ALLOC_STATUS_INVAL_BLKMASK =3D 5, +}; + +REG64(CC_BLOCK_MASK, 32); + + +typedef struct MonitorCounter { + uint64_t ctr_val; + int at; + int evt_id; + bool active; +} MonitorCounter; + +typedef struct RiscvCbqriCapacityState { + SysBusDevice parent_obj; + MemoryRegion mmio; + + /* cached value of some registers */ + uint64_t cc_mon_ctl; + uint64_t cc_mon_ctr_val; + uint64_t cc_alloc_ctl; + + /* monitoring counters */ + MonitorCounter *mon_counters; + + /* allocation blockmasks (1st one is the CC_BLOCK_MASK register) */ + uint64_t *alloc_blockmasks; + + /* properties */ + uint64_t mmio_base; + char *target; + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t ncblks; + + bool supports_at_data; + bool supports_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + bool supports_alloc_op_flush_rcid; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_occupancy; +} RiscvCbqriCapacityState; + +#define RISCV_CBQRI_CC(obj) \ + OBJECT_CHECK(RiscvCbqriCapacityState, (obj), TYPE_RISCV_CBQRI_CC) + +static inline unsigned int get_bmw(RiscvCbqriCapacityState *cc) +{ + unsigned int bmw =3D ((cc->ncblks + 63) / 64) * 64; + + return bmw; +} + +static inline unsigned int get_slots(RiscvCbqriCapacityState *cc) +{ + unsigned int slots =3D (cc->ncblks + 63) / 64; + + return slots; +} + +static uint64_t get_blockmask_offset(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at) +{ + /* + * Each blockmask is made of one or more uint64_t "slots". + * + * The first slot (or set of slots when BMW is great than 64) + * holds the CC_BLOCK_MASK register content. + * + * The following slot holds the the CC_CUNITS register content + * which has a fixed size of 8 bytes. + * + * The remaining slots contain the blockmask for each AT per RCID. + * + * For example, this would be the layout of the slots for a + * controller which has AT types Data and Code enabled and + * NCBLKS of 16. This results in a BMW of 64 so each blockmask + * can fit in 1 slot. The first 6 slots would be: + * + * Slot + * [ 0] register: CC_BLOCK_MASK + * [ 1] register: CC_CUNITS + * [ 2] RCID=3D 0 AT=3D0: cc_block_mask + * [ 3] RCID=3D 0 AT=3D1: cc_block_mask + * [ 4] RCID=3D 1 AT=3D0: cc_block_mask + * [ 5] RCID=3D 1 AT=3D1: cc_block_mask + * + * This would be the layout for NCBLKS of 100 and AT types Data + * and Code. BMW would be 128 so each blockmask takes 2 slots. + * The first 11 slots would be: + * + * Slot + * [ 0] register: CC_BLOCK_MASK + * [ 1] register: CC_BLOCK_MASK + * [ 2] register: CC_CUNITS + * [ 3] RCID=3D 0 AT=3D0: cc_block_mask + * [ 4] RCID=3D 0 AT=3D0: cc_block_mask + * [ 5] RCID=3D 0 AT=3D1: cc_block_mask + * [ 6] RCID=3D 0 AT=3D1: cc_block_mask + * [ 7] RCID=3D 1 AT=3D0: cc_block_mask + * [ 8] RCID=3D 1 AT=3D0: cc_block_mask + * [ 9] RCID=3D 1 AT=3D1: cc_block_mask + * [10] RCID=3D 1 AT=3D1: cc_block_mask + * + */ + unsigned int nb_ats =3D 0; + nb_ats +=3D !!cc->supports_at_data; + nb_ats +=3D !!cc->supports_at_code; + nb_ats =3D MAX(nb_ats, 1); + assert(at < nb_ats); + + unsigned int blockmask_offset; + unsigned int blockmask_slots =3D get_slots(cc); + blockmask_offset =3D blockmask_slots * ((rcid * nb_ats) + at); + + /* + * Add offset for cc_blockmask register in slot 0 to (blockmask_slots-= 1) + */ + blockmask_offset +=3D blockmask_slots; + + /* + * Add offset to account for cc_cunits register which is always 1 slot + */ + blockmask_offset +=3D 1; + + return blockmask_offset; +} + +static uint64_t *get_blockmask_location(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at) +{ + assert(cc->alloc_blockmasks !=3D NULL); + unsigned int blockmask_offset =3D get_blockmask_offset(cc, rcid, at); + return cc->alloc_blockmasks + blockmask_offset; +} + +static uint32_t alloc_blockmask_config(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + unsigned int blockmask_slots =3D get_slots(cc); + + if ((cc->ncblks % 64) !=3D 0) { + /* make sure provided mask isn't too large */ + uint64_t tail =3D cc->alloc_blockmasks[blockmask_slots - 1]; + if ((tail >> (cc->ncblks % 64)) !=3D 0) { + return CC_ALLOC_STATUS_INVAL_BLKMASK; + } + } + + /* for now we only preserve the current CC_BLOCK_MASK register content= */ + memcpy(get_blockmask_location(cc, rcid, at), + cc->alloc_blockmasks, blockmask_slots * 8); + return CC_ALLOC_STATUS_SUCCESS; +} + +static uint32_t alloc_blockmask_read(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + unsigned int blockmask_slots =3D get_slots(cc); + + memcpy(cc->alloc_blockmasks, + get_blockmask_location(cc, rcid, at), + blockmask_slots * 8); + return CC_ALLOC_STATUS_SUCCESS; +} + +static uint32_t alloc_blockmask_init(RiscvCbqriCapacityState *cc, + uint32_t rcid, uint32_t at, bool set, + bool *busy) +{ + void *blockmask =3D get_blockmask_location(cc, rcid, at); + + if (set) { + bitmap_fill(blockmask, cc->ncblks); + } else { + bitmap_zero(blockmask, cc->ncblks); + } + return CC_ALLOC_STATUS_SUCCESS; +} + +static bool is_valid_at(RiscvCbqriCapacityState *cc, uint32_t at) +{ + switch (at) { + case CC_AT_DATA: + return cc->supports_at_data; + case CC_AT_CODE: + return cc->supports_at_code; + default: + return false; + } +} + +static void riscv_cbqri_cc_write_mon_ctl(RiscvCbqriCapacityState *cc, + uint64_t value) +{ + if (!cc->supports_mon_op_config_event && + !cc->supports_mon_op_read_counter) { + /* monitoring not supported: leave mon_ctl set to 0 */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, CC_MON_CTL, OP); + uint32_t at =3D FIELD_EX64(value, CC_MON_CTL, AT); + uint32_t mcid =3D FIELD_EX64(value, CC_MON_CTL, MCID); + uint32_t evt_id =3D FIELD_EX64(value, CC_MON_CTL, EVT_ID); + bool atv =3D FIELD_EX64(value, CC_MON_CTL, ATV); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(cc->cc_mon_ctl, CC_MON_CTL, STATUS); + bool busy =3D FIELD_EX64(cc->cc_mon_ctl, CC_MON_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + if (!cc->supports_at_data && + !cc->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (mcid >=3D cc->nb_mcids) { + status =3D CC_MON_CTL_STATUS_INVAL_MCID; + } else if (op =3D=3D CC_MON_OP_CONFIG_EVENT && + cc->supports_mon_op_config_event) { + if (evt_id =3D=3D CC_EVT_ID_None && + cc->supports_mon_evt_id_none) { + cc->mon_counters[mcid].active =3D false; + status =3D CC_MON_CTL_STATUS_SUCCESS; + } else if (evt_id =3D=3D CC_EVT_ID_Occupancy && + cc->supports_mon_evt_id_occupancy) { + if (atv && !is_valid_at(cc, at)) { + status =3D CC_MON_CTL_STATUS_INVAL_AT; + } else { + cc->mon_counters[mcid].ctr_val =3D + FIELD_DP64(0, CC_MON_CTR_VAL, INVALID, 1); + cc->mon_counters[mcid].evt_id =3D evt_id; + cc->mon_counters[mcid].at =3D atv ? at : -1; + cc->mon_counters[mcid].active =3D true; + status =3D CC_MON_CTL_STATUS_SUCCESS; + } + } else { + status =3D CC_MON_CTL_STATUS_INVAL_EVT_ID; + } + } else if (op =3D=3D CC_MON_OP_READ_COUNTER && + cc->supports_mon_op_read_counter) { + cc->cc_mon_ctr_val =3D cc->mon_counters[mcid].ctr_val; + status =3D CC_MON_CTL_STATUS_SUCCESS; + } else { + status =3D CC_MON_CTL_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, CC_MON_CTL, OP, op); + value =3D FIELD_DP64(value, CC_MON_CTL, AT, at); + value =3D FIELD_DP64(value, CC_MON_CTL, MCID, mcid); + value =3D FIELD_DP64(value, CC_MON_CTL, EVT_ID, evt_id); + value =3D FIELD_DP64(value, CC_MON_CTL, ATV, atv); + value =3D FIELD_DP64(value, CC_MON_CTL, STATUS, status); + value =3D FIELD_DP64(value, CC_MON_CTL, BUSY, busy); + cc->cc_mon_ctl =3D value; +} + +static void riscv_cbqri_cc_write_alloc_ctl(RiscvCbqriCapacityState *cc, + uint64_t value) +{ + if (cc->ncblks =3D=3D 0 || + (!cc->supports_alloc_op_config_limit && + !cc->supports_alloc_op_read_limit && + !cc->supports_alloc_op_flush_rcid)) { + /* capacity allocation not supported: leave alloc_ctl set to 0 */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, CC_ALLOC_CTL, OP); + uint32_t at =3D FIELD_EX64(value, CC_ALLOC_CTL, AT); + uint32_t rcid =3D FIELD_EX64(value, CC_ALLOC_CTL, RCID); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(cc->cc_alloc_ctl, CC_ALLOC_CTL, STATUS); + bool busy =3D FIELD_EX64(cc->cc_alloc_ctl, CC_ALLOC_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + bool atv =3D true; + if (!cc->supports_at_data && + !cc->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (rcid >=3D cc->nb_rcids) { + status =3D CC_ALLOC_STATUS_INVAL_RCID; + } else if (atv && !is_valid_at(cc, at)) { + status =3D CC_ALLOC_STATUS_INVAL_AT; + } else if (op =3D=3D CC_ALLOC_OP_CONFIG_LIMIT && + cc->supports_alloc_op_config_limit) { + status =3D alloc_blockmask_config(cc, rcid, at, &busy); + } else if (op =3D=3D CC_ALLOC_OP_READ_LIMIT && + cc->supports_alloc_op_read_limit) { + status =3D alloc_blockmask_read(cc, rcid, at, &busy); + } else if (op =3D=3D CC_ALLOC_OP_FLUSH_RCID && + cc->supports_alloc_op_flush_rcid) { + /* + * The flush operation is not allowed to change the configured + * capacity block allocation or the capacity unit limit. + */ + status =3D CC_ALLOC_STATUS_SUCCESS; + } else { + status =3D CC_ALLOC_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, CC_ALLOC_CTL, OP, op); + value =3D FIELD_DP64(value, CC_ALLOC_CTL, AT, at); + value =3D FIELD_DP64(value, CC_ALLOC_CTL, RCID, rcid); + value =3D FIELD_DP64(value, CC_ALLOC_CTL, STATUS, status); + value =3D FIELD_DP64(value, CC_ALLOC_CTL, BUSY, busy); + cc->cc_alloc_ctl =3D value; +} + +static void riscv_cbqri_cc_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + RiscvCbqriCapacityState *cc =3D opaque; + + assert((addr % 8) =3D=3D 0); + + switch (addr) { + case A_CC_CAPABILITIES: + /* read-only register */ + break; + case A_CC_MON_CTL: + riscv_cbqri_cc_write_mon_ctl(cc, value); + break; + case A_CC_ALLOC_CTL: + riscv_cbqri_cc_write_alloc_ctl(cc, value); + break; + case A_CC_MON_CTR_VAL: + /* read-only register */ + break; + case A_CC_BLOCK_MASK: + if (cc->ncblks =3D=3D 0) { + break; + } + /* fallthrough */ + default: + uint32_t blkmask_slot =3D (addr - A_CC_BLOCK_MASK) / 8; + if (blkmask_slot =3D=3D get_slots(cc)) { + /* this is cc_cunits register */ + break; + } else if (blkmask_slot > get_slots(cc)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + break; + } + cc->alloc_blockmasks[blkmask_slot] =3D value; + } +} + +static uint64_t riscv_cbqri_cc_read(void *opaque, hwaddr addr, unsigned si= ze) +{ + RiscvCbqriCapacityState *cc =3D opaque; + uint64_t value =3D 0; + + assert((addr % 8) =3D=3D 0); + + switch (addr) { + case A_CC_CAPABILITIES: + value =3D FIELD_DP64(value, CC_CAPABILITIES, VER_MAJOR, + RISCV_CBQRI_VERSION_MAJOR); + value =3D FIELD_DP64(value, CC_CAPABILITIES, VER_MINOR, + RISCV_CBQRI_VERSION_MINOR); + value =3D FIELD_DP64(value, CC_CAPABILITIES, NCBLKS, + cc->ncblks); + value =3D FIELD_DP64(value, CC_CAPABILITIES, FRCID, + cc->supports_alloc_op_flush_rcid); + value =3D FIELD_DP64(value, CC_CAPABILITIES, CUNITS, 0); + value =3D FIELD_DP64(value, CC_CAPABILITIES, RPFX, 0); + value =3D FIELD_DP64(value, CC_CAPABILITIES, P, 0); + break; + case A_CC_MON_CTL: + value =3D cc->cc_mon_ctl; + break; + case A_CC_ALLOC_CTL: + value =3D cc->cc_alloc_ctl; + break; + case A_CC_MON_CTR_VAL: + value =3D cc->cc_mon_ctr_val; + break; + case A_CC_BLOCK_MASK: + if (cc->ncblks =3D=3D 0) { + break; + } + /* fallthrough */ + default: + unsigned int blkmask_slot =3D (addr - A_CC_BLOCK_MASK) / 8; + if (blkmask_slot =3D=3D get_slots(cc)) { + /* + * The cc_cunits register is always the slot following the + * last slot of cc_blockmask register. Capacity units are + * not supported by this implementation so must return 0. + */ + value =3D 0; + break; + } else if (blkmask_slot > get_slots(cc)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: out of bounds (addr=3D0x%x= )", + __func__, (uint32_t)addr); + break; + } + value =3D cc->alloc_blockmasks[blkmask_slot]; + } + + return value; +} + +static uint64_t riscv_cbqri_cc_read_wrapper(void *opaque, hwaddr addr, + unsigned size) +{ + uint64_t value =3D riscv_cbqri_cc_read(opaque, addr & ~0x7UL, 8); + if (size =3D=3D 4) { + if (addr & 0x7) { + return value >> 32; + } else { + return value & 0xffffffff; + } + } + return value; +} + +static void riscv_cbqri_cc_write_wrapper(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + if (size =3D=3D 4) { + uint64_t reg =3D riscv_cbqri_cc_read(opaque, addr & ~0x7UL, 8); + if (addr & 0x7) { + value =3D value << 32 | (reg & 0xffffffff); + } else { + value =3D value | (reg & ~0xffffffffUL); + } + } + riscv_cbqri_cc_write(opaque, addr & ~0x7UL, value, 8); +} + +static const MemoryRegionOps riscv_cbqri_cc_ops =3D { + .read =3D riscv_cbqri_cc_read_wrapper, + .write =3D riscv_cbqri_cc_write_wrapper, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 8, +}; + +static void riscv_cbqri_cc_realize(DeviceState *dev, Error **errp) +{ + RiscvCbqriCapacityState *cc =3D RISCV_CBQRI_CC(dev); + unsigned int bmw =3D get_bmw(cc); + /* The size of the CC registers other than bmw is 40 bytes */ + unsigned int mmio_size =3D (bmw / 8) + 40; + + if (!cc->mmio_base) { + error_setg(errp, "mmio_base property not set"); + return; + } + + assert(cc->mon_counters =3D=3D NULL); + cc->mon_counters =3D g_new0(MonitorCounter, cc->nb_mcids); + + assert(cc->alloc_blockmasks =3D=3D NULL); + unsigned int blockmasks_size =3D get_blockmask_offset(cc, cc->nb_rcids= , 0); + cc->alloc_blockmasks =3D g_new0(uint64_t, blockmasks_size); + + memory_region_init_io(&cc->mmio, OBJECT(dev), &riscv_cbqri_cc_ops, + cc, TYPE_RISCV_CBQRI_CC".mmio", mmio_size); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &cc->mmio); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, cc->mmio_base); +} + +static void riscv_cbqri_cc_reset(DeviceState *dev) +{ + RiscvCbqriCapacityState *cc =3D RISCV_CBQRI_CC(dev); + + /* + * The spec requires that the reset value is 0 for the cc_mon_ctl.BUSY + * and cc_alloc_ctl.BUSY fields, and that the reset value is UNSPECIFI= ED + * for all other registers fields. + * + * Therefore, it is legal to set the entire contents of cc_mon_ctl and + * cc_alloc_ctl to 0. + */ + cc->cc_mon_ctl =3D 0; + cc->cc_alloc_ctl =3D 0; + + /* + * The capacity controllers at reset must allocate all available + * capacity to RCID value of 0. + * + * When the capacity controller supports capacity allocation per + * access-type, then all available capacity is shared by all the + * access-type for RCID=3D0. + * + * For unsupported AT values the resource controller behaves as + * if AT was 0 (CC_AT_DATA). + */ + alloc_blockmask_init(cc, 0, CC_AT_DATA, 1, NULL); + if (cc->supports_at_code) { + alloc_blockmask_init(cc, 0, CC_AT_CODE, 1, NULL); + } +} + +static Property riscv_cbqri_cc_properties[] =3D { + DEFINE_PROP_UINT64("mmio_base", RiscvCbqriCapacityState, mmio_base, 0), + DEFINE_PROP_STRING("target", RiscvCbqriCapacityState, target), + + DEFINE_PROP_UINT16("max_mcids", RiscvCbqriCapacityState, nb_mcids, 256= ), + DEFINE_PROP_UINT16("max_rcids", RiscvCbqriCapacityState, nb_rcids, 64), + DEFINE_PROP_UINT16("ncblks", RiscvCbqriCapacityState, ncblks, 16), + + DEFINE_PROP_BOOL("at_data", RiscvCbqriCapacityState, + supports_at_data, true), + DEFINE_PROP_BOOL("at_code", RiscvCbqriCapacityState, + supports_at_code, true), + + DEFINE_PROP_BOOL("alloc_op_config_limit", RiscvCbqriCapacityState, + supports_alloc_op_config_limit, true), + DEFINE_PROP_BOOL("alloc_op_read_limit", RiscvCbqriCapacityState, + supports_alloc_op_read_limit, true), + DEFINE_PROP_BOOL("alloc_op_flush_rcid", RiscvCbqriCapacityState, + supports_alloc_op_flush_rcid, true), + + DEFINE_PROP_BOOL("mon_op_config_event", RiscvCbqriCapacityState, + supports_mon_op_config_event, true), + DEFINE_PROP_BOOL("mon_op_read_counter", RiscvCbqriCapacityState, + supports_mon_op_read_counter, true), + + DEFINE_PROP_BOOL("mon_evt_id_none", RiscvCbqriCapacityState, + supports_mon_evt_id_none, true), + DEFINE_PROP_BOOL("mon_evt_id_occupancy", RiscvCbqriCapacityState, + supports_mon_evt_id_occupancy, true), +}; + +static void riscv_cbqri_cc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D riscv_cbqri_cc_realize; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc =3D "RISC-V CBQRI Capacity Controller"; + device_class_set_props(dc, riscv_cbqri_cc_properties); + dc->legacy_reset =3D riscv_cbqri_cc_reset; + dc->user_creatable =3D true; +} + +static const TypeInfo riscv_cbqri_cc_info =3D { + .name =3D TYPE_RISCV_CBQRI_CC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RiscvCbqriCapacityState), + .class_init =3D riscv_cbqri_cc_class_init, +}; + +static void riscv_cbqri_cc_register_types(void) +{ + type_register_static(&riscv_cbqri_cc_info); +} + +DeviceState *riscv_cbqri_cc_create(hwaddr addr, + const RiscvCbqriCapacityCaps *caps, + const char *target_name) +{ + DeviceState *dev =3D qdev_new(TYPE_RISCV_CBQRI_CC); + + qdev_prop_set_uint64(dev, "mmio_base", addr); + qdev_prop_set_string(dev, "target", target_name); + qdev_prop_set_uint16(dev, "max_mcids", caps->nb_mcids); + qdev_prop_set_uint16(dev, "max_rcids", caps->nb_rcids); + qdev_prop_set_uint16(dev, "ncblks", caps->ncblks); + + qdev_prop_set_bit(dev, "at_data", + caps->supports_at_data); + qdev_prop_set_bit(dev, "at_code", + caps->supports_at_code); + qdev_prop_set_bit(dev, "alloc_op_config_limit", + caps->supports_alloc_op_config_limit); + qdev_prop_set_bit(dev, "alloc_op_read_limit", + caps->supports_alloc_op_read_limit); + qdev_prop_set_bit(dev, "alloc_op_flush_rcid", + caps->supports_alloc_op_flush_rcid); + qdev_prop_set_bit(dev, "mon_op_config_event", + caps->supports_mon_op_config_event); + qdev_prop_set_bit(dev, "mon_op_read_counter", + caps->supports_mon_op_read_counter); + qdev_prop_set_bit(dev, "mon_evt_id_none", + caps->supports_mon_evt_id_none); + qdev_prop_set_bit(dev, "mon_evt_id_occupancy", + caps->supports_mon_evt_id_occupancy); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + return dev; +} + +type_init(riscv_cbqri_cc_register_types) --=20 2.43.0 From nobody Mon Feb 9 13:46:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 1 Feb 2026 23:58:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 762AEC19425; Sun, 1 Feb 2026 23:58:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769990294; bh=HVS5JYvijnQJyKEuHjIO7N2xWlOVIn8UiT/rV+Rt4ss=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=jm5L/sW1s/CHAkzGwXip0n3vTEzi3j3kr3y9qcr+SSAHlTUXuXFQBGD5YNGHOu2vq Jr0/QbYNHA5cYg2sR7ouAMBQPPXCLN6v0LYuSasEZgi6niZYRZbMOuwCKpFXZfCnWe o8rKEZ67jVzc5mchpbrqhr5ibBijT3t8z9mJ7MhKh5vKJGVwyOpv1oDTbMzy7i3iH4 tFCwy/V9HmAo/eIXfcnFpFVe8N7F9werI/wIsuBYcP5o66oRyUQ71HEMjcTVRCuTsR Lsrg3f6sHd8ovBIPqFNDfgquujMFfV0h2vyHgZIlzLZOy/G0rpw8Q1vDJSi6gNvFQD EVDb9/c7Ewvgw== From: Drew Fustini Date: Sun, 01 Feb 2026 15:58:10 -0800 Subject: [PATCH v5 4/6] hw/riscv: implement CBQRI bandwidth controller MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260201-riscv-ssqosid-cbqri-v5-4-273ea4a21703@kernel.org> References: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> In-Reply-To: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=23805; i=fustini@kernel.org; h=from:subject:message-id; bh=d6Qz76xl+Br2Ks9OXLCKQUqgV8Xcv1+lbih8SOXHUNQ=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTWv5jyP/r7mQc+P2psNJO2TSjpdtqUc2Ni9feJ3zL1I 4SWBaWod5SyMIhxMciKKbJs+pB3YYlX6NcF819sg5nDygQyhIGLUwAmcm4lw/+sDU1SmsXZW3QT QlnvVCUvuaTgb+z14vSs5BuP9om02osy/DP5dOzprQ5fsUXBu5a9bPX+Wm7eoV2a7TbFZE+gws/ 6BRwA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2600:3c0a:e001:78e:0:1991:8:25; envelope-from=fustini@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1769990380010158500 From: Nicolas Pitre Implement a bandwidth controller according to the Capacity and Bandwidth QoS Register Interface (CBQRI) which supports these capabilities: - Number of access types: 2 (code and data) - Usage monitoring operations: CONFIG_EVENT, READ_COUNTER - Event IDs supported: None, Total read/write byte count, Total read byte count, Total write byte count - Bandwidth allocation operations: CONFIG_LIMIT, READ_LIMIT Link: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 Signed-off-by: Nicolas Pitre [fustini: add fields introduced in the ratified spec: rpfx and p] Signed-off-by: Drew Fustini --- MAINTAINERS | 1 + hw/riscv/cbqri_bandwidth.c | 638 +++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 639 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 99f4c12f3b92..3c10cd154635 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -362,6 +362,7 @@ M: Nicolas Pitre M: Drew Fustini L: qemu-riscv@nongnu.org S: Supported +F: hw/riscv/cbqri_bandwidth.c F: hw/riscv/cbqri_capacity.c F: include/hw/riscv/cbqri.h =20 diff --git a/hw/riscv/cbqri_bandwidth.c b/hw/riscv/cbqri_bandwidth.c new file mode 100644 index 000000000000..f86b3bf75027 --- /dev/null +++ b/hw/riscv/cbqri_bandwidth.c @@ -0,0 +1,638 @@ +/* + * RISC-V Capacity and Bandwidth QoS Register Interface + * URL: https://github.com/riscv-non-isa/riscv-cbqri/releases/tag/v1.0 + * + * Copyright (c) 2023 BayLibre SAS + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This file contains the Bandwidth-controller QoS Register Interface. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/sysbus.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/cbqri.h" + +/* Encodings of `AT` field */ +enum { + BC_AT_DATA =3D 0, + BC_AT_CODE =3D 1, +}; + +/* Capabilities */ +REG64(BC_CAPABILITIES, 0); +FIELD(BC_CAPABILITIES, VER, 0, 8); +FIELD(BC_CAPABILITIES, VER_MINOR, 0, 4); +FIELD(BC_CAPABILITIES, VER_MAJOR, 4, 4); +FIELD(BC_CAPABILITIES, NBWBLKS, 8, 16); +FIELD(BC_CAPABILITIES, RPFX, 24, 1); +FIELD(BC_CAPABILITIES, P, 25, 4); +FIELD(BC_CAPABILITIES, MRBWB, 32, 16); + +/* Usage monitoring control */ +REG64(BC_MON_CTL, 8); +FIELD(BC_MON_CTL, OP, 0, 5); +FIELD(BC_MON_CTL, AT, 5, 3); +FIELD(BC_MON_CTL, MCID, 8, 12); +FIELD(BC_MON_CTL, EVT_ID, 20, 8); +FIELD(BC_MON_CTL, ATV, 28, 1); +FIELD(BC_MON_CTL, STATUS, 32, 7); +FIELD(BC_MON_CTL, BUSY, 39, 1); + +/* Usage monitoring operations */ +enum { + BC_MON_OP_CONFIG_EVENT =3D 1, + BC_MON_OP_READ_COUNTER =3D 2, +}; + +/* Bandwidth monitoring event ID */ +enum { + BC_EVT_ID_None =3D 0, + BC_EVT_ID_RDWR_count =3D 1, + BC_EVT_ID_RDONLY_count =3D 2, + BC_EVT_ID_WRONLY_count =3D 3, +}; + +/* BC_MON_CTL.STATUS field encodings */ +enum { + BC_MON_CTL_STATUS_SUCCESS =3D 1, + BC_MON_CTL_STATUS_INVAL_OP =3D 2, + BC_MON_CTL_STATUS_INVAL_MCID =3D 3, + BC_MON_CTL_STATUS_INVAL_EVT_ID =3D 4, + BC_MON_CTL_STATUS_INVAL_AT =3D 5, +}; + +/* Monitoring counter value */ +REG64(BC_MON_CTR_VAL, 16); +FIELD(BC_MON_CTR_VAL, CTR, 0, 62); +FIELD(BC_MON_CTR_VAL, INVALID, 62, 1); +FIELD(BC_MON_CTR_VAL, OVF, 63, 1); + +/* Bandwidth Allocation control */ +REG64(BC_ALLOC_CTL, 24); +FIELD(BC_ALLOC_CTL, OP, 0, 5); +FIELD(BC_ALLOC_CTL, AT, 5, 3); +FIELD(BC_ALLOC_CTL, RCID, 8, 12); +FIELD(BC_ALLOC_CTL, STATUS, 32, 7); +FIELD(BC_ALLOC_CTL, BUSY, 39, 1); + +/* Bandwidth allocation operations */ +enum { + BC_ALLOC_OP_CONFIG_LIMIT =3D 1, + BC_ALLOC_OP_READ_LIMIT =3D 2, +}; + +/* BC_ALLOC_CTL.STATUS field encodings */ +enum { + BC_ALLOC_STATUS_SUCCESS =3D 1, + BC_ALLOC_STATUS_INVAL_OP =3D 2, + BC_ALLOC_STATUS_INVAL_RCID =3D 3, + BC_ALLOC_STATUS_INVAL_AT =3D 4, + BC_ALLOC_STATUS_INVAL_BLKS =3D 5, +}; + +/* Bandwidth allocation */ +REG64(BC_BW_ALLOC, 32); +FIELD(BC_BW_ALLOC, Rbwb, 0, 16); +FIELD(BC_BW_ALLOC, Mweight, 20, 8); +FIELD(BC_BW_ALLOC, sharedAT, 28, 3); +FIELD(BC_BW_ALLOC, useShared, 31, 1); + + +typedef struct MonitorCounter { + uint64_t ctr_val; + int at; + int evt_id; + bool active; +} MonitorCounter; + +typedef struct BandwidthAllocation { + uint32_t Rbwb:16; + uint32_t Mweight:8; + uint32_t sharedAT:3; + bool useShared:1; +} BandwidthAllocation; + +typedef struct RiscvCbqriBandwidthState { + SysBusDevice parent_obj; + MemoryRegion mmio; + + /* cached value of some registers */ + uint64_t bc_mon_ctl; + uint64_t bc_mon_ctr_val; + uint64_t bc_alloc_ctl; + uint64_t bc_bw_alloc; + + MonitorCounter *mon_counters; + BandwidthAllocation *bw_allocations; + + /* properties */ + + uint64_t mmio_base; + char *target; + uint16_t nb_mcids; + uint16_t nb_rcids; + + uint16_t nbwblks; + uint16_t mrbwb; + + bool supports_at_data; + bool supports_at_code; + + bool supports_alloc_op_config_limit; + bool supports_alloc_op_read_limit; + + bool supports_mon_op_config_event; + bool supports_mon_op_read_counter; + + bool supports_mon_evt_id_none; + bool supports_mon_evt_id_rdwr_count; + bool supports_mon_evt_id_rdonly_count; + bool supports_mon_evt_id_wronly_count; +} RiscvCbqriBandwidthState; + +#define RISCV_CBQRI_BC(obj) \ + OBJECT_CHECK(RiscvCbqriBandwidthState, (obj), TYPE_RISCV_CBQRI_BC) + +static BandwidthAllocation *get_bw_alloc(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at) +{ + /* + * All bandwidth allocation records are contiguous to simplify + * allocation. The first one is used to hold the BC_BW_ALLOC register + * content, followed by respective records for each AT per RCID. + */ + + unsigned int nb_ats =3D 0; + nb_ats +=3D !!bc->supports_at_data; + nb_ats +=3D !!bc->supports_at_code; + nb_ats =3D MAX(nb_ats, 1); + assert(at < nb_ats); + + return &bc->bw_allocations[1 + rcid * nb_ats + at]; +} + +static uint32_t bandwidth_config(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + BandwidthAllocation *bw_alloc =3D get_bw_alloc(bc, rcid, at); + + /* + * Bandwidth is allocated in multiples of bandwidth blocks, and the + * value in Rbwb must be at least 1 and must not exceed MRBWB value. + */ + if (bc->bw_allocations[0].Rbwb < 1) { + return BC_ALLOC_STATUS_INVAL_OP; + } else if (bc->bw_allocations[0].Rbwb > bc->mrbwb) { + return BC_ALLOC_STATUS_INVAL_OP; + } + + /* Save contents of BC_BW_ALLOC register for this rcid and at */ + *bw_alloc =3D bc->bw_allocations[0]; + return BC_ALLOC_STATUS_SUCCESS; +} + +static uint32_t bandwidth_read(RiscvCbqriBandwidthState *bc, + uint32_t rcid, uint32_t at, + bool *busy) +{ + BandwidthAllocation *bw_alloc =3D get_bw_alloc(bc, rcid, at); + + /* Populate BC_BW_ALLOC register with selected content */ + bc->bw_allocations[0] =3D *bw_alloc; + return BC_ALLOC_STATUS_SUCCESS; +} + +static bool is_valid_at(RiscvCbqriBandwidthState *bc, uint32_t at) +{ + switch (at) { + case BC_AT_DATA: + return bc->supports_at_data; + case BC_AT_CODE: + return bc->supports_at_code; + default: + return false; + } +} + +static void riscv_cbqri_bc_write_mon_ctl(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (!bc->supports_mon_op_config_event && + !bc->supports_mon_op_read_counter) { + /* monitoring not supported: leave mon_ctl set to 0 */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, BC_MON_CTL, OP); + uint32_t at =3D FIELD_EX64(value, BC_MON_CTL, AT); + uint32_t mcid =3D FIELD_EX64(value, BC_MON_CTL, MCID); + uint32_t evt_id =3D FIELD_EX64(value, BC_MON_CTL, EVT_ID); + bool atv =3D FIELD_EX64(value, BC_MON_CTL, ATV); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(bc->bc_mon_ctl, BC_MON_CTL, STATUS); + bool busy =3D FIELD_EX64(bc->bc_mon_ctl, BC_MON_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + if (!bc->supports_at_data && + !bc->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (mcid >=3D bc->nb_mcids) { + status =3D BC_MON_CTL_STATUS_INVAL_MCID; + } else if (op =3D=3D BC_MON_OP_CONFIG_EVENT && + bc->supports_mon_op_config_event) { + if (evt_id =3D=3D BC_EVT_ID_None && + bc->supports_mon_evt_id_none) { + bc->mon_counters[mcid].active =3D false; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } else if ((evt_id =3D=3D BC_EVT_ID_RDWR_count && + bc->supports_mon_evt_id_rdwr_count) || + (evt_id =3D=3D BC_EVT_ID_RDONLY_count && + bc->supports_mon_evt_id_rdonly_count) || + (evt_id =3D=3D BC_EVT_ID_WRONLY_count && + bc->supports_mon_evt_id_wronly_count)) { + if (atv && !is_valid_at(bc, at)) { + status =3D BC_MON_CTL_STATUS_INVAL_AT; + } else { + bc->mon_counters[mcid].ctr_val =3D + FIELD_DP64(0, BC_MON_CTR_VAL, INVALID, 1); + bc->mon_counters[mcid].evt_id =3D evt_id; + bc->mon_counters[mcid].at =3D atv ? at : -1; + bc->mon_counters[mcid].active =3D true; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } + } else { + status =3D BC_MON_CTL_STATUS_INVAL_EVT_ID; + } + } else if (op =3D=3D BC_MON_OP_READ_COUNTER && + bc->supports_mon_op_read_counter) { + bc->bc_mon_ctr_val =3D bc->mon_counters[mcid].ctr_val; + status =3D BC_MON_CTL_STATUS_SUCCESS; + } else { + status =3D BC_MON_CTL_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, BC_MON_CTL, OP, op); + value =3D FIELD_DP64(value, BC_MON_CTL, AT, at); + value =3D FIELD_DP64(value, BC_MON_CTL, MCID, mcid); + value =3D FIELD_DP64(value, BC_MON_CTL, EVT_ID, evt_id); + value =3D FIELD_DP64(value, BC_MON_CTL, ATV, atv); + value =3D FIELD_DP64(value, BC_MON_CTL, STATUS, status); + value =3D FIELD_DP64(value, BC_MON_CTL, BUSY, busy); + bc->bc_mon_ctl =3D value; +} + +static void riscv_cbqri_bc_write_alloc_ctl(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (bc->nbwblks =3D=3D 0 || + (!bc->supports_alloc_op_config_limit && + !bc->supports_alloc_op_read_limit)) { + /* capacity allocation not supported: leave bc_alloc_ctl set to 0 = */ + return; + } + + /* extract writable fields */ + uint32_t op =3D FIELD_EX64(value, BC_ALLOC_CTL, OP); + uint32_t at =3D FIELD_EX64(value, BC_ALLOC_CTL, AT); + uint32_t rcid =3D FIELD_EX64(value, BC_ALLOC_CTL, RCID); + + /* extract read-only fields */ + uint32_t status =3D FIELD_EX64(bc->bc_alloc_ctl, BC_ALLOC_CTL, STATUS); + bool busy =3D FIELD_EX64(bc->bc_alloc_ctl, BC_ALLOC_CTL, BUSY); + + if (busy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: busy flag still set, ignored", + __func__); + return; + } + + bool atv =3D true; + if (!bc->supports_at_data && + !bc->supports_at_code) { + /* AT not supported: hardwire to 0 */ + at =3D 0; + atv =3D false; + } + + if (rcid >=3D bc->nb_rcids) { + status =3D BC_ALLOC_STATUS_INVAL_RCID; + } else if (atv && !is_valid_at(bc, at)) { + status =3D BC_ALLOC_STATUS_INVAL_AT; + } else if (op =3D=3D BC_ALLOC_OP_CONFIG_LIMIT && + bc->supports_alloc_op_config_limit) { + status =3D bandwidth_config(bc, rcid, at, &busy); + } else if (op =3D=3D BC_ALLOC_OP_READ_LIMIT && + bc->supports_alloc_op_read_limit) { + status =3D bandwidth_read(bc, rcid, at, &busy); + } else { + status =3D BC_ALLOC_STATUS_INVAL_OP; + } + + /* reconstruct updated register value */ + value =3D 0; + value =3D FIELD_DP64(value, BC_ALLOC_CTL, OP, op); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, AT, at); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, RCID, rcid); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, STATUS, status); + value =3D FIELD_DP64(value, BC_ALLOC_CTL, BUSY, busy); + bc->bc_alloc_ctl =3D value; +} + +static void riscv_cbqri_bc_write_bw_alloc(RiscvCbqriBandwidthState *bc, + uint64_t value) +{ + if (bc->nbwblks =3D=3D 0) { + /* capacity allocation not supported: leave bw_alloc set to 0 */ + return; + } + + BandwidthAllocation *bc_bw_alloc =3D &bc->bw_allocations[0]; + + /* extract writable fields */ + bc_bw_alloc->Rbwb =3D FIELD_EX64(value, BC_BW_ALLOC, Rbwb); + bc_bw_alloc->Mweight =3D FIELD_EX64(value, BC_BW_ALLOC, Mweight); + bc_bw_alloc->sharedAT =3D FIELD_EX64(value, BC_BW_ALLOC, sharedAT); + bc_bw_alloc->useShared =3D FIELD_EX64(value, BC_BW_ALLOC, useShared); + + if (!bc->supports_at_data && + !bc->supports_at_code) { + /* AT not supported: hardwire to 0 */ + bc_bw_alloc->sharedAT =3D 0; + bc_bw_alloc->useShared =3D false; + } +} + +static void riscv_cbqri_bc_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + RiscvCbqriBandwidthState *bc =3D opaque; + + assert((addr % 8) =3D=3D 0); + + switch (addr) { + case A_BC_CAPABILITIES: + /* read-only register */ + break; + case A_BC_MON_CTL: + riscv_cbqri_bc_write_mon_ctl(bc, value); + break; + case A_BC_MON_CTR_VAL: + /* read-only register */ + break; + case A_BC_ALLOC_CTL: + riscv_cbqri_bc_write_alloc_ctl(bc, value); + break; + case A_BC_BW_ALLOC: + riscv_cbqri_bc_write_bw_alloc(bc, value); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + } +} + +static uint64_t riscv_cbqri_bc_read(void *opaque, hwaddr addr, unsigned si= ze) +{ + RiscvCbqriBandwidthState *bc =3D opaque; + uint64_t value =3D 0; + + assert((addr % 8) =3D=3D 0); + + switch (addr) { + case A_BC_CAPABILITIES: + value =3D FIELD_DP64(value, BC_CAPABILITIES, VER_MAJOR, + RISCV_CBQRI_VERSION_MAJOR); + value =3D FIELD_DP64(value, BC_CAPABILITIES, VER_MINOR, + RISCV_CBQRI_VERSION_MINOR); + value =3D FIELD_DP64(value, BC_CAPABILITIES, RPFX, 0); + value =3D FIELD_DP64(value, BC_CAPABILITIES, P, 0); + value =3D FIELD_DP64(value, BC_CAPABILITIES, NBWBLKS, bc->nbwblks); + value =3D FIELD_DP64(value, BC_CAPABILITIES, MRBWB, bc->mrbwb); + break; + case A_BC_MON_CTL: + value =3D bc->bc_mon_ctl; + break; + case A_BC_MON_CTR_VAL: + value =3D bc->bc_mon_ctr_val; + break; + case A_BC_ALLOC_CTL: + value =3D bc->bc_alloc_ctl; + break; + case A_BC_BW_ALLOC: + BandwidthAllocation *bc_bw_alloc =3D &bc->bw_allocations[0]; + value =3D FIELD_DP64(value, BC_BW_ALLOC, Rbwb, bc_bw_alloc->Rbwb); + value =3D FIELD_DP64(value, BC_BW_ALLOC, Mweight, bc_bw_alloc->Mwe= ight); + value =3D FIELD_DP64(value, BC_BW_ALLOC, sharedAT, bc_bw_alloc->sh= aredAT); + value =3D FIELD_DP64(value, BC_BW_ALLOC, useShared, + bc_bw_alloc->useShared); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: out of bounds (addr=3D0x%x)", + __func__, (uint32_t)addr); + } + + return value; +} + +static uint64_t riscv_cbqri_bc_read_wrapper(void *opaque, hwaddr addr, + unsigned size) +{ + uint64_t value =3D riscv_cbqri_bc_read(opaque, addr & ~0x7UL, 8); + if (size =3D=3D 4) { + if (addr & 0x7) { + return value >> 32; + } else { + return value & 0xffffffff; + } + } + return value; +} + +static void riscv_cbqri_bc_write_wrapper(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + if (size =3D=3D 4) { + uint64_t reg =3D riscv_cbqri_bc_read(opaque, addr & ~0x7UL, 8); + if (addr & 0x7) { + value =3D value << 32 | (reg & 0xffffffff); + } else { + value =3D value | (reg & ~0xffffffffUL); + } + } + riscv_cbqri_bc_write(opaque, addr & ~0x7UL, value, 8); +} + + +static const MemoryRegionOps riscv_cbqri_bc_ops =3D { + .read =3D riscv_cbqri_bc_read_wrapper, + .write =3D riscv_cbqri_bc_write_wrapper, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 4, + .impl.max_access_size =3D 8, +}; + +static void riscv_cbqri_bc_realize(DeviceState *dev, Error **errp) +{ + RiscvCbqriBandwidthState *bc =3D RISCV_CBQRI_BC(dev); + + if (!bc->mmio_base) { + error_setg(errp, "mmio_base property not set"); + return; + } + + assert(bc->mon_counters =3D=3D NULL); + bc->mon_counters =3D g_new0(MonitorCounter, bc->nb_mcids); + + assert(bc->bw_allocations =3D=3D NULL); + BandwidthAllocation *bw_alloc_end =3D get_bw_alloc(bc, bc->nb_rcids, 0= ); + unsigned int bw_alloc_size =3D bw_alloc_end - bc->bw_allocations; + bc->bw_allocations =3D g_new0(BandwidthAllocation, bw_alloc_size); + + memory_region_init_io(&bc->mmio, OBJECT(dev), &riscv_cbqri_bc_ops, + bc, TYPE_RISCV_CBQRI_BC".mmio", 4 * 1024); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &bc->mmio); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, bc->mmio_base); +} + +static void riscv_cbqri_bc_reset(DeviceState *dev) +{ + RiscvCbqriBandwidthState *bc =3D RISCV_CBQRI_BC(dev); + + bc->bc_mon_ctl =3D 0; + bc->bc_alloc_ctl =3D 0; +} + +static Property riscv_cbqri_bc_properties[] =3D { + DEFINE_PROP_UINT64("mmio_base", RiscvCbqriBandwidthState, mmio_base, 0= ), + DEFINE_PROP_STRING("target", RiscvCbqriBandwidthState, target), + + DEFINE_PROP_UINT16("max_mcids", RiscvCbqriBandwidthState, nb_mcids, 25= 6), + DEFINE_PROP_UINT16("max_rcids", RiscvCbqriBandwidthState, nb_rcids, 64= ), + DEFINE_PROP_UINT16("nbwblks", RiscvCbqriBandwidthState, nbwblks, 1024), + DEFINE_PROP_UINT16("mrbwb", RiscvCbqriBandwidthState, mrbwb, 819), + + DEFINE_PROP_BOOL("at_data", RiscvCbqriBandwidthState, + supports_at_data, true), + DEFINE_PROP_BOOL("at_code", RiscvCbqriBandwidthState, + supports_at_code, true), + + DEFINE_PROP_BOOL("alloc_op_config_limit", RiscvCbqriBandwidthState, + supports_alloc_op_config_limit, true), + DEFINE_PROP_BOOL("alloc_op_read_limit", RiscvCbqriBandwidthState, + supports_alloc_op_read_limit, true), + + DEFINE_PROP_BOOL("mon_op_config_event", RiscvCbqriBandwidthState, + supports_mon_op_config_event, true), + DEFINE_PROP_BOOL("mon_op_read_counter", RiscvCbqriBandwidthState, + supports_mon_op_read_counter, true), + + DEFINE_PROP_BOOL("mon_evt_id_none", RiscvCbqriBandwidthState, + supports_mon_evt_id_none, true), + DEFINE_PROP_BOOL("mon_evt_id_rdwr_count", RiscvCbqriBandwidthState, + supports_mon_evt_id_rdwr_count, true), + DEFINE_PROP_BOOL("mon_evt_id_rdonly_count", RiscvCbqriBandwidthState, + supports_mon_evt_id_rdonly_count, true), + DEFINE_PROP_BOOL("mon_evt_id_wronly_count", RiscvCbqriBandwidthState, + supports_mon_evt_id_wronly_count, true), +}; + +static void riscv_cbqri_bc_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D riscv_cbqri_bc_realize; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->desc =3D "RISC-V CBQRI Bandwidth Controller"; + device_class_set_props(dc, riscv_cbqri_bc_properties); + dc->legacy_reset =3D riscv_cbqri_bc_reset; + dc->user_creatable =3D true; +} + +static const TypeInfo riscv_cbqri_bc_info =3D { + .name =3D TYPE_RISCV_CBQRI_BC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RiscvCbqriBandwidthState), + .class_init =3D riscv_cbqri_bc_class_init, +}; + +static void riscv_cbqri_bc_register_types(void) +{ + type_register_static(&riscv_cbqri_bc_info); +} + +DeviceState *riscv_cbqri_bc_create(hwaddr addr, + const RiscvCbqriBandwidthCaps *caps, + const char *target_name) +{ + DeviceState *dev =3D qdev_new(TYPE_RISCV_CBQRI_BC); + + qdev_prop_set_uint64(dev, "mmio_base", addr); + qdev_prop_set_string(dev, "target", target_name); + qdev_prop_set_uint16(dev, "max_mcids", caps->nb_mcids); + qdev_prop_set_uint16(dev, "max_rcids", caps->nb_rcids); + qdev_prop_set_uint16(dev, "nbwblks", caps->nbwblks); + + qdev_prop_set_bit(dev, "at_data", + caps->supports_at_data); + qdev_prop_set_bit(dev, "at_code", + caps->supports_at_code); + qdev_prop_set_bit(dev, "alloc_op_config_limit", + caps->supports_alloc_op_config_limit); + qdev_prop_set_bit(dev, "alloc_op_read_limit", + caps->supports_alloc_op_read_limit); + qdev_prop_set_bit(dev, "mon_op_config_event", + caps->supports_mon_op_config_event); + qdev_prop_set_bit(dev, "mon_op_read_counter", + caps->supports_mon_op_read_counter); + qdev_prop_set_bit(dev, "mon_evt_id_none", + caps->supports_mon_evt_id_none); + qdev_prop_set_bit(dev, "mon_evt_id_rdwr_count", + caps->supports_mon_evt_id_rdwr_count); + qdev_prop_set_bit(dev, "mon_evt_id_rdonly_count", + caps->supports_mon_evt_id_rdonly_count); + qdev_prop_set_bit(dev, "mon_evt_id_wronly_count", + caps->supports_mon_evt_id_wronly_count); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + return dev; +} + +type_init(riscv_cbqri_bc_register_types) --=20 2.43.0 From nobody Mon Feb 9 13:46:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1769990350; cv=none; d=zohomail.com; s=zohoarc; b=jq5LSt49Jy+nADsXoZGM+KnPWIm/JCtwSmLZN7aNEZs9qUNXQoAUvA05BJxS9ZJwecnAYk2m8s4Ut32P5nFmBOFqKbJWIVgCJSbGLFMAISKZcf8qZvnTrqNgG51V9ASnIWXI6qb4eT5Y/xVHs5mVzI8rBCjYAPxw9+O2cNgqKJ8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769990350; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260201-riscv-ssqosid-cbqri-v5-5-273ea4a21703@kernel.org> References: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> In-Reply-To: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1382; i=fustini@kernel.org; h=from:subject:message-id; bh=kehPvMBHTRUHu6S9Q2DPtFbCgSRsdDVPdSLNBUBFc4s=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTWv5iiaHQtSralKJ1ZLT5vRT4TU3+/ZOMx0ZvJTIXpE hcnZit0lLIwiHExyIopsmz6kHdhiVfo1wXzX2yDmcPKBDKEgYtTACayupmR4WZf26070icMI+RV b7QfbPdVlf7tWfIzcsXFbQorHqxlEGD47/4kYf5MA6G2JSZHN0sdM8vhf/A+sE1nv+XUTVYbdpj /ZgEA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2600:3c0a:e001:78e:0:1991:8:25; envelope-from=fustini@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1769990371261158500 From: Nicolas Pitre Add boolean property for CBQRI and imply it should be enabled for the RISC-V virt machine. Build the CBQRI controllers when RISC-V CBQRI is enabled. Signed-off-by: Nicolas Pitre Signed-off-by: Drew Fustini --- hw/riscv/Kconfig | 4 ++++ hw/riscv/meson.build | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fc9c35bd981e..663cb78b813c 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -1,3 +1,6 @@ +config RISCV_CBQRI + bool + config RISCV_IOMMU bool =20 @@ -68,6 +71,7 @@ config RISCV_VIRT select PLATFORM_BUS select ACPI select ACPI_PCI + imply RISCV_CBQRI =20 config SHAKTI_C bool diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 2a8d5b136cc4..79e15514b797 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -14,5 +14,6 @@ riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files( 'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-h= pm.c')) riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-gen= eric.c')) riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan= _kmh.c')) +riscv_ss.add(when: 'CONFIG_RISCV_CBQRI', if_true: files('cbqri_capacity.c'= , 'cbqri_bandwidth.c')) =20 hw_arch +=3D {'riscv': riscv_ss} --=20 2.43.0 From nobody Mon Feb 9 13:46:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sun, 1 Feb 2026 23:58:15 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E8A9C116D0; Sun, 1 Feb 2026 23:58:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1769990295; bh=nVXcBke4+Xpy+dP8Jn1js2x8PMSpowa0B2KjBZEzC9o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=X7NyhJqj36qLrO2gbEeM3dHS2pg3q3veFeGDHNvK58YzwBQNAABpDwNE98s8V0yb5 Tg94DTBPZ2Vu7l5SEccmg2DKNBtyD4SwwZQOaXbB+AxPEcww9x4S2KtCHJuy2IVT+m scxkAvkZ40CF/M3XlkMMPz8hsx+WAI5PsXBTbU/ThimyFqD9qu9rWsZFFzpi/blHfz X4O7XmGOgVB/k7TbTEs1EbGGRpkuKwvluzWH8pbrYaLKyUuCPZt5hS0GF9AYVnUKXv sR9wgrWTHZ3SWiFuhwiOiFmRxFYFZxS6IJ/a39KObX9Fgx38K/a6YSU/Vok6QoQlBm aT1fkUeEhBVfA== From: Drew Fustini Date: Sun, 01 Feb 2026 15:58:12 -0800 Subject: [PATCH v5 6/6] hw/riscv: add CBQRI controllers to virt machine MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260201-riscv-ssqosid-cbqri-v5-6-273ea4a21703@kernel.org> References: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> In-Reply-To: <20260201-riscv-ssqosid-cbqri-v5-0-273ea4a21703@kernel.org> To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Paolo Bonzini , Nicolas Pitre , =?utf-8?q?Kornel_Dul=C4=99ba?= , Atish Kumar Patra , Atish Patra , Vasudevan Srinivasan , =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= , yunhui cui , Chen Pei , guo.wenjia23@zte.com.cn, liu.qingtao2@zte.com.cn, Drew Fustini X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=3217; i=fustini@kernel.org; h=from:subject:message-id; bh=e3aHR89QXlGWitka8WoVRilMH1bltd7QHZqaKaGawDs=; b=owGbwMvMwCV2+43O4ZsaG3kYT6slMWTWv5iSFl0hnNNdfC/14fTr4Wm91frrvgU35VX7TKy9L 3Cj/6xaRykLgxgXg6yYIsumD3kXlniFfl0w/8U2mDmsTCBDGLg4BWAiIpcZ/tlaucsK73l2Yl37 eZu1WrzZm+Vf7vbyMFq5Z8tys20rZlgx/Pde57vd+aNdsqhV/OvMdL2l4TVhc2+fe7VxZkvndQX uWjYA X-Developer-Key: i=fustini@kernel.org; a=openpgp; fpr=1B6F948213EA489734F3997035D5CD577C1E6010 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=172.234.252.31; envelope-from=fustini@kernel.org; helo=sea.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1769990364107158500 From: Nicolas Pitre Add CBQRI controllers to the RISC-V virt machine. The device properties can be fully configured from the command line: $ qemu-system-riscv64 -M virt ... \ -device riscv.cbqri.capacity,mmio_base=3D0x04828000[,...] -device riscv.cbqri.bandwidth,mmio_base=3D0x04829000[,...] The mmio_base option is mandatory, the others are optional. Many -device arguments as wanted can be provided as long as their mmio regions don't conflict. To see all possible options: $ qemu-system-riscv64 -device riscv.cbqri.capacity,help riscv.cbqri.capacity options: alloc_op_config_limit=3D - (default: true) alloc_op_flush_rcid=3D - (default: true) alloc_op_read_limit=3D - (default: true) at_code=3D - (default: true) at_data=3D - (default: true) max_mcids=3D - (default: 256) max_rcids=3D - (default: 64) mmio_base=3D - (default: 0) mon_evt_id_none=3D - (default: true) mon_evt_id_occupancy=3D - (default: true) mon_op_config_event=3D - (default: true) mon_op_read_counter=3D - (default: true) ncblks=3D - (default: 16) target=3D $ qemu-system-riscv64 -device riscv.cbqri.bandwidth,help riscv.cbqri.bandwidth options: alloc_op_config_limit=3D - (default: true) alloc_op_read_limit=3D - (default: true) at_code=3D - (default: true) at_data=3D - (default: true) max_mcids=3D - (default: 256) max_rcids=3D - (default: 64) mmio_base=3D - (default: 0) mon_evt_id_none=3D - (default: true) mon_evt_id_rdonly_count=3D - (default: true) mon_evt_id_rdwr_count=3D - (default: true) mon_evt_id_wronly_count=3D - (default: true) mon_op_config_event=3D - (default: true) mon_op_read_counter=3D - (default: true) nbwblks=3D - (default: 1024) target=3D Boolean options correspond to hardware capabilities that can be disabled Signed-off-by: Nicolas Pitre Reviewed-by: Daniel Henrique Barboza Signed-off-by: Drew Fustini --- hw/riscv/virt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c87c169d38cd..99871119be44 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -55,6 +55,7 @@ #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" #include "hw/acpi/aml-build.h" +#include "hw/riscv/cbqri.h" #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" #include "hw/uefi/var-service-api.h" @@ -1941,6 +1942,8 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) #ifdef CONFIG_TPM machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); #endif + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RISCV_CBQRI_BC); + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RISCV_CBQRI_CC); =20 object_class_property_add_bool(oc, "aclint", virt_get_aclint, virt_set_aclint); --=20 2.43.0