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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=202.12.124.147; envelope-from=chad@jablonski.xyz; helo=fout-b4-smtp.messagingengine.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.499, PDS_OTHER_BAD_TLD=1.999, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1769784674840158500 Content-Type: text/plain; charset="utf-8" Rage 128 cards always request 64MB for their linear (framebuffer) aperture and R100 cards always request 128MB. This is regardless of the amount of physical VRAM on the board. The following are results from real hardware tests: Card VRAM PCI BAR0 CONFIG_MEMSIZE CONFIG= _APER_SIZE AGP_APER_OFFSET Reviewed-by: BALATON Zoltan ----------------------- ---- -------- -------------- ------= ---------- --------------- Rage 128 Pro Ultra TF 32MB 64MB 0x02000000 0x020= 00000 0x02000000 Rage 128 RF/SG AGP 16MB 64MB 0x01000000 0x020= 00000 0x02000000 Radeon R100 QD [Radeon 7200] 64MB 128MB 0x04000000 0x040= 00000 N/A Radeon RV100 QY [Radeon 7000/VE] 32MB 128MB 0x02000000 0x040= 00000 N/A Previously the linear aperture (BAR0) would match the VRAM size. This discrepancy caused issues with the X.org and XFree86 r128 drivers. These drivers apply a mask of 0xfc000000 (2^26 =3D 64MB) to the linear aperture address. If that address is not on a 64MB boundary the framebuffer points to an incorrect memory location. Testing shows that the Radeon R100 also has a BAR0 larger than VRAM (128MB in this case) and the X.org radeon driver also masks to 64MB. For Rage 128, CONFIG_APER_SIZE also differs from the previous value and the behavior stated in the documentation. The Rage 128 register guide states that it should contain the size of the VRAM + AGP memory. The cards tested above show that this isn't the case. These tests also included enabling/disabling AGP with 8MB of memory. It didn't change the contents of CONFIG_APER_SIZE. For both Rage 128 and R100 the CONFIG_APER_SIZE is half of the PCI BAR0 siz= e. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 16 ++++++++++++++-- hw/display/ati_int.h | 5 +++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index e9c3ad2cd1..8438a77de0 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -361,7 +361,7 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, = unsigned int size) PCI_BASE_ADDRESS_0, size) & 0xffffff= f0; break; case CONFIG_APER_SIZE: - val =3D s->vga.vram_size / 2; + val =3D memory_region_size(&s->linear_aper) / 2; break; case CONFIG_REG_1_BASE: val =3D pci_default_read_config(&s->dev, @@ -952,6 +952,7 @@ static void ati_vga_realize(PCIDevice *dev, Error **err= p) { ATIVGAState *s =3D ATI_VGA(dev); VGACommonState *vga =3D &s->vga; + uint64_t aper_size; =20 #ifndef CONFIG_PIXMAN if (s->use_pixman !=3D 0) { @@ -1011,7 +1012,18 @@ static void ati_vga_realize(PCIDevice *dev, Error **= errp) /* io space is alias to beginning of mmregs */ memory_region_init_alias(&s->io, OBJECT(s), "ati.io", &s->mm, 0, 0x100= ); =20 - pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); + /* + * The framebuffer is at the beginning of the linear aperture. For + * Rage128 the upper half of the aperture is reserved for an AGP + * window (which we do not emulate.) + */ + aper_size =3D s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF ? + ATI_RAGE128_LINEAR_APER_SIZE : ATI_R100_LINEAR_APER_SIZE; + memory_region_init(&s->linear_aper, OBJECT(dev), "ati-linear-aperture0= ", + aper_size); + memory_region_add_subregion(&s->linear_aper, 0, &vga->vram); + + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->linear_ape= r); pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io); pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mm); =20 diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index f5a47b82b0..708cc1dd3a 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -10,6 +10,7 @@ #define ATI_INT_H =20 #include "qemu/timer.h" +#include "qemu/units.h" #include "hw/pci/pci_device.h" #include "hw/i2c/bitbang_i2c.h" #include "vga_int.h" @@ -29,6 +30,9 @@ /* Radeon RV100 (VE) */ #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 =20 +#define ATI_RAGE128_LINEAR_APER_SIZE (64 * MiB) +#define ATI_R100_LINEAR_APER_SIZE (128 * MiB) + #define TYPE_ATI_VGA "ati-vga" OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA) =20 @@ -97,6 +101,7 @@ struct ATIVGAState { QEMUCursor *cursor; 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charset="utf-8" Reading DST_PITCH and SRC_PITCH on the Rage 128 is broken. The read handlers attempt to construct the value from pitch and tile bits in the register state but mistakenly AND them instead of ORing them. This means the pitch is always zero on read. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 8438a77de0..777a6b0a2e 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -438,7 +438,7 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, = unsigned int size) case DST_PITCH: val =3D s->regs.dst_pitch; if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - val &=3D s->regs.dst_tile << 16; + val |=3D s->regs.dst_tile << 16; } break; case DST_WIDTH: @@ -468,7 +468,7 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, = unsigned int size) case SRC_PITCH: val =3D s->regs.src_pitch; if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - val &=3D s->regs.src_tile << 16; + val |=3D s->regs.src_tile << 16; } break; case DP_BRUSH_BKGD_CLR: --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" DP_GUI_MASTER_CNTL aliases several fields from DP_DATATYPE and DP_MIX. These were being written correctly but not returned on a read of DP_GUI_MASTER_CNTL. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 8 +++++++- hw/display/ati_regs.h | 5 +++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 777a6b0a2e..028efd13e1 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -460,7 +460,13 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) val =3D s->regs.dst_y; break; case DP_GUI_MASTER_CNTL: - val =3D s->regs.dp_gui_master_cntl; + /* DP_GUI_MASTER_CNTL aliases fields from DP_MIX and DP_DATATYPE */ + val =3D s->regs.dp_gui_master_cntl | + ((s->regs.dp_datatype & DP_BRUSH_DATATYPE) >> 4) | + ((s->regs.dp_datatype & DP_DST_DATATYPE) << 8) | + ((s->regs.dp_datatype & DP_SRC_DATATYPE) >> 4) | + (s->regs.dp_mix & DP_ROP3) | + ((s->regs.dp_mix & DP_SRC_SOURCE) << 16); break; case SRC_OFFSET: val =3D s->regs.src_offset; diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index d7127748ff..0a0825db04 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -386,6 +386,9 @@ #define DST_16BPP 0x00000004 #define DST_24BPP 0x00000005 #define DST_32BPP 0x00000006 +#define DP_DST_DATATYPE 0x0000000f +#define DP_BRUSH_DATATYPE 0x00000f00 +#define DP_SRC_DATATYPE 0x00030000 =20 #define BRUSH_SOLIDCOLOR 0x00000d00 =20 @@ -437,6 +440,8 @@ #define DP_SRC_RECT 0x00000200 #define DP_SRC_HOST 0x00000300 #define DP_SRC_HOST_BYTEALIGN 0x00000400 +#define DP_SRC_SOURCE 0x00000700 +#define DP_ROP3 0x00ff0000 =20 /* LVDS_GEN_CNTL constants */ #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Hardware testing on the Rage 128 confirms that (SRC/DST)_OFFSET, and (SRC/DST)_PITCH are latched when (SRC/DST)_PITCH_OFFSET_CNTL bits in DP_GUI_MASTER_CNTL are set to "default". The earlier approach looked at the state of the (SRC/DST)_PITCH_OFFSET_CNTL bits when offset and pitch registers were used. This meant that when (SRC/DST)_PITCH_OFFSET_CNTL was reset to "leave alone" the old values stored in the registers would return. This is not how the real hardware works. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 9 +++++++++ hw/display/ati_2d.c | 13 ++++--------- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 028efd13e1..ce23e5e48b 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -868,6 +868,15 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dp_datatype =3D (data & 0x0f00) >> 8 | (data & 0x30f0) << = 4 | (data & 0x4000) << 16; s->regs.dp_mix =3D (data & GMC_ROP3_MASK) | (data & 0x7000000) >> = 16; + + if (!(data & GMC_SRC_PITCH_OFFSET_CNTL)) { + s->regs.src_offset =3D s->regs.default_offset; + s->regs.src_pitch =3D s->regs.default_pitch; + } + if (!(data & GMC_DST_PITCH_OFFSET_CNTL)) { + s->regs.dst_offset =3D s->regs.default_offset; + s->regs.dst_pitch =3D s->regs.default_pitch; + } break; case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 309bb5ccb6..a8c4c534b9 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -43,8 +43,6 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } =20 -#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CN= TL) - void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -63,13 +61,12 @@ void ati_2d_blt(ATIVGAState *s) qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; } - int dst_stride =3D DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_= pitch; + int dst_stride =3D s->regs.dst_pitch; if (!dst_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - uint8_t *dst_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? - s->regs.dst_offset : s->regs.default_offset); + uint8_t *dst_bits =3D s->vga.vram_ptr + s->regs.dst_offset; =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; @@ -97,14 +94,12 @@ void ati_2d_blt(ATIVGAState *s) s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_wid= th); unsigned src_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_hei= ght); - int src_stride =3D DEFAULT_CNTL ? - s->regs.src_pitch : s->regs.default_pitch; + int src_stride =3D s->regs.src_pitch; if (!src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); return; } - uint8_t *src_bits =3D s->vga.vram_ptr + (DEFAULT_CNTL ? - s->regs.src_offset : s->regs.default_offset); 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charset="utf-8" These are straightforward 32-bit register write handlers. They're necessary for a future patch which will use them for color expansion from monochrome host data transfers. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index ce23e5e48b..26fc74b19b 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -924,6 +924,12 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DP_CNTL: s->regs.dp_cntl =3D data; break; + case DP_SRC_FRGD_CLR: + s->regs.dp_src_frgd_clr =3D data; + break; + case DP_SRC_BKGD_CLR: + s->regs.dp_src_bkgd_clr =3D data; + break; case DP_DATATYPE: s->regs.dp_datatype =3D data & 0xe0070f0f; break; --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; a=rsa-sha256; t=1769784695; cv=none; d=zohomail.com; s=zohoarc; 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charset="utf-8" Implement read and write operations on SC_TOP_LEFT, SC_BOTTOM_RIGHT, and SRC_SC_BOTTOM_RIGHT registers. These registers are also updated when the src and/or dst clipping fields on DP_GUI_MASTER_CNTL are set to default clipping. Scissor clipping is used when rendering text in X.org. The r128 driver sends host data much wider than is necessary to draw a glyph and cuts it down to size using clipping before rendering. The actual clipping implementation follows in a future patch. This also includes a very minor refactor of the combined default_sc_bottom_right field in the registers struct to default_sc_bottom and default_sc_right. This was done to stay consistent with the other scissor registers and prevent repeated masking and extraction. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- v5: Removed unused default_sc_bottom_right field --- hw/display/ati.c | 70 +++++++++++++++++++++++++++++++++++++++++-- hw/display/ati_int.h | 9 +++++- hw/display/ati_regs.h | 2 ++ 3 files changed, 78 insertions(+), 3 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index 26fc74b19b..6cf243bcf9 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -514,7 +514,32 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) val |=3D s->regs.default_tile << 16; break; case DEFAULT_SC_BOTTOM_RIGHT: - val =3D s->regs.default_sc_bottom_right; + val =3D (s->regs.default_sc_bottom << 16) | + s->regs.default_sc_right; + break; + case SC_TOP: + val =3D s->regs.sc_top; + break; + case SC_LEFT: + val =3D s->regs.sc_left; + break; + case SC_BOTTOM: + val =3D s->regs.sc_bottom; + break; + case SC_RIGHT: + val =3D s->regs.sc_right; + break; + case SRC_SC_BOTTOM: + val =3D s->regs.src_sc_bottom; + break; + case SRC_SC_RIGHT: + val =3D s->regs.src_sc_right; + break; + case SC_TOP_LEFT: + case SC_BOTTOM_RIGHT: + case SRC_SC_BOTTOM_RIGHT: + qemu_log_mask(LOG_GUEST_ERROR, + "Read from write-only register 0x%x\n", (unsigned)ad= dr); break; default: break; @@ -877,6 +902,16 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dst_offset =3D s->regs.default_offset; s->regs.dst_pitch =3D s->regs.default_pitch; } + if (!(data & GMC_SRC_CLIPPING)) { + s->regs.src_sc_right =3D s->regs.default_sc_right; + s->regs.src_sc_bottom =3D s->regs.default_sc_bottom; + } + if (!(data & GMC_DST_CLIPPING)) { + s->regs.sc_top =3D 0; + s->regs.sc_left =3D 0; + s->regs.sc_right =3D s->regs.default_sc_right; + s->regs.sc_bottom =3D s->regs.default_sc_bottom; + } break; case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; @@ -956,7 +991,38 @@ static void ati_mm_write(void *opaque, hwaddr addr, } break; case DEFAULT_SC_BOTTOM_RIGHT: - s->regs.default_sc_bottom_right =3D data & 0x3fff3fff; + s->regs.default_sc_right =3D data & 0x3fff; + s->regs.default_sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SC_TOP_LEFT: + s->regs.sc_left =3D data & 0x3fff; + s->regs.sc_top =3D (data >> 16) & 0x3fff; + break; + case SC_LEFT: + s->regs.sc_left =3D data & 0x3fff; + break; + case SC_TOP: + s->regs.sc_top =3D data & 0x3fff; + break; + case SC_BOTTOM_RIGHT: + s->regs.sc_right =3D data & 0x3fff; + s->regs.sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SC_RIGHT: + s->regs.sc_right =3D data & 0x3fff; + break; + case SC_BOTTOM: + s->regs.sc_bottom =3D data & 0x3fff; + break; + case SRC_SC_BOTTOM_RIGHT: + s->regs.src_sc_right =3D data & 0x3fff; + s->regs.src_sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SRC_SC_RIGHT: + s->regs.src_sc_right =3D data & 0x3fff; + break; + case SRC_SC_BOTTOM: + s->regs.src_sc_bottom =3D data & 0x3fff; break; default: break; diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 708cc1dd3a..98f57ca5fa 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -78,14 +78,21 @@ typedef struct ATIVGARegs { uint32_t dp_brush_frgd_clr; uint32_t dp_src_frgd_clr; uint32_t dp_src_bkgd_clr; + uint16_t sc_top; + uint16_t sc_left; + uint16_t sc_bottom; + uint16_t sc_right; + uint16_t src_sc_bottom; + uint16_t src_sc_right; uint32_t dp_cntl; uint32_t dp_datatype; uint32_t dp_mix; uint32_t dp_write_mask; uint32_t default_offset; uint32_t default_pitch; + uint16_t default_sc_bottom; + uint16_t default_sc_right; uint32_t default_tile; - uint32_t default_sc_bottom_right; } ATIVGARegs; =20 struct ATIVGAState { diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 0a0825db04..3999edb9b7 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -397,6 +397,8 @@ #define GMC_DST_PITCH_OFFSET_CNTL 0x00000002 #define GMC_SRC_CLIP_DEFAULT 0x00000000 #define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIPPING 0x00000004 +#define GMC_DST_CLIPPING 0x00000008 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 #define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" The Mobility M6 register reference (DST_HEIGHT_WIDTH) states that dst_y is updated after a blit but this appears to not be the case. Hardware testing revealed that both the R128 and R100 do not update dst_x or dst_y after a blit, regardless of the source. This removes the update. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan --- hw/display/ati_2d.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index a8c4c534b9..cfc7bf9789 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -174,10 +174,6 @@ void ati_2d_blt(ATIVGAState *s) dst_y * surface_stride(ds), s->regs.dst_height * surface_stride(ds= )); } - s->regs.dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? - dst_x + s->regs.dst_width : dst_x); - s->regs.dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - dst_y + s->regs.dst_height : dst_y); break; } case ROP3_PATCOPY: @@ -228,8 +224,6 @@ void ati_2d_blt(ATIVGAState *s) dst_y * surface_stride(ds), s->regs.dst_height * surface_stride(ds= )); } - s->regs.dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - dst_y + s->regs.dst_height : dst_y); break; } default: --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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charset="utf-8" Both supported ROPs follow the same memory set dirty logic. This consolidates that logic to remove the duplication. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index cfc7bf9789..846f83e747 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -166,14 +166,6 @@ void ati_2d_blt(ATIVGAState *s) memmove(&dst_bits[i], &src_bits[j], s->regs.dst_width * by= pp); } } - if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && - dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + - s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { - memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + - s->regs.dst_offset + - dst_y * surface_stride(ds), - s->regs.dst_height * surface_stride(ds= )); - } break; } case ROP3_PATCOPY: @@ -216,18 +208,19 @@ void ati_2d_blt(ATIVGAState *s) } } } - if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && - dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + - s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset= ) { - memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + - s->regs.dst_offset + - dst_y * surface_stride(ds), - s->regs.dst_height * surface_stride(ds= )); - } break; } default: qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); + return; + } + + if (dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && + dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { + memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + + s->regs.dst_offset + dst_y * surface_strid= e(ds), + s->regs.dst_height * surface_stride(ds)); } } --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; a=rsa-sha256; t=1769784782; cv=none; d=zohomail.com; s=zohoarc; b=gyE3X7MaVjijmFZGBaiGd1J5m4fWIq0tCVJ4whpGair2KnoIUtaYQC5I13bc5YkDTkEd28yzLdBtvULS+c7cmFOSLsCeHxRFXMag04fMbiMYMxMy2602kZzATQSRCEEp4aMEPSVKdvY68w7znJ1ELY8+VaRX80VAuicCid569YE= ARC-Message-Signature: i=1; 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charset="utf-8" Pixman requires stride in words. So over the course of the ati_2d_blt function both src and dst stride were mutated before being passed to pixman and then back afterwards. This creates local variables holding src and dst stride in words avoiding the potentially confusing mutation. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 846f83e747..310b3067b4 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -72,6 +72,7 @@ void ati_2d_blt(ATIVGAState *s) dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; dst_stride *=3D bpp; } + int dst_stride_words =3D dst_stride / sizeof(uint32_t); uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >=3D end || dst_bits + dst_x @@ -105,6 +106,7 @@ void ati_2d_blt(ATIVGAState *s) src_bits +=3D s->regs.crtc_offset & 0x07ffffff; src_stride *=3D bpp; } + int src_stride_words =3D src_stride / sizeof(uint32_t); if (src_x > 0x3fff || src_y > 0x3fff || src_bits >=3D end || src_bits + src_x + (src_y + s->regs.dst_height) * src_stride >=3D end) { @@ -112,18 +114,16 @@ void ati_2d_blt(ATIVGAState *s) return; } =20 - src_stride /=3D sizeof(uint32_t); - dst_stride /=3D sizeof(uint32_t); DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", - src_bits, dst_bits, src_stride, dst_stride, bpp, bpp, - src_x, src_y, dst_x, dst_y, + src_bits, dst_bits, src_stride_words, dst_stride_words, + bpp, bpp, src_x, src_y, dst_x, dst_y, s->regs.dst_width, s->regs.dst_height); #ifdef CONFIG_PIXMAN if ((s->use_pixman & BIT(1)) && s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { fallback =3D !pixman_blt((uint32_t *)src_bits, (uint32_t *)dst= _bits, - src_stride, dst_stride, bpp, bpp, + src_stride_words, dst_stride_words, bpp= , bpp, src_x, src_y, dst_x, dst_y, s->regs.dst_width, s->regs.dst_height); } else if (s->use_pixman & BIT(1)) { @@ -133,12 +133,12 @@ void ati_2d_blt(ATIVGAState *s) uint32_t *tmp =3D g_malloc(tmp_stride * sizeof(uint32_t) * s->regs.dst_height); fallback =3D !pixman_blt((uint32_t *)src_bits, tmp, - src_stride, tmp_stride, bpp, bpp, + src_stride_words, tmp_stride, bpp, bpp, src_x, src_y, 0, 0, s->regs.dst_width, s->regs.dst_height); if (!fallback) { fallback =3D !pixman_blt(tmp, (uint32_t *)dst_bits, - tmp_stride, dst_stride, bpp, bpp, + tmp_stride, dst_stride_words, bpp, = bpp, 0, 0, dst_x, dst_y, s->regs.dst_width, s->regs.dst_heig= ht); } @@ -150,18 +150,15 @@ void ati_2d_blt(ATIVGAState *s) } if (fallback) { unsigned int y, i, j, bypp =3D bpp / 8; - unsigned int src_pitch =3D src_stride * sizeof(uint32_t); - unsigned int dst_pitch =3D dst_stride * sizeof(uint32_t); - for (y =3D 0; y < s->regs.dst_height; y++) { i =3D dst_x * bypp; j =3D src_x * bypp; if (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { - i +=3D (dst_y + y) * dst_pitch; - j +=3D (src_y + y) * src_pitch; + i +=3D (dst_y + y) * dst_stride; + j +=3D (src_y + y) * src_stride; } else { - i +=3D (dst_y + s->regs.dst_height - 1 - y) * dst_pitc= h; - j +=3D (src_y + s->regs.dst_height - 1 - y) * src_pitc= h; + i +=3D (dst_y + s->regs.dst_height - 1 - y) * dst_stri= de; + j +=3D (src_y + s->regs.dst_height - 1 - y) * src_stri= de; } memmove(&dst_bits[i], &src_bits[j], s->regs.dst_width * by= pp); } @@ -188,21 +185,20 @@ void ati_2d_blt(ATIVGAState *s) break; } =20 - dst_stride /=3D sizeof(uint32_t); DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", - dst_bits, dst_stride, bpp, dst_x, dst_y, + dst_bits, dst_stride_words, bpp, dst_x, dst_y, s->regs.dst_width, s->regs.dst_height, filler); #ifdef CONFIG_PIXMAN if (!(s->use_pixman & BIT(0)) || - !pixman_fill((uint32_t *)dst_bits, dst_stride, bpp, dst_x, dst= _y, - s->regs.dst_width, s->regs.dst_height, filler)) + !pixman_fill((uint32_t *)dst_bits, dst_stride_words, + bpp, dst_x, dst_y, + s->regs.dst_width, s->regs.dst_height, filler)) #endif { /* fallback when pixman failed or we don't want to call it */ unsigned int x, y, i, bypp =3D bpp / 8; - unsigned int dst_pitch =3D dst_stride * sizeof(uint32_t); for (y =3D 0; y < s->regs.dst_height; y++) { - i =3D dst_x * bypp + (dst_y + y) * dst_pitch; + i =3D dst_x * bypp + (dst_y + y) * dst_stride; for (x =3D 0; x < s->regs.dst_width; x++, i +=3D bypp) { stn_he_p(&dst_bits[i], bypp, filler); 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charset="utf-8" ati_2d_blt uses a mixture of locals and direct register access of needed state. This assigns all values derived from register state to local variables. It prepares the function for a larger refactor that removes the dependency on the full device and direct register access entirely. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 104 ++++++++++++++++++++++++-------------------- 1 file changed, 57 insertions(+), 47 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 310b3067b4..a368950182 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -48,14 +48,24 @@ void ati_2d_blt(ATIVGAState *s) /* FIXME it is probably more complex than this and may need to be */ /* rewritten but for now as a start just to get some output: */ DisplaySurface *ds =3D qemu_console_surface(s->vga.con); + bool use_pixman_fill =3D s->use_pixman & BIT(0); + bool use_pixman_blt =3D s->use_pixman & BIT(1); + int rop3 =3D s->regs.dp_mix & GMC_ROP3_MASK; + bool left_to_right =3D s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; + bool top_to_bottom =3D s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; + uint32_t frgd_clr =3D s->regs.dp_brush_frgd_clr; + uint8_t *palette =3D s->vga.palette; DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), - (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); - unsigned dst_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? - s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_widt= h); - unsigned dst_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_heig= ht); + rop3 >> 16); + unsigned dst_offset =3D s->regs.dst_offset; + unsigned dst_width =3D s->regs.dst_width; + unsigned dst_height =3D s->regs.dst_height; + unsigned dst_x =3D (left_to_right ? + s->regs.dst_x : s->regs.dst_x + 1 - dst_width); + unsigned dst_y =3D (top_to_bottom ? + s->regs.dst_y : s->regs.dst_y + 1 - dst_height); int bpp =3D ati_bpp_from_datatype(s); if (!bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); @@ -66,7 +76,7 @@ void ati_2d_blt(ATIVGAState *s) qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - uint8_t *dst_bits =3D s->vga.vram_ptr + s->regs.dst_offset; + uint8_t *dst_bits =3D s->vga.vram_ptr + dst_offset; =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; @@ -76,25 +86,25 @@ void ati_2d_blt(ATIVGAState *s) uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >=3D end || dst_bits + dst_x - + (dst_y + s->regs.dst_height) * dst_stride >=3D end) { + + (dst_y + dst_height) * dst_stride >=3D end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", - s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset, - s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch, + s->regs.src_offset, dst_offset, s->regs.default_offset, + s->regs.src_pitch, dst_stride, s->regs.default_pitch, s->regs.src_x, s->regs.src_y, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height, - (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'), - (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^')); - switch (s->regs.dp_mix & GMC_ROP3_MASK) { + dst_width, dst_height, + (left_to_right ? '>' : '<'), + (top_to_bottom ? 'v' : '^')); + switch (rop3) { case ROP3_SRCCOPY: { bool fallback =3D false; - unsigned src_x =3D (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? - s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_wid= th); - unsigned src_y =3D (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? - s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_hei= ght); + unsigned src_x =3D (left_to_right ? + s->regs.src_x : s->regs.src_x + 1 - dst_width); + unsigned src_y =3D (top_to_bottom ? + s->regs.src_y : s->regs.src_y + 1 - dst_height); int src_stride =3D s->regs.src_pitch; if (!src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); @@ -109,7 +119,7 @@ void ati_2d_blt(ATIVGAState *s) int src_stride_words =3D src_stride / sizeof(uint32_t); if (src_x > 0x3fff || src_y > 0x3fff || src_bits >=3D end || src_bits + src_x - + (src_y + s->regs.dst_height) * src_stride >=3D end) { + + (src_y + dst_height) * src_stride >=3D end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } @@ -117,30 +127,28 @@ void ati_2d_blt(ATIVGAState *s) DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", src_bits, dst_bits, src_stride_words, dst_stride_words, bpp, bpp, src_x, src_y, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height); + dst_width, dst_height); #ifdef CONFIG_PIXMAN - if ((s->use_pixman & BIT(1)) && - s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT && - s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { + if (use_pixman_blt && left_to_right && top_to_bottom) { fallback =3D !pixman_blt((uint32_t *)src_bits, (uint32_t *)dst= _bits, src_stride_words, dst_stride_words, bpp= , bpp, src_x, src_y, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height); - } else if (s->use_pixman & BIT(1)) { + dst_width, dst_height); + } else if (use_pixman_blt) { /* FIXME: We only really need a temporary if src and dst overl= ap */ - int llb =3D s->regs.dst_width * (bpp / 8); + int llb =3D dst_width * (bpp / 8); int tmp_stride =3D DIV_ROUND_UP(llb, sizeof(uint32_t)); uint32_t *tmp =3D g_malloc(tmp_stride * sizeof(uint32_t) * - s->regs.dst_height); + dst_height); fallback =3D !pixman_blt((uint32_t *)src_bits, tmp, src_stride_words, tmp_stride, bpp, bpp, src_x, src_y, 0, 0, - s->regs.dst_width, s->regs.dst_height); + dst_width, dst_height); if (!fallback) { fallback =3D !pixman_blt(tmp, (uint32_t *)dst_bits, tmp_stride, dst_stride_words, bpp, = bpp, 0, 0, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_heig= ht); + dst_width, dst_height); } g_free(tmp); } else @@ -150,17 +158,17 @@ void ati_2d_blt(ATIVGAState *s) } if (fallback) { unsigned int y, i, j, bypp =3D bpp / 8; - for (y =3D 0; y < s->regs.dst_height; y++) { + for (y =3D 0; y < dst_height; y++) { i =3D dst_x * bypp; j =3D src_x * bypp; - if (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) { + if (top_to_bottom) { i +=3D (dst_y + y) * dst_stride; j +=3D (src_y + y) * src_stride; } else { - i +=3D (dst_y + s->regs.dst_height - 1 - y) * dst_stri= de; - j +=3D (src_y + s->regs.dst_height - 1 - y) * src_stri= de; + i +=3D (dst_y + dst_height - 1 - y) * dst_stride; + j +=3D (src_y + dst_height - 1 - y) * src_stride; } - memmove(&dst_bits[i], &src_bits[j], s->regs.dst_width * by= pp); + memmove(&dst_bits[i], &src_bits[j], dst_width * bypp); } } break; @@ -171,35 +179,37 @@ void ati_2d_blt(ATIVGAState *s) { uint32_t filler =3D 0; =20 - switch (s->regs.dp_mix & GMC_ROP3_MASK) { + switch (rop3) { case ROP3_PATCOPY: - filler =3D s->regs.dp_brush_frgd_clr; + filler =3D frgd_clr; break; case ROP3_BLACKNESS: - filler =3D 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0], - s->vga.palette[1], s->vga.palette[2]); + filler =3D 0xffUL << 24 | rgb_to_pixel32(palette[0], + palette[1], + palette[2]); break; case ROP3_WHITENESS: - filler =3D 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3], - s->vga.palette[4], s->vga.palette[5]); + filler =3D 0xffUL << 24 | rgb_to_pixel32(palette[3], + palette[4], + palette[5]); break; } =20 DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", dst_bits, dst_stride_words, bpp, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height, filler); + dst_width, dst_height, filler); #ifdef CONFIG_PIXMAN - if (!(s->use_pixman & BIT(0)) || + if (!use_pixman_fill || !pixman_fill((uint32_t *)dst_bits, dst_stride_words, bpp, dst_x, dst_y, - s->regs.dst_width, s->regs.dst_height, filler)) + dst_width, dst_height, filler)) #endif { /* fallback when pixman failed or we don't want to call it */ unsigned int x, y, i, bypp =3D bpp / 8; - for (y =3D 0; y < s->regs.dst_height; y++) { + for (y =3D 0; y < dst_height; y++) { i =3D dst_x * bypp + (dst_y + y) * dst_stride; - for (x =3D 0; x < s->regs.dst_width; x++, i +=3D bypp) { + for (x =3D 0; x < dst_width; x++, i +=3D bypp) { stn_he_p(&dst_bits[i], bypp, filler); } } @@ -208,7 +218,7 @@ void ati_2d_blt(ATIVGAState *s) } default: qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", - (s->regs.dp_mix & GMC_ROP3_MASK) >> 16); + rop3 >> 16); return; } =20 @@ -216,7 +226,7 @@ void ati_2d_blt(ATIVGAState *s) dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + - s->regs.dst_offset + dst_y * surface_strid= e(ds), - s->regs.dst_height * surface_stride(ds)); + dst_offset + dst_y * surface_stride(ds), + dst_height * surface_stride(ds)); } } --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Previously all state derived from registers was moved to locals. Now we can mechanically replace those locals with fields on the new ATI2DCtx struct. Signed-off-by: Chad Jablonski --- vram_end feels a little out of place to me in the ATI2DCtx struct but moving it into the ctx allows us to eventually remove ATIVGAState entirely. I also considered moving the dst validation that requires it outside of ati_2d_blt and making it the responsibility of the caller but that has its own downsides (forgetting to validate). In the end I left it in the ctx. --- hw/display/ati_2d.c | 216 +++++++++++++++++++++++++------------------- 1 file changed, 122 insertions(+), 94 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index a368950182..bc41ad37f6 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -13,6 +13,7 @@ #include "qemu/log.h" #include "ui/pixel_ops.h" #include "ui/console.h" +#include "ui/rect.h" =20 /* * NOTE: @@ -43,6 +44,26 @@ static int ati_bpp_from_datatype(ATIVGAState *s) } } =20 +typedef struct { + int bpp; + uint32_t rop3; + bool left_to_right; + bool top_to_bottom; + uint32_t frgd_clr; + const uint8_t *palette; + const uint8_t *vram_end; + + /* dst */ + QemuRect dst; + int dst_stride; + uint8_t *dst_bits; + + /* src */ + QemuRect src; + int src_stride; + const uint8_t *src_bits; +} ATI2DCtx; + void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -50,105 +71,111 @@ void ati_2d_blt(ATIVGAState *s) DisplaySurface *ds =3D qemu_console_surface(s->vga.con); bool use_pixman_fill =3D s->use_pixman & BIT(0); bool use_pixman_blt =3D s->use_pixman & BIT(1); - int rop3 =3D s->regs.dp_mix & GMC_ROP3_MASK; - bool left_to_right =3D s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; - bool top_to_bottom =3D s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; - uint32_t frgd_clr =3D s->regs.dp_brush_frgd_clr; - uint8_t *palette =3D s->vga.palette; + ATI2DCtx ctx; + ctx.rop3 =3D s->regs.dp_mix & GMC_ROP3_MASK; + ctx.left_to_right =3D s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; + ctx.top_to_bottom =3D s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; + ctx.frgd_clr =3D s->regs.dp_brush_frgd_clr; + ctx.palette =3D s->vga.palette; DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), - rop3 >> 16); + ctx.rop3 >> 16); unsigned dst_offset =3D s->regs.dst_offset; - unsigned dst_width =3D s->regs.dst_width; - unsigned dst_height =3D s->regs.dst_height; - unsigned dst_x =3D (left_to_right ? - s->regs.dst_x : s->regs.dst_x + 1 - dst_width); - unsigned dst_y =3D (top_to_bottom ? - s->regs.dst_y : s->regs.dst_y + 1 - dst_height); - int bpp =3D ati_bpp_from_datatype(s); - if (!bpp) { + ctx.dst.width =3D s->regs.dst_width; + ctx.dst.height =3D s->regs.dst_height; + ctx.dst.x =3D (ctx.left_to_right ? + s->regs.dst_x : s->regs.dst_x + 1 - ctx.dst.width); + ctx.dst.y =3D (ctx.top_to_bottom ? + s->regs.dst_y : s->regs.dst_y + 1 - ctx.dst.height); + ctx.bpp =3D ati_bpp_from_datatype(s); + if (!ctx.bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; } - int dst_stride =3D s->regs.dst_pitch; - if (!dst_stride) { + ctx.dst_stride =3D s->regs.dst_pitch; + if (!ctx.dst_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - uint8_t *dst_bits =3D s->vga.vram_ptr + dst_offset; + ctx.dst_bits =3D s->vga.vram_ptr + dst_offset; =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; - dst_stride *=3D bpp; + ctx.dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; + ctx.dst_stride *=3D ctx.bpp; } - int dst_stride_words =3D dst_stride / sizeof(uint32_t); - uint8_t *end =3D s->vga.vram_ptr + s->vga.vram_size; - if (dst_x > 0x3fff || dst_y > 0x3fff || dst_bits >=3D end - || dst_bits + dst_x - + (dst_y + dst_height) * dst_stride >=3D end) { + int dst_stride_words =3D ctx.dst_stride / sizeof(uint32_t); + ctx.vram_end =3D s->vga.vram_ptr + s->vga.vram_size; + if (ctx.dst.x > 0x3fff || ctx.dst.y > 0x3fff || ctx.dst_bits >=3D ctx.= vram_end + || ctx.dst_bits + ctx.dst.x + + (ctx.dst.y + ctx.dst.height) * ctx.dst_stride >=3D ctx.vram_end= ) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", s->regs.src_offset, dst_offset, s->regs.default_offset, - s->regs.src_pitch, dst_stride, s->regs.default_pitch, - s->regs.src_x, s->regs.src_y, dst_x, dst_y, - dst_width, dst_height, - (left_to_right ? '>' : '<'), - (top_to_bottom ? 'v' : '^')); - switch (rop3) { + ctx.src_stride, ctx.dst_stride, s->regs.default_pitch, + ctx.src.x, ctx.src.y, ctx.dst.x, ctx.dst.y, + ctx.dst.width, ctx.dst.height, + (ctx.left_to_right ? '>' : '<'), + (ctx.top_to_bottom ? 'v' : '^')); + switch (ctx.rop3) { case ROP3_SRCCOPY: { bool fallback =3D false; - unsigned src_x =3D (left_to_right ? - s->regs.src_x : s->regs.src_x + 1 - dst_width); - unsigned src_y =3D (top_to_bottom ? - s->regs.src_y : s->regs.src_y + 1 - dst_height); - int src_stride =3D s->regs.src_pitch; - if (!src_stride) { + ctx.src.x =3D (ctx.left_to_right ? + s->regs.src_x : s->regs.src_x + 1 - ctx.dst.width); + ctx.src.y =3D (ctx.top_to_bottom ? + s->regs.src_y : s->regs.src_y + 1 - ctx.dst.height); + ctx.src_stride =3D s->regs.src_pitch; + if (!ctx.src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); return; } - uint8_t *src_bits =3D s->vga.vram_ptr + s->regs.src_offset; + ctx.src_bits =3D s->vga.vram_ptr + s->regs.src_offset; =20 if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - src_bits +=3D s->regs.crtc_offset & 0x07ffffff; - src_stride *=3D bpp; + ctx.src_bits +=3D s->regs.crtc_offset & 0x07ffffff; + ctx.src_stride *=3D ctx.bpp; } - int src_stride_words =3D src_stride / sizeof(uint32_t); - if (src_x > 0x3fff || src_y > 0x3fff || src_bits >=3D end - || src_bits + src_x - + (src_y + dst_height) * src_stride >=3D end) { + int src_stride_words =3D ctx.src_stride / sizeof(uint32_t); + if (ctx.src.x > 0x3fff || ctx.src.y > 0x3fff + || ctx.src_bits >=3D ctx.vram_end + || ctx.src_bits + ctx.src.x + + (ctx.src.y + ctx.dst.height) * ctx.src_stride >=3D ctx.vram= _end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } =20 DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", - src_bits, dst_bits, src_stride_words, dst_stride_words, - bpp, bpp, src_x, src_y, dst_x, dst_y, - dst_width, dst_height); + ctx.src_bits, ctx.dst_bits, src_stride_words, dst_stride_w= ords, + ctx.bpp, ctx.bpp, ctx.src.x, ctx.src.y, ctx.dst.x, ctx.dst= .y, + ctx.dst.width, ctx.dst.height); #ifdef CONFIG_PIXMAN - if (use_pixman_blt && left_to_right && top_to_bottom) { - fallback =3D !pixman_blt((uint32_t *)src_bits, (uint32_t *)dst= _bits, - src_stride_words, dst_stride_words, bpp= , bpp, - src_x, src_y, dst_x, dst_y, - dst_width, dst_height); + if (use_pixman_blt && ctx.left_to_right && ctx.top_to_bottom) { + fallback =3D !pixman_blt((uint32_t *)ctx.src_bits, + (uint32_t *)ctx.dst_bits, + src_stride_words, dst_stride_words, + ctx.bpp, ctx.bpp, + ctx.src.x, ctx.src.y, ctx.dst.x, ctx.ds= t.y, + ctx.dst.width, ctx.dst.height); } else if (use_pixman_blt) { /* FIXME: We only really need a temporary if src and dst overl= ap */ - int llb =3D dst_width * (bpp / 8); + int llb =3D ctx.dst.width * (ctx.bpp / 8); int tmp_stride =3D DIV_ROUND_UP(llb, sizeof(uint32_t)); uint32_t *tmp =3D g_malloc(tmp_stride * sizeof(uint32_t) * - dst_height); - fallback =3D !pixman_blt((uint32_t *)src_bits, tmp, - src_stride_words, tmp_stride, bpp, bpp, - src_x, src_y, 0, 0, - dst_width, dst_height); + ctx.dst.height); + fallback =3D !pixman_blt((uint32_t *)ctx.src_bits, tmp, + src_stride_words, tmp_stride, + ctx.bpp, ctx.bpp, + ctx.src.x, ctx.src.y, 0, 0, + ctx.dst.width, ctx.dst.height); if (!fallback) { - fallback =3D !pixman_blt(tmp, (uint32_t *)dst_bits, - tmp_stride, dst_stride_words, bpp, = bpp, - 0, 0, dst_x, dst_y, - dst_width, dst_height); + fallback =3D !pixman_blt(tmp, (uint32_t *)ctx.dst_bits, + tmp_stride, dst_stride_words, + ctx.bpp, ctx.bpp, + 0, 0, ctx.dst.x, ctx.dst.y, + ctx.dst.width, ctx.dst.height); } g_free(tmp); } else @@ -157,18 +184,19 @@ void ati_2d_blt(ATIVGAState *s) fallback =3D true; } if (fallback) { - unsigned int y, i, j, bypp =3D bpp / 8; - for (y =3D 0; y < dst_height; y++) { - i =3D dst_x * bypp; - j =3D src_x * bypp; - if (top_to_bottom) { - i +=3D (dst_y + y) * dst_stride; - j +=3D (src_y + y) * src_stride; + unsigned int y, i, j, bypp =3D ctx.bpp / 8; + for (y =3D 0; y < ctx.dst.height; y++) { + i =3D ctx.dst.x * bypp; + j =3D ctx.src.x * bypp; + if (ctx.top_to_bottom) { + i +=3D (ctx.dst.y + y) * ctx.dst_stride; + j +=3D (ctx.src.y + y) * ctx.src_stride; } else { - i +=3D (dst_y + dst_height - 1 - y) * dst_stride; - j +=3D (src_y + dst_height - 1 - y) * src_stride; + i +=3D (ctx.dst.y + ctx.dst.height - 1 - y) * ctx.dst_= stride; + j +=3D (ctx.src.y + ctx.dst.height - 1 - y) * ctx.src_= stride; } - memmove(&dst_bits[i], &src_bits[j], dst_width * bypp); + memmove(&ctx.dst_bits[i], &ctx.src_bits[j], + ctx.dst.width * bypp); } } break; @@ -179,38 +207,38 @@ void ati_2d_blt(ATIVGAState *s) { uint32_t filler =3D 0; =20 - switch (rop3) { + switch (ctx.rop3) { case ROP3_PATCOPY: - filler =3D frgd_clr; + filler =3D ctx.frgd_clr; break; case ROP3_BLACKNESS: - filler =3D 0xffUL << 24 | rgb_to_pixel32(palette[0], - palette[1], - palette[2]); + filler =3D 0xffUL << 24 | rgb_to_pixel32(ctx.palette[0], + ctx.palette[1], + ctx.palette[2]); break; case ROP3_WHITENESS: - filler =3D 0xffUL << 24 | rgb_to_pixel32(palette[3], - palette[4], - palette[5]); + filler =3D 0xffUL << 24 | rgb_to_pixel32(ctx.palette[3], + ctx.palette[4], + ctx.palette[5]); break; } =20 DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", - dst_bits, dst_stride_words, bpp, dst_x, dst_y, - dst_width, dst_height, filler); + ctx.dst_bits, dst_stride_words, ctx.bpp, ctx.dst.x, ctx.ds= t.y, + ctx.dst.width, ctx.dst.height, filler); #ifdef CONFIG_PIXMAN if (!use_pixman_fill || - !pixman_fill((uint32_t *)dst_bits, dst_stride_words, - bpp, dst_x, dst_y, - dst_width, dst_height, filler)) + !pixman_fill((uint32_t *)ctx.dst_bits, dst_stride_words, + ctx.bpp, ctx.dst.x, ctx.dst.y, + ctx.dst.width, ctx.dst.height, filler)) #endif { /* fallback when pixman failed or we don't want to call it */ - unsigned int x, y, i, bypp =3D bpp / 8; - for (y =3D 0; y < dst_height; y++) { - i =3D dst_x * bypp + (dst_y + y) * dst_stride; - for (x =3D 0; x < dst_width; x++, i +=3D bypp) { - stn_he_p(&dst_bits[i], bypp, filler); + unsigned int x, y, i, bypp =3D ctx.bpp / 8; + for (y =3D 0; y < ctx.dst.height; y++) { + i =3D ctx.dst.x * bypp + (ctx.dst.y + y) * ctx.dst_stride; + for (x =3D 0; x < ctx.dst.width; x++, i +=3D bypp) { + stn_he_p(&ctx.dst_bits[i], bypp, filler); } } } @@ -218,15 +246,15 @@ void ati_2d_blt(ATIVGAState *s) } default: qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", - rop3 >> 16); + ctx.rop3 >> 16); return; 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charset="utf-8" setup_2d_blt_ctx is responsible for knowing how to retrieve the state needed by ati_2d_blt from the registers and assigning it to the ATI2DCtx. This will be useful in a future patch when HOST_DATA needs to make small modifications to the ctx. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 71 +++++++++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 32 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index bc41ad37f6..4c55898e9a 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -25,7 +25,7 @@ * possible. */ =20 -static int ati_bpp_from_datatype(ATIVGAState *s) +static int ati_bpp_from_datatype(const ATIVGAState *s) { switch (s->regs.dp_datatype & 0xf) { case 2: @@ -64,6 +64,43 @@ typedef struct { const uint8_t *src_bits; } ATI2DCtx; =20 +static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx) +{ + ctx->bpp =3D ati_bpp_from_datatype(s); + ctx->rop3 =3D s->regs.dp_mix & GMC_ROP3_MASK; + ctx->left_to_right =3D s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; + ctx->top_to_bottom =3D s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; + ctx->frgd_clr =3D s->regs.dp_brush_frgd_clr; + ctx->palette =3D s->vga.palette; + ctx->vram_end =3D s->vga.vram_ptr + s->vga.vram_size; + + /* dst */ + ctx->dst.width =3D s->regs.dst_width; + ctx->dst.height =3D s->regs.dst_height; + ctx->dst.x =3D (ctx->left_to_right ? + s->regs.dst_x : s->regs.dst_x + 1 - ctx->dst.width); + ctx->dst.y =3D (ctx->top_to_bottom ? + s->regs.dst_y : s->regs.dst_y + 1 - ctx->dst.height); + ctx->dst_stride =3D s->regs.dst_pitch; + ctx->dst_bits =3D s->vga.vram_ptr + s->regs.dst_offset; + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + ctx->dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; + ctx->dst_stride *=3D ctx->bpp; + } + + /* src */ + ctx->src.x =3D (ctx->left_to_right ? + s->regs.src_x : s->regs.src_x + 1 - ctx->dst.width); + ctx->src.y =3D (ctx->top_to_bottom ? + s->regs.src_y : s->regs.src_y + 1 - ctx->dst.height); + ctx->src_stride =3D s->regs.src_pitch; + ctx->src_bits =3D s->vga.vram_ptr + s->regs.src_offset; + if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { + ctx->src_bits +=3D s->regs.crtc_offset & 0x07ffffff; + ctx->src_stride *=3D ctx->bpp; + } +} + void ati_2d_blt(ATIVGAState *s) { /* FIXME it is probably more complex than this and may need to be */ @@ -72,40 +109,21 @@ void ati_2d_blt(ATIVGAState *s) bool use_pixman_fill =3D s->use_pixman & BIT(0); bool use_pixman_blt =3D s->use_pixman & BIT(1); ATI2DCtx ctx; - ctx.rop3 =3D s->regs.dp_mix & GMC_ROP3_MASK; - ctx.left_to_right =3D s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT; - ctx.top_to_bottom =3D s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM; - ctx.frgd_clr =3D s->regs.dp_brush_frgd_clr; - ctx.palette =3D s->vga.palette; + setup_2d_blt_ctx(s, &ctx); DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), ctx.rop3 >> 16); unsigned dst_offset =3D s->regs.dst_offset; - ctx.dst.width =3D s->regs.dst_width; - ctx.dst.height =3D s->regs.dst_height; - ctx.dst.x =3D (ctx.left_to_right ? - s->regs.dst_x : s->regs.dst_x + 1 - ctx.dst.width); - ctx.dst.y =3D (ctx.top_to_bottom ? - s->regs.dst_y : s->regs.dst_y + 1 - ctx.dst.height); - ctx.bpp =3D ati_bpp_from_datatype(s); if (!ctx.bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; } - ctx.dst_stride =3D s->regs.dst_pitch; if (!ctx.dst_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - ctx.dst_bits =3D s->vga.vram_ptr + dst_offset; - - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - ctx.dst_bits +=3D s->regs.crtc_offset & 0x07ffffff; - ctx.dst_stride *=3D ctx.bpp; - } int dst_stride_words =3D ctx.dst_stride / sizeof(uint32_t); - ctx.vram_end =3D s->vga.vram_ptr + s->vga.vram_size; if (ctx.dst.x > 0x3fff || ctx.dst.y > 0x3fff || ctx.dst_bits >=3D ctx.= vram_end || ctx.dst_bits + ctx.dst.x + (ctx.dst.y + ctx.dst.height) * ctx.dst_stride >=3D ctx.vram_end= ) { @@ -123,21 +141,10 @@ void ati_2d_blt(ATIVGAState *s) case ROP3_SRCCOPY: { bool fallback =3D false; - ctx.src.x =3D (ctx.left_to_right ? - s->regs.src_x : s->regs.src_x + 1 - ctx.dst.width); - ctx.src.y =3D (ctx.top_to_bottom ? - s->regs.src_y : s->regs.src_y + 1 - ctx.dst.height); - ctx.src_stride =3D s->regs.src_pitch; if (!ctx.src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); return; } - ctx.src_bits =3D s->vga.vram_ptr + s->regs.src_offset; - - if (s->dev_id =3D=3D PCI_DEVICE_ID_ATI_RAGE128_PF) { - ctx.src_bits +=3D s->regs.crtc_offset & 0x07ffffff; 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charset="utf-8" ati_2d_blt remains the public interface to the blitter but the bulk of the implementation is moved down into ati_2d_do_blt which is passed an ATI2DCtx. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 162 ++++++++++++++++++++++++-------------------- 1 file changed, 87 insertions(+), 75 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 4c55898e9a..5ea2df1126 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -101,88 +101,90 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, AT= I2DCtx *ctx) } } =20 -void ati_2d_blt(ATIVGAState *s) +static void ati_2d_do_blt(ATIVGAState *s, ATI2DCtx *ctx) { /* FIXME it is probably more complex than this and may need to be */ /* rewritten but for now as a start just to get some output: */ DisplaySurface *ds =3D qemu_console_surface(s->vga.con); bool use_pixman_fill =3D s->use_pixman & BIT(0); bool use_pixman_blt =3D s->use_pixman & BIT(1); - ATI2DCtx ctx; - setup_2d_blt_ctx(s, &ctx); DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), - ctx.rop3 >> 16); + ctx->rop3 >> 16); unsigned dst_offset =3D s->regs.dst_offset; - if (!ctx.bpp) { + if (!ctx->bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; } - if (!ctx.dst_stride) { + if (!ctx->dst_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero dest pitch\n"); return; } - int dst_stride_words =3D ctx.dst_stride / sizeof(uint32_t); - if (ctx.dst.x > 0x3fff || ctx.dst.y > 0x3fff || ctx.dst_bits >=3D ctx.= vram_end - || ctx.dst_bits + ctx.dst.x - + (ctx.dst.y + ctx.dst.height) * ctx.dst_stride >=3D ctx.vram_end= ) { + int dst_stride_words =3D ctx->dst_stride / sizeof(uint32_t); + if (ctx->dst.x > 0x3fff || ctx->dst.y > 0x3fff + || ctx->dst_bits >=3D ctx->vram_end + || ctx->dst_bits + ctx->dst.x + + (ctx->dst.y + ctx->dst.height) * ctx->dst_stride >=3D ctx->vram= _end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", s->regs.src_offset, dst_offset, s->regs.default_offset, - ctx.src_stride, ctx.dst_stride, s->regs.default_pitch, - ctx.src.x, ctx.src.y, ctx.dst.x, ctx.dst.y, - ctx.dst.width, ctx.dst.height, - (ctx.left_to_right ? '>' : '<'), - (ctx.top_to_bottom ? 'v' : '^')); - switch (ctx.rop3) { + ctx->src_stride, ctx->dst_stride, s->regs.default_pitch, + ctx->src.x, ctx->src.y, ctx->dst.x, ctx->dst.y, + ctx->dst.width, ctx->dst.height, + (ctx->left_to_right ? '>' : '<'), + (ctx->top_to_bottom ? 'v' : '^')); + switch (ctx->rop3) { case ROP3_SRCCOPY: { bool fallback =3D false; - if (!ctx.src_stride) { + if (!ctx->src_stride) { qemu_log_mask(LOG_GUEST_ERROR, "Zero source pitch\n"); return; } - int src_stride_words =3D ctx.src_stride / sizeof(uint32_t); - if (ctx.src.x > 0x3fff || ctx.src.y > 0x3fff - || ctx.src_bits >=3D ctx.vram_end - || ctx.src_bits + ctx.src.x - + (ctx.src.y + ctx.dst.height) * ctx.src_stride >=3D ctx.vram= _end) { + int src_stride_words =3D ctx->src_stride / sizeof(uint32_t); + if (ctx->src.x > 0x3fff || ctx->src.y > 0x3fff + || ctx->src_bits >=3D ctx->vram_end + || ctx->src_bits + ctx->src.x + + (ctx->src.y + ctx->dst.height) + * ctx->src_stride >=3D ctx->vram_end) { qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } =20 DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", - ctx.src_bits, ctx.dst_bits, src_stride_words, dst_stride_w= ords, - ctx.bpp, ctx.bpp, ctx.src.x, ctx.src.y, ctx.dst.x, ctx.dst= .y, - ctx.dst.width, ctx.dst.height); + ctx->src_bits, ctx->dst_bits, + src_stride_words, dst_stride_words, ctx->bpp, ctx->bpp, + ctx->src.x, ctx->src.y, ctx->dst.x, ctx->dst.y, + ctx->dst.width, ctx->dst.height); #ifdef CONFIG_PIXMAN - if (use_pixman_blt && ctx.left_to_right && ctx.top_to_bottom) { - fallback =3D !pixman_blt((uint32_t *)ctx.src_bits, - (uint32_t *)ctx.dst_bits, + if (use_pixman_blt && ctx->left_to_right && ctx->top_to_bottom) { + fallback =3D !pixman_blt((uint32_t *)ctx->src_bits, + (uint32_t *)ctx->dst_bits, src_stride_words, dst_stride_words, - ctx.bpp, ctx.bpp, - ctx.src.x, ctx.src.y, ctx.dst.x, ctx.ds= t.y, - ctx.dst.width, ctx.dst.height); + ctx->bpp, ctx->bpp, + ctx->src.x, ctx->src.y, + ctx->dst.x, ctx->dst.y, + ctx->dst.width, ctx->dst.height); } else if (use_pixman_blt) { /* FIXME: We only really need a temporary if src and dst overl= ap */ - int llb =3D ctx.dst.width * (ctx.bpp / 8); + int llb =3D ctx->dst.width * (ctx->bpp / 8); int tmp_stride =3D DIV_ROUND_UP(llb, sizeof(uint32_t)); uint32_t *tmp =3D g_malloc(tmp_stride * sizeof(uint32_t) * - ctx.dst.height); - fallback =3D !pixman_blt((uint32_t *)ctx.src_bits, tmp, + ctx->dst.height); + fallback =3D !pixman_blt((uint32_t *)ctx->src_bits, tmp, src_stride_words, tmp_stride, - ctx.bpp, ctx.bpp, - ctx.src.x, ctx.src.y, 0, 0, - ctx.dst.width, ctx.dst.height); + ctx->bpp, ctx->bpp, + ctx->src.x, ctx->src.y, 0, 0, + ctx->dst.width, ctx->dst.height); if (!fallback) { - fallback =3D !pixman_blt(tmp, (uint32_t *)ctx.dst_bits, + fallback =3D !pixman_blt(tmp, (uint32_t *)ctx->dst_bits, tmp_stride, dst_stride_words, - ctx.bpp, ctx.bpp, - 0, 0, ctx.dst.x, ctx.dst.y, - ctx.dst.width, ctx.dst.height); + ctx->bpp, ctx->bpp, + 0, 0, ctx->dst.x, ctx->dst.y, + ctx->dst.width, ctx->dst.height); } g_free(tmp); } else @@ -191,19 +193,21 @@ void ati_2d_blt(ATIVGAState *s) fallback =3D true; } if (fallback) { - unsigned int y, i, j, bypp =3D ctx.bpp / 8; - for (y =3D 0; y < ctx.dst.height; y++) { - i =3D ctx.dst.x * bypp; - j =3D ctx.src.x * bypp; - if (ctx.top_to_bottom) { - i +=3D (ctx.dst.y + y) * ctx.dst_stride; - j +=3D (ctx.src.y + y) * ctx.src_stride; + unsigned int y, i, j, bypp =3D ctx->bpp / 8; + for (y =3D 0; y < ctx->dst.height; y++) { + i =3D ctx->dst.x * bypp; + j =3D ctx->src.x * bypp; + if (ctx->top_to_bottom) { + i +=3D (ctx->dst.y + y) * ctx->dst_stride; + j +=3D (ctx->src.y + y) * ctx->src_stride; } else { - i +=3D (ctx.dst.y + ctx.dst.height - 1 - y) * ctx.dst_= stride; - j +=3D (ctx.src.y + ctx.dst.height - 1 - y) * ctx.src_= stride; + i +=3D (ctx->dst.y + ctx->dst.height - 1 - y) + * ctx->dst_stride; + j +=3D (ctx->src.y + ctx->dst.height - 1 - y) + * ctx->src_stride; } - memmove(&ctx.dst_bits[i], &ctx.src_bits[j], - ctx.dst.width * bypp); + memmove(&ctx->dst_bits[i], &ctx->src_bits[j], + ctx->dst.width * bypp); } } break; @@ -214,38 +218,39 @@ void ati_2d_blt(ATIVGAState *s) { uint32_t filler =3D 0; =20 - switch (ctx.rop3) { + switch (ctx->rop3) { case ROP3_PATCOPY: - filler =3D ctx.frgd_clr; + filler =3D ctx->frgd_clr; break; case ROP3_BLACKNESS: - filler =3D 0xffUL << 24 | rgb_to_pixel32(ctx.palette[0], - ctx.palette[1], - ctx.palette[2]); + filler =3D 0xffUL << 24 | rgb_to_pixel32(ctx->palette[0], + ctx->palette[1], + ctx->palette[2]); break; case ROP3_WHITENESS: - filler =3D 0xffUL << 24 | rgb_to_pixel32(ctx.palette[3], - ctx.palette[4], - ctx.palette[5]); + filler =3D 0xffUL << 24 | rgb_to_pixel32(ctx->palette[3], + ctx->palette[4], + ctx->palette[5]); break; } =20 DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", - ctx.dst_bits, dst_stride_words, ctx.bpp, ctx.dst.x, ctx.ds= t.y, - ctx.dst.width, ctx.dst.height, filler); + ctx->dst_bits, dst_stride_words, ctx->bpp, + ctx->dst.x, ctx->dst.y, + ctx->dst.width, ctx->dst.height, filler); #ifdef CONFIG_PIXMAN if (!use_pixman_fill || - !pixman_fill((uint32_t *)ctx.dst_bits, dst_stride_words, - ctx.bpp, ctx.dst.x, ctx.dst.y, - ctx.dst.width, ctx.dst.height, filler)) + !pixman_fill((uint32_t *)ctx->dst_bits, dst_stride_words, + ctx->bpp, ctx->dst.x, ctx->dst.y, + ctx->dst.width, ctx->dst.height, filler)) #endif { /* fallback when pixman failed or we don't want to call it */ - unsigned int x, y, i, bypp =3D ctx.bpp / 8; - for (y =3D 0; y < ctx.dst.height; y++) { - i =3D ctx.dst.x * bypp + (ctx.dst.y + y) * ctx.dst_stride; - for (x =3D 0; x < ctx.dst.width; x++, i +=3D bypp) { - stn_he_p(&ctx.dst_bits[i], bypp, filler); + unsigned int x, y, i, bypp =3D ctx->bpp / 8; + for (y =3D 0; y < ctx->dst.height; y++) { + i =3D ctx->dst.x * bypp + (ctx->dst.y + y) * ctx->dst_stri= de; + for (x =3D 0; x < ctx->dst.width; x++, i +=3D bypp) { + stn_he_p(&ctx->dst_bits[i], bypp, filler); } } } @@ -253,15 +258,22 @@ void ati_2d_blt(ATIVGAState *s) } default: qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n", - ctx.rop3 >> 16); + ctx->rop3 >> 16); return; } =20 - if (ctx.dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && - ctx.dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + + if (ctx->dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && + ctx->dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + - dst_offset + ctx.dst.y * surface_stride(ds= ), - ctx.dst.height * surface_stride(ds)); + dst_offset + ctx->dst.y * surface_stride(d= s), + ctx->dst.height * surface_stride(ds)); } } + +void ati_2d_blt(ATIVGAState *s) +{ + ATI2DCtx ctx; + setup_2d_blt_ctx(s, &ctx); + ati_2d_do_blt(s, &ctx); +} --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; a=rsa-sha256; t=1769784783; cv=none; d=zohomail.com; s=zohoarc; b=BM4t0GvDCoo/Zcr1MYdlQOuy99qWuZn0R6fjBnVYzdbzDuy4Knff/uMOkp2mbWaYqJN7FKb4vnrE4TggmrFnTf8ILV7nTA5tXDlL46dsEuN8S8tVLxWYjr5pnJklXrfEVhpWKcmD9PeTWbXnxZz+6Ap4PX1MwAeK7a56Cnc9C6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769784783; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" This is done in preparation for the removal of the ATIVGAState *s parameter. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 5ea2df1126..39ea67aeb7 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -101,13 +101,13 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, AT= I2DCtx *ctx) } } =20 -static void ati_2d_do_blt(ATIVGAState *s, ATI2DCtx *ctx) +static void ati_2d_do_blt(ATIVGAState *s, ATI2DCtx *ctx, uint8_t use_pixma= n) { /* FIXME it is probably more complex than this and may need to be */ /* rewritten but for now as a start just to get some output: */ DisplaySurface *ds =3D qemu_console_surface(s->vga.con); - bool use_pixman_fill =3D s->use_pixman & BIT(0); - bool use_pixman_blt =3D s->use_pixman & BIT(1); + bool use_pixman_fill =3D use_pixman & BIT(0); + bool use_pixman_blt =3D use_pixman & BIT(1); DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), @@ -275,5 +275,5 @@ void ati_2d_blt(ATIVGAState *s) { ATI2DCtx ctx; setup_2d_blt_ctx(s, &ctx); - ati_2d_do_blt(s, &ctx); + ati_2d_do_blt(s, &ctx, s->use_pixman); } --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; a=rsa-sha256; t=1769784727; cv=none; d=zohomail.com; s=zohoarc; b=BMuKyDXiLCMEWJ9BcApJDmjszauIrFmf0ujwUhBLMULF+dduc0rObclR85dX1MSim1pJvwgDoLAZ/RHSvXvo7Fs3U6/X3RHwyDjEsnpvFOMhbeekzDU8ByEUqgK+WozDs087siRBICWrYglR2txcTggHFyUWJmgBK/KjJT3v5GQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769784727; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" This is done in preparation for the removal of the ATIVGAState *s parameter. It will also be used by the HOST_DATA implementation. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 39ea67aeb7..5c15c3ec70 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -64,6 +64,19 @@ typedef struct { const uint8_t *src_bits; } ATI2DCtx; =20 +static void ati_set_dirty(VGACommonState *vga, const ATI2DCtx *ctx) +{ + DisplaySurface *ds =3D qemu_console_surface(vga->con); + unsigned dst_offset =3D ctx->dst_bits - vga->vram_ptr; + if (ctx->dst_bits >=3D vga->vram_ptr + vga->vbe_start_addr && + ctx->dst_bits < vga->vram_ptr + vga->vbe_start_addr + + vga->vbe_regs[VBE_DISPI_INDEX_YRES] * vga->vbe_line_offset) { + memory_region_set_dirty(&vga->vram, vga->vbe_start_addr + + dst_offset + ctx->dst.y * surface_stride(d= s), + ctx->dst.height * surface_stride(ds)); + } +} + static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2DCtx *ctx) { ctx->bpp =3D ati_bpp_from_datatype(s); @@ -105,14 +118,12 @@ static void ati_2d_do_blt(ATIVGAState *s, ATI2DCtx *c= tx, uint8_t use_pixman) { /* FIXME it is probably more complex than this and may need to be */ /* rewritten but for now as a start just to get some output: */ - DisplaySurface *ds =3D qemu_console_surface(s->vga.con); bool use_pixman_fill =3D use_pixman & BIT(0); bool use_pixman_blt =3D use_pixman & BIT(1); DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), surface_bits_per_pixel(ds), ctx->rop3 >> 16); - unsigned dst_offset =3D s->regs.dst_offset; if (!ctx->bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; @@ -261,14 +272,6 @@ static void ati_2d_do_blt(ATIVGAState *s, ATI2DCtx *ct= x, uint8_t use_pixman) ctx->rop3 >> 16); return; } - - if (ctx->dst_bits >=3D s->vga.vram_ptr + s->vga.vbe_start_addr && - ctx->dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr + - s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) { - memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr + - dst_offset + ctx->dst.y * surface_stride(d= s), - ctx->dst.height * surface_stride(ds)); - } } =20 void ati_2d_blt(ATIVGAState *s) @@ -276,4 +279,5 @@ void ati_2d_blt(ATIVGAState *s) ATI2DCtx ctx; setup_2d_blt_ctx(s, &ctx); ati_2d_do_blt(s, &ctx, s->use_pixman); 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charset="utf-8" This completes the decoupling from the ATIVGAState struct. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 5c15c3ec70..89a9d006af 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -68,6 +68,10 @@ static void ati_set_dirty(VGACommonState *vga, const ATI= 2DCtx *ctx) { DisplaySurface *ds =3D qemu_console_surface(vga->con); unsigned dst_offset =3D ctx->dst_bits - vga->vram_ptr; + DPRINTF("%p %u ds: %p %d %d rop: %x\n", vga->vram_ptr, + vga->vbe_start_addr, surface_data(ds), surface_stride(ds), + surface_bits_per_pixel(ds), + ctx->rop3 >> 16); if (ctx->dst_bits >=3D vga->vram_ptr + vga->vbe_start_addr && ctx->dst_bits < vga->vram_ptr + vga->vbe_start_addr + vga->vbe_regs[VBE_DISPI_INDEX_YRES] * vga->vbe_line_offset) { @@ -114,16 +118,12 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, AT= I2DCtx *ctx) } } =20 -static void ati_2d_do_blt(ATIVGAState *s, ATI2DCtx *ctx, uint8_t use_pixma= n) +static void ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_pixman) { /* FIXME it is probably more complex than this and may need to be */ /* rewritten but for now as a start just to get some output: */ bool use_pixman_fill =3D use_pixman & BIT(0); bool use_pixman_blt =3D use_pixman & BIT(1); - DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr, - s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds), - surface_bits_per_pixel(ds), - ctx->rop3 >> 16); if (!ctx->bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; @@ -140,9 +140,8 @@ static void ati_2d_do_blt(ATIVGAState *s, ATI2DCtx *ctx= , uint8_t use_pixman) qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } - DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", - s->regs.src_offset, dst_offset, s->regs.default_offset, - ctx->src_stride, ctx->dst_stride, s->regs.default_pitch, + DPRINTF("%d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", + ctx->src_stride, ctx->dst_stride, ctx->src.x, ctx->src.y, ctx->dst.x, ctx->dst.y, ctx->dst.width, ctx->dst.height, (ctx->left_to_right ? '>' : '<'), @@ -278,6 +277,6 @@ void ati_2d_blt(ATIVGAState *s) { ATI2DCtx ctx; setup_2d_blt_ctx(s, &ctx); - ati_2d_do_blt(s, &ctx, s->use_pixman); + ati_2d_do_blt(&ctx, s->use_pixman); ati_set_dirty(&s->vga, &ctx); } --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=jablonski.xyz ARC-Seal: i=1; a=rsa-sha256; t=1769784672; cv=none; d=zohomail.com; s=zohoarc; b=IQ3boMiTeO+S+Sf7gKOIdjETTGrsHk8H0NNdYpN+Bu0GLyzZvijTEQEfV9G0P0VafYngW4xguxj4K1/Jynat0vajEAqUmBVX7z+oegFPXJKRRSVpJRwQaR4kVn2oqlOTG6p2zqt+5j3/KRAZuYuURN4Vi8W7uzJWRUClxOMFt6Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769784672; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" A call to ati_2d_blt implies that the source will be vram. Checking bounds is useful in that case. Other sources (HOST_DATA) will not make sense to check against vram bounds. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 89a9d006af..3ff874c3ed 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -155,14 +155,6 @@ static void ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_p= ixman) return; } int src_stride_words =3D ctx->src_stride / sizeof(uint32_t); - if (ctx->src.x > 0x3fff || ctx->src.y > 0x3fff - || ctx->src_bits >=3D ctx->vram_end - || ctx->src_bits + ctx->src.x - + (ctx->src.y + ctx->dst.height) - * ctx->src_stride >=3D ctx->vram_end) { - qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); - return; - } =20 DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", ctx->src_bits, ctx->dst_bits, @@ -277,6 +269,14 @@ void ati_2d_blt(ATIVGAState *s) { ATI2DCtx ctx; setup_2d_blt_ctx(s, &ctx); + if (ctx.src.x > 0x3fff || ctx.src.y > 0x3fff + || ctx.src_bits >=3D ctx.vram_end + || ctx.src_bits + ctx.src.x + + (ctx.src.y + ctx.dst.height) + * ctx.src_stride >=3D ctx.vram_end) { + qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); 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charset="utf-8" Use scissor registers to clip blit operations. This is required for text rendering in X using the r128 driver. Without it overly-wide glyphs are drawn and create all sorts of chaos. The visible destination rectangle (vis_dst) is the intersection of the scissor rectangle and the destination rectangle (dst). The src also needs to be offset if clipped on the top and/or left sides to ensure that src data is read correctly and appears clipped when drawn rather than shifted. Signed-off-by: Chad Jablonski --- hw/display/ati_2d.c | 80 +++++++++++++++++++++++++++++---------------- 1 file changed, 52 insertions(+), 28 deletions(-) diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 3ff874c3ed..36bed89de0 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -52,6 +52,7 @@ typedef struct { uint32_t frgd_clr; const uint8_t *palette; const uint8_t *vram_end; + QemuRect scissor; =20 /* dst */ QemuRect dst; @@ -91,6 +92,12 @@ static void setup_2d_blt_ctx(const ATIVGAState *s, ATI2D= Ctx *ctx) ctx->palette =3D s->vga.palette; ctx->vram_end =3D s->vga.vram_ptr + s->vga.vram_size; =20 + /* scissor */ + ctx->scissor.width =3D s->regs.sc_right - s->regs.sc_left + 1; + ctx->scissor.height =3D s->regs.sc_bottom - s->regs.sc_top + 1; + ctx->scissor.x =3D s->regs.sc_left; + ctx->scissor.y =3D s->regs.sc_top; + /* dst */ ctx->dst.width =3D s->regs.dst_width; ctx->dst.height =3D s->regs.dst_height; @@ -124,6 +131,7 @@ static void ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_pi= xman) /* rewritten but for now as a start just to get some output: */ bool use_pixman_fill =3D use_pixman & BIT(0); bool use_pixman_blt =3D use_pixman & BIT(1); + QemuRect vis_src, vis_dst; if (!ctx->bpp) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid bpp\n"); return; @@ -140,10 +148,26 @@ static void ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_= pixman) qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n"); return; } + qemu_rect_intersect(&ctx->dst, &ctx->scissor, &vis_dst); + if (!vis_dst.height || !vis_dst.width) { + /* Nothing is visible, completely clipped */ + return; + } + /* + * The src must be offset if clipping is applied to the dst. + * This is so that when the source is blit to a dst clipped + * on the top or left the src image is not shifted into the + * clipped region but actually clipped. + */ + vis_src.x =3D ctx->src.x + (vis_dst.x - ctx->dst.x); + vis_src.y =3D ctx->src.y + (vis_dst.y - ctx->dst.y); + vis_src.width =3D vis_dst.width; + vis_src.height =3D vis_dst.height; + DPRINTF("%d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n", ctx->src_stride, ctx->dst_stride, - ctx->src.x, ctx->src.y, ctx->dst.x, ctx->dst.y, - ctx->dst.width, ctx->dst.height, + vis_src.x, vis_src.y, vis_dst.x, vis_dst.y, + vis_dst.width, vis_dst.height, (ctx->left_to_right ? '>' : '<'), (ctx->top_to_bottom ? 'v' : '^')); switch (ctx->rop3) { @@ -159,34 +183,34 @@ static void ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_= pixman) DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d= )\n", ctx->src_bits, ctx->dst_bits, src_stride_words, dst_stride_words, ctx->bpp, ctx->bpp, - ctx->src.x, ctx->src.y, ctx->dst.x, ctx->dst.y, - ctx->dst.width, ctx->dst.height); + vis_src.x, vis_src.y, vis_dst.x, vis_dst.y, + vis_dst.width, vis_dst.height); #ifdef CONFIG_PIXMAN if (use_pixman_blt && ctx->left_to_right && ctx->top_to_bottom) { fallback =3D !pixman_blt((uint32_t *)ctx->src_bits, (uint32_t *)ctx->dst_bits, src_stride_words, dst_stride_words, ctx->bpp, ctx->bpp, - ctx->src.x, ctx->src.y, - ctx->dst.x, ctx->dst.y, - ctx->dst.width, ctx->dst.height); + vis_src.x, vis_src.y, + vis_dst.x, vis_dst.y, + vis_dst.width, vis_dst.height); } else if (use_pixman_blt) { /* FIXME: We only really need a temporary if src and dst overl= ap */ - int llb =3D ctx->dst.width * (ctx->bpp / 8); + int llb =3D vis_dst.width * (ctx->bpp / 8); int tmp_stride =3D DIV_ROUND_UP(llb, sizeof(uint32_t)); uint32_t *tmp =3D g_malloc(tmp_stride * sizeof(uint32_t) * - ctx->dst.height); + vis_dst.height); fallback =3D !pixman_blt((uint32_t *)ctx->src_bits, tmp, src_stride_words, tmp_stride, ctx->bpp, ctx->bpp, - ctx->src.x, ctx->src.y, 0, 0, - ctx->dst.width, ctx->dst.height); + vis_src.x, vis_src.y, 0, 0, + vis_dst.width, vis_dst.height); if (!fallback) { fallback =3D !pixman_blt(tmp, (uint32_t *)ctx->dst_bits, tmp_stride, dst_stride_words, ctx->bpp, ctx->bpp, - 0, 0, ctx->dst.x, ctx->dst.y, - ctx->dst.width, ctx->dst.height); + 0, 0, vis_dst.x, vis_dst.y, + vis_dst.width, vis_dst.height); } g_free(tmp); } else @@ -196,20 +220,20 @@ static void ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_= pixman) } if (fallback) { unsigned int y, i, j, bypp =3D ctx->bpp / 8; - for (y =3D 0; y < ctx->dst.height; y++) { - i =3D ctx->dst.x * bypp; - j =3D ctx->src.x * bypp; + for (y =3D 0; y < vis_dst.height; y++) { + i =3D vis_dst.x * bypp; + j =3D vis_src.x * bypp; if (ctx->top_to_bottom) { - i +=3D (ctx->dst.y + y) * ctx->dst_stride; - j +=3D (ctx->src.y + y) * ctx->src_stride; + i +=3D (vis_dst.y + y) * ctx->dst_stride; + j +=3D (vis_src.y + y) * ctx->src_stride; } else { - i +=3D (ctx->dst.y + ctx->dst.height - 1 - y) + i +=3D (vis_dst.y + vis_dst.height - 1 - y) * ctx->dst_stride; - j +=3D (ctx->src.y + ctx->dst.height - 1 - y) + j +=3D (vis_src.y + vis_dst.height - 1 - y) * ctx->src_stride; } memmove(&ctx->dst_bits[i], &ctx->src_bits[j], - ctx->dst.width * bypp); + vis_dst.width * bypp); } } break; @@ -238,20 +262,20 @@ static void ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_= pixman) =20 DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n", ctx->dst_bits, dst_stride_words, ctx->bpp, - ctx->dst.x, ctx->dst.y, - ctx->dst.width, ctx->dst.height, filler); + vis_dst.x, vis_dst.y, + vis_dst.width, vis_dst.height, filler); #ifdef CONFIG_PIXMAN if (!use_pixman_fill || !pixman_fill((uint32_t *)ctx->dst_bits, dst_stride_words, - ctx->bpp, ctx->dst.x, ctx->dst.y, - ctx->dst.width, ctx->dst.height, filler)) + ctx->bpp, vis_dst.x, vis_dst.y, + vis_dst.width, vis_dst.height, filler)) #endif { /* fallback when pixman failed or we don't want to call it */ unsigned int x, y, i, bypp =3D ctx->bpp / 8; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=202.12.124.153; envelope-from=chad@jablonski.xyz; helo=fhigh-b2-smtp.messagingengine.com X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.499, PDS_OTHER_BAD_TLD=1.999, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @jablonski.xyz) X-ZM-MESSAGEID: 1769784712457158500 Content-Type: text/plain; charset="utf-8" Writing to any of the HOST_DATA0-7 registers pushes the written data into a 128-bit accumulator. When the accumulator is full a flush is triggered to copy it to the framebuffer. A final write to HOST_DATA_LAST will also initiate a flush. The flush itself is left for the next patch. Unaligned HOST_DATA* writes result in, from what I can tell, undefined behavior on real hardware. A well-behaved driver shouldn't be doing this anyway. For that reason they are not handled here at all. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 32 ++++++++++++++++++++++++++++++++ hw/display/ati_dbg.c | 9 +++++++++ hw/display/ati_int.h | 8 ++++++++ hw/display/ati_regs.h | 9 +++++++++ 4 files changed, 58 insertions(+) diff --git a/hw/display/ati.c b/hw/display/ati.c index 6cf243bcf9..fd717044b0 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -561,6 +561,13 @@ static inline void ati_reg_write_offs(uint32_t *reg, i= nt offs, } } =20 +static void ati_host_data_reset(ATIHostDataState *hd) +{ + hd->next =3D 0; + hd->row =3D 0; + hd->col =3D 0; +} + static void ati_mm_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -836,6 +843,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, break; case DST_WIDTH: s->regs.dst_width =3D data & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DST_HEIGHT: @@ -886,6 +894,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_HEIGHT_WIDTH: s->regs.dst_width =3D data & 0x3fff; s->regs.dst_height =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DP_GUI_MASTER_CNTL: @@ -916,6 +925,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; s->regs.dst_width =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case SRC_X_Y: @@ -929,6 +939,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, case DST_WIDTH_HEIGHT: s->regs.dst_height =3D data & 0x3fff; s->regs.dst_width =3D (data >> 16) & 0x3fff; + ati_host_data_reset(&s->host_data); ati_2d_blt(s); break; case DST_HEIGHT_Y: @@ -1024,6 +1035,25 @@ static void ati_mm_write(void *opaque, hwaddr addr, case SRC_SC_BOTTOM: s->regs.src_sc_bottom =3D data & 0x3fff; break; + case HOST_DATA0: + case HOST_DATA1: + case HOST_DATA2: + case HOST_DATA3: + case HOST_DATA4: + case HOST_DATA5: + case HOST_DATA6: + case HOST_DATA7: + s->host_data.acc[s->host_data.next++] =3D data; + if (s->host_data.next >=3D 4) { + qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\= n"); + s->host_data.next =3D 0; + } + break; + case HOST_DATA_LAST: + s->host_data.acc[s->host_data.next] =3D data; + qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\n"); + ati_host_data_reset(&s->host_data); + break; default: break; } @@ -1129,6 +1159,8 @@ static void ati_vga_reset(DeviceState *dev) /* reset vga */ vga_common_reset(&s->vga); s->mode =3D VGA_MODE; + + ati_host_data_reset(&s->host_data); } =20 static void ati_vga_exit(PCIDevice *dev) diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c index 3ffa7f35df..5c799d540a 100644 --- a/hw/display/ati_dbg.c +++ b/hw/display/ati_dbg.c @@ -252,6 +252,15 @@ static struct ati_regdesc ati_reg_names[] =3D { {"MC_SRC1_CNTL", 0x19D8}, {"TEX_CNTL", 0x1800}, {"RAGE128_MPP_TB_CONFIG", 0x01c0}, + {"HOST_DATA0", 0x17c0}, + {"HOST_DATA1", 0x17c4}, + {"HOST_DATA2", 0x17c8}, + {"HOST_DATA3", 0x17cc}, + {"HOST_DATA4", 0x17d0}, + {"HOST_DATA5", 0x17d4}, + {"HOST_DATA6", 0x17d8}, + {"HOST_DATA7", 0x17dc}, + {"HOST_DATA_LAST", 0x17e0}, {NULL, -1} }; =20 diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 98f57ca5fa..ef474e366e 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -95,6 +95,13 @@ typedef struct ATIVGARegs { uint32_t default_tile; } ATIVGARegs; =20 +typedef struct ATIHostDataState { + uint32_t row; + uint32_t col; + uint32_t next; + uint32_t acc[4]; +} ATIHostDataState; + struct ATIVGAState { PCIDevice dev; VGACommonState vga; @@ -112,6 +119,7 @@ struct ATIVGAState { MemoryRegion io; MemoryRegion mm; ATIVGARegs regs; + ATIHostDataState host_data; }; =20 const char *ati_reg_name(int num); diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 3999edb9b7..48f15e9b1d 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -252,6 +252,15 @@ #define DP_T12_CNTL 0x178c #define DST_BRES_T1_LNTH 0x1790 #define DST_BRES_T2_LNTH 0x1794 +#define HOST_DATA0 0x17c0 +#define HOST_DATA1 0x17c4 +#define HOST_DATA2 0x17c8 +#define HOST_DATA3 0x17cc +#define HOST_DATA4 0x17d0 +#define HOST_DATA5 0x17d4 +#define HOST_DATA6 0x17d8 +#define HOST_DATA7 0x17dc +#define HOST_DATA_LAST 0x17e0 #define SCALE_SRC_HEIGHT_WIDTH 0x1994 #define SCALE_OFFSET_0 0x1998 #define SCALE_PITCH 0x199c --=20 2.52.0 From nobody Mon Feb 9 12:28:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Implement flushing the 128-bit HOST_DATA accumulator to VRAM to enable text rendering in X. Currently supports only the monochrome foreground/background datatype. The flush is broken up into two steps. First, expansion of the monochrome bits to the destination color depth. Then the expanded pixels are sent to the ati_2d_do_blt one scanline at a time. ati_2d_do_blt then clips and performs the blit. Signed-off-by: Chad Jablonski --- hw/display/ati.c | 4 +-- hw/display/ati_2d.c | 84 +++++++++++++++++++++++++++++++++++++++++++ hw/display/ati_int.h | 3 ++ hw/display/ati_regs.h | 4 +++ 4 files changed, 93 insertions(+), 2 deletions(-) diff --git a/hw/display/ati.c b/hw/display/ati.c index fd717044b0..514935e510 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -1045,13 +1045,13 @@ static void ati_mm_write(void *opaque, hwaddr addr, case HOST_DATA7: s->host_data.acc[s->host_data.next++] =3D data; if (s->host_data.next >=3D 4) { - qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\= n"); + ati_flush_host_data(s); s->host_data.next =3D 0; } break; case HOST_DATA_LAST: s->host_data.acc[s->host_data.next] =3D data; - qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\n"); + ati_flush_host_data(s); ati_host_data_reset(&s->host_data); break; default: diff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c index 36bed89de0..538dba145b 100644 --- a/hw/display/ati_2d.c +++ b/hw/display/ati_2d.c @@ -292,6 +292,11 @@ static void ati_2d_do_blt(ATI2DCtx *ctx, uint8_t use_p= ixman) void ati_2d_blt(ATIVGAState *s) { ATI2DCtx ctx; + uint32_t src_source =3D s->regs.dp_mix & DP_SRC_SOURCE; + if (src_source =3D=3D DP_SRC_HOST || src_source =3D=3D DP_SRC_HOST_BYT= EALIGN) { + /* HOST_DATA sources are handled by ati_flush_host_data() */ + return; + } setup_2d_blt_ctx(s, &ctx); if (ctx.src.x > 0x3fff || ctx.src.y > 0x3fff || ctx.src_bits >=3D ctx.vram_end @@ -304,3 +309,82 @@ void ati_2d_blt(ATIVGAState *s) ati_2d_do_blt(&ctx, s->use_pixman); ati_set_dirty(&s->vga, &ctx); } + +void ati_flush_host_data(ATIVGAState *s) +{ + ATI2DCtx ctx, chunk; + uint32_t fg =3D s->regs.dp_src_frgd_clr; + uint32_t bg =3D s->regs.dp_src_bkgd_clr; + unsigned bypp, row, col, idx; + uint8_t pix_buf[ATI_HOST_DATA_ACC_BITS * sizeof(uint32_t)]; + uint32_t byte_pix_order =3D s->regs.dp_datatype & DP_BYTE_PIX_ORDER; + uint32_t src_source =3D s->regs.dp_mix & DP_SRC_SOURCE; + uint32_t src_datatype =3D s->regs.dp_datatype & DP_SRC_DATATYPE; + + if (src_source !=3D DP_SRC_HOST) { + qemu_log_mask(LOG_UNIMP, "host_data_blt: only DP_SRC_HOST supporte= d\n"); + return; + } + if (src_datatype !=3D SRC_MONO_FRGD_BKGD) { + qemu_log_mask(LOG_UNIMP, + "host_data_blt: only SRC_MONO_FRGD_BKGD supported\n"= ); + return; + } + + setup_2d_blt_ctx(s, &ctx); + + if (!ctx.left_to_right || !ctx.top_to_bottom) { + qemu_log_mask(LOG_UNIMP, "host_data_blt: only L->R, T->B supported= \n"); + return; + } + + bypp =3D ctx.bpp / 8; + + /* Expand monochrome bits to color pixels */ + idx =3D 0; + for (int word =3D 0; word < 4; word++) { + for (int byte =3D 0; byte < 4; byte++) { + uint8_t byte_val =3D s->host_data.acc[word] >> (byte * 8); + for (int i =3D 0; i < 8; i++) { + int bit =3D byte_pix_order ? i : (7 - i); + bool is_fg =3D extract8(byte_val, bit, 1); + uint32_t color =3D is_fg ? fg : bg; + stn_he_p(&pix_buf[idx * bypp], bypp, color); + idx +=3D 1; + } + } + } + + /* Copy and then modify blit ctx for use in a chunked blit */ + chunk =3D ctx; + chunk.src_bits =3D pix_buf; + chunk.src.y =3D 0; + chunk.src_stride =3D ATI_HOST_DATA_ACC_BITS * bypp; + + /* Blit one scanline chunk at a time */ + row =3D s->host_data.row; + col =3D s->host_data.col; + idx =3D 0; + while (idx < ATI_HOST_DATA_ACC_BITS && row < ctx.dst.height) { + unsigned pix_in_scanline =3D MIN(ATI_HOST_DATA_ACC_BITS - idx, + ctx.dst.width - col); + chunk.src.x =3D idx; + /* Build a rect for this scanline chunk */ + chunk.dst.x =3D ctx.dst.x + col; + chunk.dst.y =3D ctx.dst.y + row; + chunk.dst.width =3D pix_in_scanline; + chunk.dst.height =3D 1; + ati_2d_do_blt(&chunk, s->use_pixman); + ati_set_dirty(&s->vga, &chunk); + idx +=3D pix_in_scanline; + col +=3D pix_in_scanline; + if (col >=3D ctx.dst.width) { + col =3D 0; + row +=3D 1; + } + } + + /* Track state of the overall blit for use by the next flush */ + s->host_data.row =3D row; + s->host_data.col =3D col; +} diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index ef474e366e..32d1e628d3 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -33,6 +33,8 @@ #define ATI_RAGE128_LINEAR_APER_SIZE (64 * MiB) #define ATI_R100_LINEAR_APER_SIZE (128 * MiB) =20 +#define ATI_HOST_DATA_ACC_BITS 128 + #define TYPE_ATI_VGA "ati-vga" OBJECT_DECLARE_SIMPLE_TYPE(ATIVGAState, ATI_VGA) =20 @@ -125,5 +127,6 @@ struct ATIVGAState { const char *ati_reg_name(int num); =20 void ati_2d_blt(ATIVGAState *s); +void ati_flush_host_data(ATIVGAState *s); =20 #endif /* ATI_INT_H */ diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 48f15e9b1d..9d08d3e956 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -397,7 +397,11 @@ #define DST_32BPP 0x00000006 #define DP_DST_DATATYPE 0x0000000f #define DP_BRUSH_DATATYPE 0x00000f00 +#define SRC_MONO_FRGD_BKGD 0x00000000 +#define SRC_MONO_FRGD 0x00010000 +#define SRC_COLOR 0x00020000 #define DP_SRC_DATATYPE 0x00030000 +#define DP_BYTE_PIX_ORDER 0x40000000 =20 #define BRUSH_SOLIDCOLOR 0x00000d00 =20 --=20 2.52.0