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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.09.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:09:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769702965; x=1770307765; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=L9xXgSAQQ0ho77YnxVcq3hL9FgFenk/Ub66527/ohzQ=; b=C2EU9eRwQy+7Q7+UmYE9Ih/TqCfYZvEtdZXDkHLHJKygP3R9wOxlbmSKCEjdBH5byO 71MgqXAojYaYjQdvGtgoFBXpcoYupO7sD7SwiDYl2GRqEBuTdZfWRvS73ypBRZXPiFvM ORuygTXBEeCJZQm4zsc0avE99ZIkgbz6zxMcxSBk5uMBQOu5d13jCknlw2DRVlEdVwdu VX5qpzrNgn0TJI1o7z4Nt9XhIpZX6U1MBZ68umPJLjqoDUAOP22JEncaKCCljh1siU/4 021YFKMsm9U2wSDxgDQIjag/szTakwfZRpvPtn9epV555qhiAPIoDaxb9PD59HClccfc AdwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769702965; x=1770307765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=L9xXgSAQQ0ho77YnxVcq3hL9FgFenk/Ub66527/ohzQ=; b=tNFIkmb1YXjpbjSC/BjN5R+QdEgJKpAEJQ9qj+P2QRzvA5+oEwiEywuPtR99OFa9dV nzSjKrxhEzchcOTUU3aZsbtR9NUDki18UytwvDbFw5v2zxEq1eVnTicMdILWZDzN3rt3 +gUdpHC7L9fbYoH9Li0yo0NKjSqJ2KgReHIybDlWVvB408SICM818Nf/LVV4AqNqDsW1 RbdMVcds7MD2QJkKJqhMJc2Y1c1P82v7P+H2E/PY9EuELUX0MQHZC1D4MMlhCPckYWTk 3bzp6V2QLd/4vWSKZBQteUG5jiSM48yuwhg7lB+QcH1nYNI5URaS+rqIJzSpjDLCFuDo W39Q== X-Gm-Message-State: AOJu0YxKE8WLbR3OxBZ7yIaec0aJyyBoP0Cls7pBnUtnJPIWxu1jwHTC tWuE2NglnE3GUJWX8LSkzvgz1dBo6qn5cVHgdZQcm1f1XA2SMMWAzh7EhtDG+LIxDnKwu+ATqHw VjN6gM0Y= X-Gm-Gg: AZuq6aKHgd8GUyEHlxQr9qsQKe6VdA8hqLUWT5qZ76lms3UL4ZHcnP/LxKrLm00sl5z oC59j+COdJ7itH/YgefTPaV86GbPOfAS/lcOsczfuoQC5qMM5QS0eeI4cEj38X0jr3kjdNeSv49 wb1XNcEpJOGd70HZ0XKgV3yHTkfazNrolDVGNmnpzyFWcMRwGNSiq4zNLlpZJ5K2n63Z1iqxTvK lI6atgWDuSGgGdv2BK97lj47he1cZ0oJG69HacK8PObejnTLNLUl5ju2vv/kmxtpU+MC0PuFBtb gca1orl9BYSpnTVMobvoYSKu7JOh2BcQwH/ZqS2oJ4gih08QXZPHAQozzvaDuXdJLew10Ll1lcB j3xCh8EC/qrQtcdB7vVWjXak6I4g8vD56utIX2AgEilGYEUrquQ/RYLGFf4EJ85E7VkT7fHRFZ0 b5kTZ+IYjq1ZHM7bu16hJAlHWfpDZYjw== X-Received: by 2002:a05:6000:26cd:b0:430:f7c9:94c3 with SMTP id ffacd0b85a97d-435f3a864dcmr188130f8f.25.1769702964597; Thu, 29 Jan 2026 08:09:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/43] hw/arm/smmu-common: Make iommu ops part of SMMUState Date: Thu, 29 Jan 2026 16:08:38 +0000 Message-ID: <20260129160917.1415092-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703251382154100 From: Shameer Kolothum Make iommu ops part of SMMUState and set to the current default smmu_ops. No functional change intended. This will allow=C2=A0SMMUv3 accel implementa= tion to set a=C2=A0different=C2=A0iommu ops later. Reviewed-by: Jonathan Cameron Reviewed-by: Nicolin Chen Reviewed-by: Eric Auger Tested-by: Zhangfei Gao Tested-by: Eric Auger Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-5-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmu-common.c | 7 +++++-- include/hw/arm/smmu-common.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 1492d7dd95..58c4452b1f 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -959,6 +959,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) "smmu-secure-memory-view"); } =20 + if (!s->iommu_ops) { + s->iommu_ops =3D &smmu_ops; + } /* * We only allow default PCIe Root Complex(pcie.0) or pxb-pcie based e= xtra * root complexes to be associated with SMMU. @@ -978,9 +981,9 @@ static void smmu_base_realize(DeviceState *dev, Error *= *errp) } =20 if (s->smmu_per_bus) { - pci_setup_iommu_per_bus(pci_bus, &smmu_ops, s); + pci_setup_iommu_per_bus(pci_bus, s->iommu_ops, s); } else { - pci_setup_iommu(pci_bus, &smmu_ops, s); + pci_setup_iommu(pci_bus, s->iommu_ops, s); } return; } diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index f5060cf36f..7b975abc25 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -166,6 +166,7 @@ struct SMMUState { AddressSpace memory_as; MemoryRegion *secure_memory; AddressSpace secure_memory_as; + const PCIIOMMUOps *iommu_ops; }; =20 struct SMMUBaseClass { --=20 2.43.0