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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e10edf62sm16762185f8f.13.2026.01.29.08.10.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 08:10:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1769703003; x=1770307803; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DUXXViwauWLkh3b067d+qkCc8ZKPqxtPhuKZgFQ3Zck=; b=wLRATYbCCU3cnYBik7NPC/wS4sEhdu26GdBCTycmXNsVlZmAbQoUpjPQRzp8SpP6zk Xhgu0X5PfI3HMVo4RPSPNTxgJAhdQfWB3OReb9tmeHFOUkXTVTD2sBVjNu350/2ROOFK Cb98xe9blK3rrx0eNAid82wvZ++znHg6yeeMJU78Gxe0OqlPL1yImNgdsPAV5yIHS9yk zzJW+uQ/poKweshP0gECsnlzrhO5SXB6myj8P6rVkeG95ZELAroLQv2Al4uGYc+oUXzx UQD3CJtsw66WlLnAUa2QAUCKwqdmQljLCIB+xUQZkRGdcR/NG4fVXqYA7nNLeK+cVwRr U6fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769703003; x=1770307803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=DUXXViwauWLkh3b067d+qkCc8ZKPqxtPhuKZgFQ3Zck=; b=OsF1y60cEtxEXX2P4ELHWOVD2X9wg4MzuC5lsfLOCpFDwjhP6SaRFu01h0+2zLl94O 7qwtD1HEMPl8ru5Wazee4tXiCR6/bmYJdNjxWpMyLCCiYQ+2TH74UjNPw3nB/uhIhV7b vu7ylCDrP54oE3c+TffXsvN0I+FeqYmKzNe93KSS04gf+J+DMkruG5oHgsVDBDtfO6mx 30S6VCwAxdRM2yHjYQf7dpkdfCngiFaVim9Qu3Z9nm/rVe9HO5tt0LFmZXTHjnIXZzCh r9R+mkbpmJ2BvODYIvXzRoAXRyQESZV4UV7RRYANjBh6O2m0nsk2ACJTZQAVNRWoy7nj Kzsg== X-Gm-Message-State: AOJu0Yyxhe138Cvn7leSWGBrMvwesExk4ukgZ9MXgCSzPYOTskpfPxKV DizL4TCRIiGT1TXbtQg0GwryhPSwt3Zs3/+an3yZcnAu3UwKFcsbPL6J/EhrNsggLwRAjbCr9mY zwoo/BNU= X-Gm-Gg: AZuq6aJtWDfa3btKaqXqrLtT0GZy6yimo2ImLdbN0/XsrRZTugb8Fxislt3JfFMsMpg CwpzGR6qatoy4vwGqKYFXAFh4MUKiDTUxVRVY3FgVY4i7FcgOl23Rod+Am6HPq1DMA1mVzoHUn6 NYxpH2TsXYWCb0T3ruoR3ebvnMjtprsnr6F3fv0ib4oydW820xfWEwGQ5rzeggxPqJJ7kZnte6L dVmB6jwCcazPmooaN3Heqs4nYcrGViIO+1V1VCJDP9cgix6cPymcByNF8DHo86cGEztHhycLN1W CU3L1r1P11av0miCpZxQXxdXi36SAMhhCQXCiOqxrtQMiVpuuBQ/hCPK+zS9ySiKmoJhxXDd+pP r3ZOid5U0gTmnmdxPulzQfGuwBbVhIRQkIyi/qF3zf8xk2MsgO06/f51v5eV0kk5sbiH9qKia3l gxepjmB2hhMzzI0TCCqVwg/6mZXAD5JA== X-Received: by 2002:a05:6000:2004:b0:430:f9c2:8500 with SMTP id ffacd0b85a97d-435f3aae815mr144730f8f.43.1769703002868; Thu, 29 Jan 2026 08:10:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/43] hw/arm/smmuv3-accel: Make SubstreamID support configurable Date: Thu, 29 Jan 2026 16:09:11 +0000 Message-ID: <20260129160917.1415092-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260129160917.1415092-1-peter.maydell@linaro.org> References: <20260129160917.1415092-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1769703223829158500 Content-Type: text/plain; charset="utf-8" From: Shameer Kolothum QEMU SMMUv3 currently reports no SubstreamID support, forcing SSID to zero. This prevents accelerated use cases such as Shared Virtual Addressing (SVA), which require multiple Stage-1 context descriptors indexed by SubstreamID. Add a new "ssidsize" property to explicitly configure the number of bits used for SubstreamIDs. A value greater than zero enables SubstreamID support and advertises PASID capability to the vIOMMU. The requested SSIDSIZE is validated against host SMMUv3 capabilities and is only supported when accel=3Don. Reviewed-by: Jonathan Cameron Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Tested-by: Eric Auger Tested-by: Zhangfei Gao Signed-off-by: Shameer Kolothum Message-id: 20260126104342.253965-38-skolothumtho@nvidia.com Signed-off-by: Peter Maydell --- hw/arm/smmuv3-accel.c | 25 ++++++++++++++++++++++++- hw/arm/smmuv3.c | 22 ++++++++++++++++++++-- include/hw/arm/smmuv3-common.h | 1 + include/hw/arm/smmuv3.h | 1 + 4 files changed, 46 insertions(+), 3 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 342944da23..f5cd4df336 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -76,6 +76,16 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, return false; } =20 + /* Check SSIDSIZE value opted-in is compatible with Host SMMUv3 SSIDSI= ZE */ + if (FIELD_EX32(info->idr[1], IDR1, SSIDSIZE) < + FIELD_EX32(s->idr[1], IDR1, SSIDSIZE)) { + error_setg(errp, "Host SMMUv3 SSIDSIZE not compatible " + "(host=3D%u, QEMU=3D%u)", + FIELD_EX32(info->idr[1], IDR1, SSIDSIZE), + FIELD_EX32(s->idr[1], IDR1, SSIDSIZE)); + return false; + } + /* User can disable QEMU SMMUv3 Range Invalidation support */ if (FIELD_EX32(info->idr[3], IDR3, RIL) < FIELD_EX32(s->idr[3], IDR3, RIL)) { @@ -652,7 +662,14 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *op= aque) * The real HW nested support should be reported from host SMMUv3 and = if * it doesn't, the nesting parent allocation will fail anyway in VFIO = core. */ - return VIOMMU_FLAG_WANT_NESTING_PARENT; + uint64_t flags =3D VIOMMU_FLAG_WANT_NESTING_PARENT; + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + + if (s->ssidsize) { + flags |=3D VIOMMU_FLAG_PASID_SUPPORTED; + } + return flags; } =20 static const PCIIOMMUOps smmuv3_accel_ops =3D { @@ -680,6 +697,12 @@ void smmuv3_accel_idr_override(SMMUv3State *s) if (s->oas =3D=3D SMMU_OAS_48BIT) { s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } + + /* + * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if u= ser + * has enabled it. + */ + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize); } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index cb02184d2d..c08d58c579 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -611,9 +611,11 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cf= g, } } =20 - if (STE_S1CDMAX(ste) !=3D 0) { + /* Multiple context descriptors require SubstreamID support */ + if (!s->ssidsize && STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, - "SMMUv3 does not support multiple context descriptor= s yet\n"); + "SMMUv3: multiple S1 context descriptors require Substream= ID support. " + "Configure ssidsize > 0 (requires accel=3Don)\n"); goto bad_ste; } =20 @@ -1954,6 +1956,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } + if (s->ssidsize) { + error_setg(errp, "ssidsize can only be set if accel=3Don"); + return false; + } return true; } =20 @@ -1968,6 +1974,11 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; } + if (s->ssidsize > SMMU_SSID_MAX_BITS) { + error_setg(errp, "ssidsize must be in the range 0 to %d", + SMMU_SSID_MAX_BITS); + return false; + } =20 return true; } @@ -2096,6 +2107,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2129,6 +2141,12 @@ static void smmuv3_class_init(ObjectClass *klass, co= nst void *data) object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " "are 44 or 48 bits. Defaults to 44 bits"); + object_class_property_set_description(klass, "ssidsize", + "Number of bits used to represent SubstreamIDs (SSIDs). " + "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " + "Valid range is 0-20, where 0 disables SubstreamID support. " + "Defaults to 0. A value greater than 0 is required to enable " + "PASID support."); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index abe3565357..67a23fbeaa 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -311,6 +311,7 @@ REG32(IDR1, 0x4) FIELD(IDR1, TABLES_PRESET, 30, 1) FIELD(IDR1, ECMDQ, 31, 1) =20 +#define SMMU_SSID_MAX_BITS 20 #define SMMU_IDR1_SIDSIZE 16 #define SMMU_CMDQS 19 #define SMMU_EVENTQS 19 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d488a39cd0..26b2fc42fd 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -72,6 +72,7 @@ struct SMMUv3State { bool ril; bool ats; uint8_t oas; + uint8_t ssidsize; }; =20 typedef enum { --=20 2.43.0